------------- Classes -----------------
class A57WriteLMOpsListType<list<SchedWriteRes> A57WriteLMOpsListType:writes = ?> {
  list<SchedWriteRes> Writes = A57WriteLMOpsListType:writes;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class A9WriteLMOpsListType<list<WriteSequence> A9WriteLMOpsListType:writes = ?> {
  list<WriteSequence> Writes = A9WriteLMOpsListType:writes;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class AAI<bits<8> AAI:op27_20 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<8> AAI:op11_4 = { ?, ?, ?, ?, ?, ?, ?, ? }, string AAI:opc = ?, list<dag> AAI:pattern = [], dag AAI:iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), string AAI:asm = "	$Rd, $Rn, $Rm"> {	// Instruction InstTemplate Encoding InstARM I AI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AAI:op27_20{7}, AAI:op27_20{6}, AAI:op27_20{5}, AAI:op27_20{4}, AAI:op27_20{3}, AAI:op27_20{2}, AAI:op27_20{1}, AAI:op27_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, AAI:op11_4{7}, AAI:op11_4{6}, AAI:op11_4{5}, AAI:op11_4{4}, AAI:op11_4{3}, AAI:op11_4{2}, AAI:op11_4{1}, AAI:op11_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = !con(AAI:iops, (ins pred:$p));
  string AsmString = !strconcat(AAI:opc, !strconcat("${p}", AAI:asm));
  list<dag> Pattern = AAI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = DPFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class AAIIntrinsic<bits<8> AAIIntrinsic:op27_20 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<8> AAIIntrinsic:op11_4 = { ?, ?, ?, ?, ?, ?, ?, ? }, string AAIIntrinsic:opc = ?, Intrinsic AAIIntrinsic:intrinsic = ?> {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AAIIntrinsic:op27_20{7}, AAIIntrinsic:op27_20{6}, AAIIntrinsic:op27_20{5}, AAIIntrinsic:op27_20{4}, AAIIntrinsic:op27_20{3}, AAIIntrinsic:op27_20{2}, AAIIntrinsic:op27_20{1}, AAIIntrinsic:op27_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, AAIIntrinsic:op11_4{7}, AAIIntrinsic:op11_4{6}, AAIIntrinsic:op11_4{5}, AAIIntrinsic:op11_4{4}, AAIIntrinsic:op11_4{3}, AAIIntrinsic:op11_4{2}, AAIIntrinsic:op11_4{1}, AAIIntrinsic:op11_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = !strconcat(AAIIntrinsic:opc, "${p}	$Rd, $Rn, $Rm");
  list<dag> Pattern = [(set GPRnopc:$Rd, (AAIIntrinsic:intrinsic GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = DPFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class AAIRevOpr<bits<8> AAIRevOpr:op27_20 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<8> AAIRevOpr:op11_4 = { ?, ?, ?, ?, ?, ?, ?, ? }, string AAIRevOpr:opc = ?, list<dag> AAIRevOpr:pattern = []> {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AAIRevOpr:op27_20{7}, AAIRevOpr:op27_20{6}, AAIRevOpr:op27_20{5}, AAIRevOpr:op27_20{4}, AAIRevOpr:op27_20{3}, AAIRevOpr:op27_20{2}, AAIRevOpr:op27_20{1}, AAIRevOpr:op27_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, AAIRevOpr:op11_4{7}, AAIRevOpr:op11_4{6}, AAIRevOpr:op11_4{5}, AAIRevOpr:op11_4{4}, AAIRevOpr:op11_4{3}, AAIRevOpr:op11_4{2}, AAIRevOpr:op11_4{1}, AAIRevOpr:op11_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, GPRnopc:$Rn, pred:$p);
  string AsmString = !strconcat(AAIRevOpr:opc, "${p}	$Rd, $Rm, $Rn");
  list<dag> Pattern = AAIRevOpr:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = DPFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class ABI<bits<4> ABI:opcod = { ?, ?, ?, ? }, dag ABI:oops = ?, dag ABI:iops = ?, InstrItinClass ABI:itin = ?, string ABI:opc = ?, string ABI:asm = ?, list<dag> ABI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ABI:opcod{3}, ABI:opcod{2}, ABI:opcod{1}, ABI:opcod{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ABI:oops;
  dag InOperandList = !con(ABI:iops, (ins pred:$p));
  string AsmString = !strconcat(ABI:opc, !strconcat("${p}", ABI:asm));
  list<dag> Pattern = ABI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ABI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class ABXI<bits<4> ABXI:opcod = { ?, ?, ?, ? }, dag ABXI:oops = ?, dag ABXI:iops = ?, InstrItinClass ABXI:itin = ?, string ABXI:asm = ?, list<dag> ABXI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM XI
  field bits<32> Inst = { ?, ?, ?, ?, ABXI:opcod{3}, ABXI:opcod{2}, ABXI:opcod{1}, ABXI:opcod{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ABXI:oops;
  dag InOperandList = ABXI:iops;
  string AsmString = ABXI:asm;
  list<dag> Pattern = ABXI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ABXI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class ACI<dag ACI:oops = ?, dag ACI:iops = ?, string ACI:opc = ?, string ACI:asm = ?, list<dag> ACI:pattern = ?, IndexMode ACI:im = IndexModeNone> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ACI:oops;
  dag InOperandList = !con(ACI:iops, (ins pred:$p));
  string AsmString = !strconcat(ACI:opc, !strconcat("${p}", ACI:asm));
  list<dag> Pattern = ACI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = ACI:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class ACInoP<dag ACInoP:oops = ?, dag ACInoP:iops = ?, string ACInoP:opc = ?, string ACInoP:asm = ?, list<dag> ACInoP:pattern = ?, IndexMode ACInoP:im = IndexModeNone> {	// Instruction InstTemplate Encoding InstARM InoP
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ACInoP:oops;
  dag InOperandList = ACInoP:iops;
  string AsmString = !strconcat(ACInoP:opc, ACInoP:asm);
  list<dag> Pattern = ACInoP:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = ACInoP:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class ADI5<bits<4> ADI5:opcod1 = { ?, ?, ?, ? }, bits<2> ADI5:opcod2 = { ?, ? }, dag ADI5:oops = ?, dag ADI5:iops = ?, InstrItinClass ADI5:itin = ?, string ADI5:opc = ?, string ADI5:asm = ?, list<dag> ADI5:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ADI5:opcod1{3}, ADI5:opcod1{2}, ADI5:opcod1{1}, ADI5:opcod1{0}, addr{8}, Dd{4}, ADI5:opcod2{1}, ADI5:opcod2{0}, addr{12}, addr{11}, addr{10}, addr{9}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ADI5:oops;
  dag InOperandList = !con(ADI5:iops, (ins pred:$p));
  string AsmString = !strconcat(ADI5:opc, !strconcat("${p}", ADI5:asm));
  list<dag> Pattern = ADI5:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ADI5:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode5;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ADbI<bits<5> ADbI:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ADbI:opcod2 = { ?, ? }, bit ADbI:op6 = ?, bit ADbI:op4 = ?, dag ADbI:oops = ?, dag ADbI:iops = ?, InstrItinClass ADbI:itin = ?, string ADbI:opc = ?, string ADbI:asm = ?, list<dag> ADbI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ADbI:opcod1{4}, ADbI:opcod1{3}, ADbI:opcod1{2}, ADbI:opcod1{1}, ADbI:opcod1{0}, Dd{4}, ADbI:opcod2{1}, ADbI:opcod2{0}, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, ADbI:op6, Dm{4}, ADbI:op4, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ADbI:oops;
  dag InOperandList = !con(ADbI:iops, (ins pred:$p));
  string AsmString = !strconcat(ADbI:opc, !strconcat("${p}", ADbI:asm));
  list<dag> Pattern = ADbI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ADbI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPBinaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ADbInp<bits<5> ADbInp:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ADbInp:opcod2 = { ?, ? }, bit ADbInp:opcod3 = ?, dag ADbInp:oops = ?, dag ADbInp:iops = ?, InstrItinClass ADbInp:itin = ?, string ADbInp:asm = ?, list<dag> ADbInp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPXI
  field bits<32> Inst = { 1, 1, 1, 1, ADbInp:opcod1{4}, ADbInp:opcod1{3}, ADbInp:opcod1{2}, ADbInp:opcod1{1}, ADbInp:opcod1{0}, Dd{4}, ADbInp:opcod2{1}, ADbInp:opcod2{0}, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, ADbInp:opcod3, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ADbInp:oops;
  dag InOperandList = ADbInp:iops;
  string AsmString = ADbInp:asm;
  list<dag> Pattern = ADbInp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ADbInp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPBinaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ADivA1I<bits<3> ADivA1I:opcod = { ?, ?, ? }, dag ADivA1I:oops = ?, dag ADivA1I:iops = ?, InstrItinClass ADivA1I:itin = ?, string ADivA1I:opc = ?, string ADivA1I:asm = ?, list<dag> ADivA1I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, ADivA1I:opcod{2}, ADivA1I:opcod{1}, ADivA1I:opcod{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ADivA1I:oops;
  dag InOperandList = !con(ADivA1I:iops, (ins pred:$p));
  string AsmString = !strconcat(ADivA1I:opc, !strconcat("${p}", ADivA1I:asm));
  list<dag> Pattern = ADivA1I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ADivA1I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ArithMiscFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class ADuI<bits<5> ADuI:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ADuI:opcod2 = { ?, ? }, bits<4> ADuI:opcod3 = { ?, ?, ?, ? }, bits<2> ADuI:opcod4 = { ?, ? }, bit ADuI:opcod5 = ?, dag ADuI:oops = ?, dag ADuI:iops = ?, InstrItinClass ADuI:itin = ?, string ADuI:opc = ?, string ADuI:asm = ?, list<dag> ADuI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ADuI:opcod1{4}, ADuI:opcod1{3}, ADuI:opcod1{2}, ADuI:opcod1{1}, ADuI:opcod1{0}, Dd{4}, ADuI:opcod2{1}, ADuI:opcod2{0}, ADuI:opcod3{3}, ADuI:opcod3{2}, ADuI:opcod3{1}, ADuI:opcod3{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, ADuI:opcod4{1}, ADuI:opcod4{0}, Dm{4}, ADuI:opcod5, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ADuI:oops;
  dag InOperandList = !con(ADuI:iops, (ins pred:$p));
  string AsmString = !strconcat(ADuI:opc, !strconcat("${p}", ADuI:asm));
  list<dag> Pattern = ADuI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ADuI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPUnaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ADuInp<bits<5> ADuInp:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ADuInp:opcod2 = { ?, ? }, bits<4> ADuInp:opcod3 = { ?, ?, ?, ? }, bits<2> ADuInp:opcod4 = { ?, ? }, bit ADuInp:opcod5 = ?, dag ADuInp:oops = ?, dag ADuInp:iops = ?, InstrItinClass ADuInp:itin = ?, string ADuInp:asm = ?, list<dag> ADuInp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPXI
  field bits<32> Inst = { 1, 1, 1, 1, ADuInp:opcod1{4}, ADuInp:opcod1{3}, ADuInp:opcod1{2}, ADuInp:opcod1{1}, ADuInp:opcod1{0}, Dd{4}, ADuInp:opcod2{1}, ADuInp:opcod2{0}, ADuInp:opcod3{3}, ADuInp:opcod3{2}, ADuInp:opcod3{1}, ADuInp:opcod3{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, ADuInp:opcod4{1}, ADuInp:opcod4{0}, Dm{4}, ADuInp:opcod5, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ADuInp:oops;
  dag InOperandList = ADuInp:iops;
  string AsmString = ADuInp:asm;
  list<dag> Pattern = ADuInp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ADuInp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPUnaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AES<string AES:op = ?, bit AES:op7 = ?, bit AES:op6 = ?, SDPatternOperator AES:Int = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntXnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, AES:op7, AES:op6, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = !strconcat(!strconcat("aes", AES:op), ".8	$Vd, $Vm");
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (AES:Int (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AES2Op<string AES2Op:op = ?, bit AES2Op:op7 = ?, bit AES2Op:op6 = ?, SDPatternOperator AES2Op:Int = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntX2np Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, AES2Op:op7, AES2Op:op6, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vm);
  string AsmString = !strconcat(!strconcat("aes", AES2Op:op), ".8	$Vd, $Vm");
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (AES2Op:Int (v16i8 QPR:$src), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AES_1Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AES_2Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AExtI<bits<8> AExtI:opcod = { ?, ?, ?, ?, ?, ?, ?, ? }, dag AExtI:oops = ?, dag AExtI:iops = ?, InstrItinClass AExtI:itin = ?, string AExtI:opc = ?, string AExtI:asm = ?, list<dag> AExtI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AExtI:opcod{7}, AExtI:opcod{6}, AExtI:opcod{5}, AExtI:opcod{4}, AExtI:opcod{3}, AExtI:opcod{2}, AExtI:opcod{1}, AExtI:opcod{0}, ?, ?, ?, ?, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AExtI:oops;
  dag InOperandList = !con(AExtI:iops, (ins pred:$p));
  string AsmString = !strconcat(AExtI:opc, !strconcat("${p}", AExtI:asm));
  list<dag> Pattern = AExtI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AExtI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ExtFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class AHI5<bits<4> AHI5:opcod1 = { ?, ?, ?, ? }, bits<2> AHI5:opcod2 = { ?, ? }, dag AHI5:oops = ?, dag AHI5:iops = ?, InstrItinClass AHI5:itin = ?, string AHI5:opc = ?, string AHI5:asm = ?, list<dag> AHI5:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AHI5:opcod1{3}, AHI5:opcod1{2}, AHI5:opcod1{1}, AHI5:opcod1{0}, addr{8}, Sd{0}, AHI5:opcod2{1}, AHI5:opcod2{0}, addr{12}, addr{11}, addr{10}, addr{9}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AHI5:oops;
  dag InOperandList = !con(AHI5:iops, (ins pred:$p));
  string AsmString = !strconcat(AHI5:opc, !strconcat("${p}", AHI5:asm));
  list<dag> Pattern = AHI5:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AHI5:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode5FP16;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AHbI<bits<5> AHbI:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AHbI:opcod2 = { ?, ? }, bit AHbI:op6 = ?, bit AHbI:op4 = ?, dag AHbI:oops = ?, dag AHbI:iops = ?, InstrItinClass AHbI:itin = ?, string AHbI:opc = ?, string AHbI:asm = ?, list<dag> AHbI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AHbI:opcod1{4}, AHbI:opcod1{3}, AHbI:opcod1{2}, AHbI:opcod1{1}, AHbI:opcod1{0}, Sd{0}, AHbI:opcod2{1}, AHbI:opcod2{0}, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, AHbI:op6, Sm{0}, AHbI:op4, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AHbI:oops;
  dag InOperandList = !con(AHbI:iops, (ins pred:$p));
  string AsmString = !strconcat(AHbI:opc, !strconcat("${p}", AHbI:asm));
  list<dag> Pattern = AHbI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AHbI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPBinaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AHbInp<bits<5> AHbInp:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AHbInp:opcod2 = { ?, ? }, bit AHbInp:opcod3 = ?, dag AHbInp:oops = ?, dag AHbInp:iops = ?, InstrItinClass AHbInp:itin = ?, string AHbInp:asm = ?, list<dag> AHbInp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPXI
  field bits<32> Inst = { 1, 1, 1, 1, AHbInp:opcod1{4}, AHbInp:opcod1{3}, AHbInp:opcod1{2}, AHbInp:opcod1{1}, AHbInp:opcod1{0}, Sd{0}, AHbInp:opcod2{1}, AHbInp:opcod2{0}, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, AHbInp:opcod3, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AHbInp:oops;
  dag InOperandList = AHbInp:iops;
  string AsmString = AHbInp:asm;
  list<dag> Pattern = AHbInp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AHbInp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPBinaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AHuI<bits<5> AHuI:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AHuI:opcod2 = { ?, ? }, bits<4> AHuI:opcod3 = { ?, ?, ?, ? }, bits<2> AHuI:opcod4 = { ?, ? }, bit AHuI:opcod5 = ?, dag AHuI:oops = ?, dag AHuI:iops = ?, InstrItinClass AHuI:itin = ?, string AHuI:opc = ?, string AHuI:asm = ?, list<dag> AHuI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AHuI:opcod1{4}, AHuI:opcod1{3}, AHuI:opcod1{2}, AHuI:opcod1{1}, AHuI:opcod1{0}, Sd{0}, AHuI:opcod2{1}, AHuI:opcod2{0}, AHuI:opcod3{3}, AHuI:opcod3{2}, AHuI:opcod3{1}, AHuI:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, AHuI:opcod4{1}, AHuI:opcod4{0}, Sm{0}, AHuI:opcod5, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AHuI:oops;
  dag InOperandList = !con(AHuI:iops, (ins pred:$p));
  string AsmString = !strconcat(AHuI:opc, !strconcat("${p}", AHuI:asm));
  list<dag> Pattern = AHuI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AHuI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPUnaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AHuInp<bits<5> AHuInp:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AHuInp:opcod2 = { ?, ? }, bits<4> AHuInp:opcod3 = { ?, ?, ?, ? }, bits<2> AHuInp:opcod4 = { ?, ? }, bit AHuInp:opcod5 = ?, dag AHuInp:oops = ?, dag AHuInp:iops = ?, InstrItinClass AHuInp:itin = ?, string AHuInp:asm = ?, list<dag> AHuInp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPXI
  field bits<32> Inst = { 1, 1, 1, 1, AHuInp:opcod1{4}, AHuInp:opcod1{3}, AHuInp:opcod1{2}, AHuInp:opcod1{1}, AHuInp:opcod1{0}, Sd{0}, AHuInp:opcod2{1}, AHuInp:opcod2{0}, AHuInp:opcod3{3}, AHuInp:opcod3{2}, AHuInp:opcod3{1}, AHuInp:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, AHuInp:opcod4{1}, AHuInp:opcod4{0}, Sm{0}, AHuInp:opcod5, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AHuInp:oops;
  dag InOperandList = AHuInp:iops;
  string AsmString = AHuInp:asm;
  list<dag> Pattern = AHuInp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AHuInp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPUnaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AI<dag AI:oops = ?, dag AI:iops = ?, Format AI:f = ?, InstrItinClass AI:itin = ?, string AI:opc = ?, string AI:asm = ?, list<dag> AI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI:oops;
  dag InOperandList = !con(AI:iops, (ins pred:$p));
  string AsmString = !strconcat(AI:opc, !strconcat("${p}", AI:asm));
  list<dag> Pattern = AI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI1<bits<4> AI1:opcod = { ?, ?, ?, ? }, dag AI1:oops = ?, dag AI1:iops = ?, Format AI1:f = ?, InstrItinClass AI1:itin = ?, string AI1:opc = ?, string AI1:asm = ?, list<dag> AI1:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, ?, AI1:opcod{3}, AI1:opcod{2}, AI1:opcod{1}, AI1:opcod{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI1:oops;
  dag InOperandList = !con(AI1:iops, (ins pred:$p));
  string AsmString = !strconcat(AI1:opc, !strconcat("${p}", AI1:asm));
  list<dag> Pattern = AI1:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI1:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI1:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI1:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI2ldst<bits<3> AI2ldst:op = { ?, ?, ? }, bit AI2ldst:isLd = ?, bit AI2ldst:isByte = ?, dag AI2ldst:oops = ?, dag AI2ldst:iops = ?, AddrMode AI2ldst:am = ?, Format AI2ldst:f = ?, InstrItinClass AI2ldst:itin = ?, string AI2ldst:opc = ?, string AI2ldst:asm = ?, list<dag> AI2ldst:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AI2ldst:op{2}, AI2ldst:op{1}, AI2ldst:op{0}, 1, ?, AI2ldst:isByte, 0, AI2ldst:isLd, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI2ldst:oops;
  dag InOperandList = !con(AI2ldst:iops, (ins pred:$p));
  string AsmString = !strconcat(AI2ldst:opc, !strconcat("${p}", AI2ldst:asm));
  list<dag> Pattern = AI2ldst:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI2ldst:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI2ldst:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AI2ldst:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI2ldst:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI2ldstidx<bit AI2ldstidx:isLd = ?, bit AI2ldstidx:isByte = ?, bit AI2ldstidx:isPre = ?, dag AI2ldstidx:oops = ?, dag AI2ldstidx:iops = ?, IndexMode AI2ldstidx:im = ?, Format AI2ldstidx:f = ?, InstrItinClass AI2ldstidx:itin = ?, string AI2ldstidx:opc = ?, string AI2ldstidx:asm = ?, string AI2ldstidx:cstr = ?, list<dag> AI2ldstidx:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, ?, AI2ldstidx:isPre, ?, AI2ldstidx:isByte, AI2ldstidx:isPre, AI2ldstidx:isLd, ?, ?, ?, ?, Rt{3}, Rt{2}, Rt{1}, Rt{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI2ldstidx:oops;
  dag InOperandList = !con(AI2ldstidx:iops, (ins pred:$p));
  string AsmString = !strconcat(AI2ldstidx:opc, !strconcat("${p}", AI2ldstidx:asm));
  list<dag> Pattern = AI2ldstidx:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI2ldstidx:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI2ldstidx:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AI2ldstidx:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = AI2ldstidx:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI2ldstidx:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI2stridxT<bit AI2stridxT:isByte = ?, bit AI2stridxT:isPre = ?, dag AI2stridxT:oops = ?, dag AI2stridxT:iops = ?, IndexMode AI2stridxT:im = ?, Format AI2stridxT:f = ?, InstrItinClass AI2stridxT:itin = ?, string AI2stridxT:opc = ?, string AI2stridxT:asm = ?, string AI2stridxT:cstr = ?, list<dag> AI2stridxT:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, addr{13}, AI2stridxT:isPre, addr{12}, AI2stridxT:isByte, AI2stridxT:isPre, 0, addr{17}, addr{16}, addr{15}, addr{14}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI2stridxT:oops;
  dag InOperandList = !con(AI2stridxT:iops, (ins pred:$p));
  string AsmString = !strconcat(AI2stridxT:opc, !strconcat("${p}", AI2stridxT:asm));
  list<dag> Pattern = AI2stridxT:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI2stridxT:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI2stridxT:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AI2stridxT:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = AI2stridxT:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI2stridxT:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<18> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AI2stridx_imm<bit AI2stridx_imm:isByte = ?, bit AI2stridx_imm:isPre = ?, dag AI2stridx_imm:oops = ?, dag AI2stridx_imm:iops = ?, IndexMode AI2stridx_imm:im = ?, Format AI2stridx_imm:f = ?, InstrItinClass AI2stridx_imm:itin = ?, string AI2stridx_imm:opc = ?, string AI2stridx_imm:asm = ?, string AI2stridx_imm:cstr = ?, list<dag> AI2stridx_imm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, AI2stridx_imm:isPre, offset{12}, AI2stridx_imm:isByte, AI2stridx_imm:isPre, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI2stridx_imm:oops;
  dag InOperandList = !con(AI2stridx_imm:iops, (ins pred:$p));
  string AsmString = !strconcat(AI2stridx_imm:opc, !strconcat("${p}", AI2stridx_imm:asm));
  list<dag> Pattern = AI2stridx_imm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI2stridx_imm:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI2stridx_imm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AI2stridx_imm:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = AI2stridx_imm:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI2stridx_imm:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI2stridx_reg<bit AI2stridx_reg:isByte = ?, bit AI2stridx_reg:isPre = ?, dag AI2stridx_reg:oops = ?, dag AI2stridx_reg:iops = ?, IndexMode AI2stridx_reg:im = ?, Format AI2stridx_reg:f = ?, InstrItinClass AI2stridx_reg:itin = ?, string AI2stridx_reg:opc = ?, string AI2stridx_reg:asm = ?, string AI2stridx_reg:cstr = ?, list<dag> AI2stridx_reg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, AI2stridx_reg:isPre, offset{12}, AI2stridx_reg:isByte, AI2stridx_reg:isPre, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, 0, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI2stridx_reg:oops;
  dag InOperandList = !con(AI2stridx_reg:iops, (ins pred:$p));
  string AsmString = !strconcat(AI2stridx_reg:opc, !strconcat("${p}", AI2stridx_reg:asm));
  list<dag> Pattern = AI2stridx_reg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI2stridx_reg:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI2stridx_reg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AI2stridx_reg:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = AI2stridx_reg:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI2stridx_reg:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI3ld<bits<4> AI3ld:op = { ?, ?, ?, ? }, bit AI3ld:op20 = ?, dag AI3ld:oops = ?, dag AI3ld:iops = ?, Format AI3ld:f = ?, InstrItinClass AI3ld:itin = ?, string AI3ld:opc = ?, string AI3ld:asm = ?, list<dag> AI3ld:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 0, AI3ld:op20, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, AI3ld:op{3}, AI3ld:op{2}, AI3ld:op{1}, AI3ld:op{0}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI3ld:oops;
  dag InOperandList = !con(AI3ld:iops, (ins pred:$p));
  string AsmString = !strconcat(AI3ld:opc, !strconcat("${p}", AI3ld:asm));
  list<dag> Pattern = AI3ld:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI3ld:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI3ld:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI3ld:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI3ldstidx<bits<4> AI3ldstidx:op = { ?, ?, ?, ? }, bit AI3ldstidx:op20 = ?, bit AI3ldstidx:isPre = ?, dag AI3ldstidx:oops = ?, dag AI3ldstidx:iops = ?, IndexMode AI3ldstidx:im = ?, Format AI3ldstidx:f = ?, InstrItinClass AI3ldstidx:itin = ?, string AI3ldstidx:opc = ?, string AI3ldstidx:asm = ?, string AI3ldstidx:cstr = ?, list<dag> AI3ldstidx:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, AI3ldstidx:isPre, ?, ?, AI3ldstidx:isPre, AI3ldstidx:op20, ?, ?, ?, ?, Rt{3}, Rt{2}, Rt{1}, Rt{0}, ?, ?, ?, ?, AI3ldstidx:op{3}, AI3ldstidx:op{2}, AI3ldstidx:op{1}, AI3ldstidx:op{0}, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI3ldstidx:oops;
  dag InOperandList = !con(AI3ldstidx:iops, (ins pred:$p));
  string AsmString = !strconcat(AI3ldstidx:opc, !strconcat("${p}", AI3ldstidx:asm));
  list<dag> Pattern = AI3ldstidx:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI3ldstidx:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI3ldstidx:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AI3ldstidx:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = AI3ldstidx:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI3ldstidx:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI3ldstidxT<bits<4> AI3ldstidxT:op = { ?, ?, ?, ? }, bit AI3ldstidxT:isLoad = ?, dag AI3ldstidxT:oops = ?, dag AI3ldstidxT:iops = ?, IndexMode AI3ldstidxT:im = ?, Format AI3ldstidxT:f = ?, InstrItinClass AI3ldstidxT:itin = ?, string AI3ldstidxT:opc = ?, string AI3ldstidxT:asm = ?, string AI3ldstidxT:cstr = ?, list<dag> AI3ldstidxT:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, ?, ?, 1, AI3ldstidxT:isLoad, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, ?, ?, ?, ?, AI3ldstidxT:op{3}, AI3ldstidxT:op{2}, AI3ldstidxT:op{1}, AI3ldstidxT:op{0}, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI3ldstidxT:oops;
  dag InOperandList = !con(AI3ldstidxT:iops, (ins pred:$p));
  string AsmString = !strconcat(AI3ldstidxT:opc, !strconcat("${p}", AI3ldstidxT:asm));
  list<dag> Pattern = AI3ldstidxT:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI3ldstidxT:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI3ldstidxT:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AI3ldstidxT:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = AI3ldstidxT:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI3ldstidxT:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI3str<bits<4> AI3str:op = { ?, ?, ?, ? }, dag AI3str:oops = ?, dag AI3str:iops = ?, Format AI3str:f = ?, InstrItinClass AI3str:itin = ?, string AI3str:opc = ?, string AI3str:asm = ?, list<dag> AI3str:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, AI3str:op{3}, AI3str:op{2}, AI3str:op{1}, AI3str:op{0}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AI3str:oops;
  dag InOperandList = !con(AI3str:iops, (ins pred:$p));
  string AsmString = !strconcat(AI3str:opc, !strconcat("${p}", AI3str:asm));
  list<dag> Pattern = AI3str:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AI3str:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AI3str:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AI3str:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI_crc32<bit AI_crc32:C = ?, bits<2> AI_crc32:sz = { ?, ? }, string AI_crc32:suffix = ?, SDPatternOperator AI_crc32:builtin = ?> {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, AI_crc32:sz{1}, AI_crc32:sz{0}, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, AI_crc32:C, 0, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm);
  string AsmString = !strconcat(!strconcat("crc32", AI_crc32:suffix), "	$Rd, $Rn, $Rm");
  list<dag> Pattern = [(set GPRnopc:$Rd, (AI_crc32:builtin GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MiscFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class AI_ext_rrot<bits<8> AI_ext_rrot:opcod = { ?, ?, ?, ?, ?, ?, ?, ? }, string AI_ext_rrot:opc = ?, PatFrag AI_ext_rrot:opnode = ?> {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AI_ext_rrot:opcod{7}, AI_ext_rrot:opcod{6}, AI_ext_rrot:opcod{5}, AI_ext_rrot:opcod{4}, AI_ext_rrot:opcod{3}, AI_ext_rrot:opcod{2}, AI_ext_rrot:opcod{1}, AI_ext_rrot:opcod{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = !strconcat(AI_ext_rrot:opc, "${p}	$Rd, $Rm$rot");
  list<dag> Pattern = [(set GPRnopc:$Rd, (AI_ext_rrot:opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALUsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ExtFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
class AI_ext_rrot_np<bits<8> AI_ext_rrot_np:opcod = { ?, ?, ?, ?, ?, ?, ?, ? }, string AI_ext_rrot_np:opc = ?> {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AI_ext_rrot_np:opcod{7}, AI_ext_rrot_np:opcod{6}, AI_ext_rrot_np:opcod{5}, AI_ext_rrot_np:opcod{4}, AI_ext_rrot_np:opcod{3}, AI_ext_rrot_np:opcod{2}, AI_ext_rrot_np:opcod{1}, AI_ext_rrot_np:opcod{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = !strconcat(AI_ext_rrot_np:opc, "${p}	$Rd, $Rm$rot");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALUsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ExtFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
class AI_exta_rrot<bits<8> AI_exta_rrot:opcod = { ?, ?, ?, ?, ?, ?, ?, ? }, string AI_exta_rrot:opc = ?, PatFrag AI_exta_rrot:opnode = ?> {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AI_exta_rrot:opcod{7}, AI_exta_rrot:opcod{6}, AI_exta_rrot:opcod{5}, AI_exta_rrot:opcod{4}, AI_exta_rrot:opcod{3}, AI_exta_rrot:opcod{2}, AI_exta_rrot:opcod{1}, AI_exta_rrot:opcod{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = !strconcat(AI_exta_rrot:opc, "${p}	$Rd, $Rn, $Rm$rot");
  list<dag> Pattern = [(set GPRnopc:$Rd, (AI_exta_rrot:opnode GPR:$Rn, (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAr;
  list<SchedReadWrite> SchedRW = [WriteALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ExtFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
class AI_exta_rrot_np<bits<8> AI_exta_rrot_np:opcod = { ?, ?, ?, ?, ?, ?, ?, ? }, string AI_exta_rrot_np:opc = ?> {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AI_exta_rrot_np:opcod{7}, AI_exta_rrot_np:opcod{6}, AI_exta_rrot_np:opcod{5}, AI_exta_rrot_np:opcod{4}, AI_exta_rrot_np:opcod{3}, AI_exta_rrot_np:opcod{2}, AI_exta_rrot_np:opcod{1}, AI_exta_rrot_np:opcod{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = !strconcat(AI_exta_rrot_np:opc, "${p}	$Rd, $Rn, $Rm$rot");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAr;
  list<SchedReadWrite> SchedRW = [WriteALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ExtFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
class AIldaex<bits<2> AIldaex:opcod = { ?, ? }, dag AIldaex:oops = ?, dag AIldaex:iops = ?, InstrItinClass AIldaex:itin = ?, string AIldaex:opc = ?, string AIldaex:asm = ?, list<dag> AIldaex:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, AIldaex:opcod{1}, AIldaex:opcod{0}, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AIldaex:oops;
  dag InOperandList = !con(AIldaex:iops, (ins pred:$p));
  string AsmString = !strconcat(AIldaex:opc, !strconcat("${p}", AIldaex:asm));
  list<dag> Pattern = AIldaex:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AIldaex:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = LdStExFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
class AIldr_ex_or_acq<bits<2> AIldr_ex_or_acq:opcod = { ?, ? }, bits<2> AIldr_ex_or_acq:opcod2 = { ?, ? }, dag AIldr_ex_or_acq:oops = ?, dag AIldr_ex_or_acq:iops = ?, InstrItinClass AIldr_ex_or_acq:itin = ?, string AIldr_ex_or_acq:opc = ?, string AIldr_ex_or_acq:asm = ?, list<dag> AIldr_ex_or_acq:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, AIldr_ex_or_acq:opcod{1}, AIldr_ex_or_acq:opcod{0}, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, AIldr_ex_or_acq:opcod2{1}, AIldr_ex_or_acq:opcod2{0}, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AIldr_ex_or_acq:oops;
  dag InOperandList = !con(AIldr_ex_or_acq:iops, (ins pred:$p));
  string AsmString = !strconcat(AIldr_ex_or_acq:opc, !strconcat("${p}", AIldr_ex_or_acq:asm));
  list<dag> Pattern = AIldr_ex_or_acq:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AIldr_ex_or_acq:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = LdStExFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
class AIldracq<bits<2> AIldracq:opcod = { ?, ? }, dag AIldracq:oops = ?, dag AIldracq:iops = ?, InstrItinClass AIldracq:itin = ?, string AIldracq:opc = ?, string AIldracq:asm = ?, list<dag> AIldracq:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, AIldracq:opcod{1}, AIldracq:opcod{0}, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AIldracq:oops;
  dag InOperandList = !con(AIldracq:iops, (ins pred:$p));
  string AsmString = !strconcat(AIldracq:opc, !strconcat("${p}", AIldracq:asm));
  list<dag> Pattern = AIldracq:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AIldracq:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = LdStExFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
class AIldrex<bits<2> AIldrex:opcod = { ?, ? }, dag AIldrex:oops = ?, dag AIldrex:iops = ?, InstrItinClass AIldrex:itin = ?, string AIldrex:opc = ?, string AIldrex:asm = ?, list<dag> AIldrex:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, AIldrex:opcod{1}, AIldrex:opcod{0}, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AIldrex:oops;
  dag InOperandList = !con(AIldrex:iops, (ins pred:$p));
  string AsmString = !strconcat(AIldrex:opc, !strconcat("${p}", AIldrex:asm));
  list<dag> Pattern = AIldrex:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AIldrex:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = LdStExFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
class AInoP<dag AInoP:oops = ?, dag AInoP:iops = ?, Format AInoP:f = ?, InstrItinClass AInoP:itin = ?, string AInoP:opc = ?, string AInoP:asm = ?, list<dag> AInoP:pattern = ?> {	// Instruction InstTemplate Encoding InstARM InoP
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AInoP:oops;
  dag InOperandList = AInoP:iops;
  string AsmString = !strconcat(AInoP:opc, AInoP:asm);
  list<dag> Pattern = AInoP:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AInoP:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AInoP:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AInoP:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class AIstlex<bits<2> AIstlex:opcod = { ?, ? }, dag AIstlex:oops = ?, dag AIstlex:iops = ?, InstrItinClass AIstlex:itin = ?, string AIstlex:opc = ?, string AIstlex:asm = ?, list<dag> AIstlex:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, AIstlex:opcod{1}, AIstlex:opcod{0}, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 0, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AIstlex:oops;
  dag InOperandList = !con(AIstlex:iops, (ins pred:$p));
  string AsmString = !strconcat(AIstlex:opc, !strconcat("${p}", AIstlex:asm));
  list<dag> Pattern = AIstlex:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AIstlex:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = LdStExFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
class AIstr_ex_or_rel<bits<2> AIstr_ex_or_rel:opcod = { ?, ? }, bits<2> AIstr_ex_or_rel:opcod2 = { ?, ? }, dag AIstr_ex_or_rel:oops = ?, dag AIstr_ex_or_rel:iops = ?, InstrItinClass AIstr_ex_or_rel:itin = ?, string AIstr_ex_or_rel:opc = ?, string AIstr_ex_or_rel:asm = ?, list<dag> AIstr_ex_or_rel:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, AIstr_ex_or_rel:opcod{1}, AIstr_ex_or_rel:opcod{0}, 0, addr{3}, addr{2}, addr{1}, addr{0}, ?, ?, ?, ?, 1, 1, AIstr_ex_or_rel:opcod2{1}, AIstr_ex_or_rel:opcod2{0}, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AIstr_ex_or_rel:oops;
  dag InOperandList = !con(AIstr_ex_or_rel:iops, (ins pred:$p));
  string AsmString = !strconcat(AIstr_ex_or_rel:opc, !strconcat("${p}", AIstr_ex_or_rel:asm));
  list<dag> Pattern = AIstr_ex_or_rel:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AIstr_ex_or_rel:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = LdStExFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
class AIstrex<bits<2> AIstrex:opcod = { ?, ? }, dag AIstrex:oops = ?, dag AIstrex:iops = ?, InstrItinClass AIstrex:itin = ?, string AIstrex:opc = ?, string AIstrex:asm = ?, list<dag> AIstrex:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, AIstrex:opcod{1}, AIstrex:opcod{0}, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AIstrex:oops;
  dag InOperandList = !con(AIstrex:iops, (ins pred:$p));
  string AsmString = !strconcat(AIstrex:opc, !strconcat("${p}", AIstrex:asm));
  list<dag> Pattern = AIstrex:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AIstrex:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = LdStExFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
class AIstrrel<bits<2> AIstrrel:opcod = { ?, ? }, dag AIstrrel:oops = ?, dag AIstrrel:iops = ?, InstrItinClass AIstrrel:itin = ?, string AIstrrel:opc = ?, string AIstrrel:asm = ?, list<dag> AIstrrel:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, AIstrrel:opcod{1}, AIstrrel:opcod{0}, 0, addr{3}, addr{2}, addr{1}, addr{0}, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AIstrrel:oops;
  dag InOperandList = !con(AIstrrel:iops, (ins pred:$p));
  string AsmString = !strconcat(AIstrrel:opc, !strconcat("${p}", AIstrrel:asm));
  list<dag> Pattern = AIstrrel:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AIstrrel:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = LdStExFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
class AIswp<bit AIswp:b = ?, dag AIswp:oops = ?, dag AIswp:iops = ?, string AIswp:opc = ?, list<dag> AIswp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, AIswp:b, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 1, 0, 0, 1, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AIswp:oops;
  dag InOperandList = !con(AIswp:iops, (ins pred:$p));
  string AsmString = !strconcat(AIswp:opc, "${p}	$Rt, $Rt2, $addr");
  list<dag> Pattern = AIswp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSwap";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MiscFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMDGPUArg<LLVMType AMDGPUArg:ty = ?, string AMDGPUArg:name = ?> {
  LLVMType Type = AMDGPUArg:ty;
  string Name = AMDGPUArg:name;
  string NAME = ?;
}
class AMDGPUAtomicIncIntrin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, anonymous_6, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
class AMDGPUBufferAtomic {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
class AMDGPUBufferLoad {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 0;
  bit IsImage = 0;
  string NAME = ?;
}
class AMDGPUBufferStore {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
class AMDGPUDimAtomicProfile<string AMDGPUDimAtomicProfile:opmod = ?, AMDGPUDimProps AMDGPUDimAtomicProfile:dim = ?, list<AMDGPUArg> AMDGPUDimAtomicProfile:dataargs = ?> {	// AMDGPUDimProfile
  AMDGPUDimProps Dim = AMDGPUDimAtomicProfile:dim;
  string OpMod = AMDGPUDimAtomicProfile:opmod;
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = AMDGPUDimAtomicProfile:dataargs;
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = !foldl(0, !listconcat(RetTypes, !foreach(arg, DataArgs, arg.Type)), a, b, !add(a, b.isAny));
  list<AMDGPUArg> AddrArgs = arglistconcat<[ExtraAddrArgs, !if(Gradients, AMDGPUDimAtomicProfile:dim.GradientArgs, []), !listconcat(!if(IsSample, AMDGPUDimAtomicProfile:dim.CoordSliceArgs, AMDGPUDimAtomicProfile:dim.CoordSliceIntArgs), !if(!eq(LodClampMip, ""), [], [AMDGPUArg<anonymous_6, LodClampMip>]))], NumRetAndDataAnyTypes>.ret;
  list<LLVMType> AddrTypes = !foreach(arg, AddrArgs, arg.Type);
  list<AMDGPUArg> AddrDefaultArgs = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_float_ty, llvm_i32_ty), arg.Type), arg.Name>);
  list<AMDGPUArg> AddrA16Args = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_half_ty, llvm_i16_ty), arg.Type), arg.Name>);
  string NAME = ?;
}
class AMDGPUDimGetResInfoProfile<AMDGPUDimProps AMDGPUDimGetResInfoProfile:dim = ?> {	// AMDGPUDimProfile
  AMDGPUDimProps Dim = AMDGPUDimGetResInfoProfile:dim;
  string OpMod = "GET_RESINFO";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = !foldl(0, !listconcat(RetTypes, !foreach(arg, DataArgs, arg.Type)), a, b, !add(a, b.isAny));
  list<AMDGPUArg> AddrArgs = [anonymous_65];
  list<LLVMType> AddrTypes = !foreach(arg, AddrArgs, arg.Type);
  list<AMDGPUArg> AddrDefaultArgs = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_float_ty, llvm_i32_ty), arg.Type), arg.Name>);
  list<AMDGPUArg> AddrA16Args = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_half_ty, llvm_i16_ty), arg.Type), arg.Name>);
  string NAME = ?;
}
class AMDGPUDimNoSampleProfile<string AMDGPUDimNoSampleProfile:opmod = ?, AMDGPUDimProps AMDGPUDimNoSampleProfile:dim = ?, list<LLVMType> AMDGPUDimNoSampleProfile:retty = ?, list<AMDGPUArg> AMDGPUDimNoSampleProfile:dataargs = ?, bit AMDGPUDimNoSampleProfile:Mip = 0> {	// AMDGPUDimProfile
  AMDGPUDimProps Dim = AMDGPUDimNoSampleProfile:dim;
  string OpMod = AMDGPUDimNoSampleProfile:opmod;
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = AMDGPUDimNoSampleProfile:retty;
  list<AMDGPUArg> DataArgs = AMDGPUDimNoSampleProfile:dataargs;
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = !if(AMDGPUDimNoSampleProfile:Mip, "mip", "");
  int NumRetAndDataAnyTypes = !foldl(0, !listconcat(RetTypes, !foreach(arg, DataArgs, arg.Type)), a, b, !add(a, b.isAny));
  list<AMDGPUArg> AddrArgs = arglistconcat<[ExtraAddrArgs, !if(Gradients, AMDGPUDimNoSampleProfile:dim.GradientArgs, []), !listconcat(!if(IsSample, AMDGPUDimNoSampleProfile:dim.CoordSliceArgs, AMDGPUDimNoSampleProfile:dim.CoordSliceIntArgs), !if(!eq(LodClampMip, ""), [], [AMDGPUArg<anonymous_6, LodClampMip>]))], NumRetAndDataAnyTypes>.ret;
  list<LLVMType> AddrTypes = !foreach(arg, AddrArgs, arg.Type);
  list<AMDGPUArg> AddrDefaultArgs = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_float_ty, llvm_i32_ty), arg.Type), arg.Name>);
  list<AMDGPUArg> AddrA16Args = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_half_ty, llvm_i16_ty), arg.Type), arg.Name>);
  string NAME = ?;
}
class AMDGPUDimProfile<string AMDGPUDimProfile:opmod = ?, AMDGPUDimProps AMDGPUDimProfile:dim = ?> {
  AMDGPUDimProps Dim = AMDGPUDimProfile:dim;
  string OpMod = AMDGPUDimProfile:opmod;
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = !foldl(0, !listconcat(RetTypes, !foreach(arg, DataArgs, arg.Type)), a, b, !add(a, b.isAny));
  list<AMDGPUArg> AddrArgs = arglistconcat<[ExtraAddrArgs, !if(Gradients, AMDGPUDimProfile:dim.GradientArgs, []), !listconcat(!if(IsSample, AMDGPUDimProfile:dim.CoordSliceArgs, AMDGPUDimProfile:dim.CoordSliceIntArgs), !if(!eq(LodClampMip, ""), [], [AMDGPUArg<anonymous_6, LodClampMip>]))], NumRetAndDataAnyTypes>.ret;
  list<LLVMType> AddrTypes = !foreach(arg, AddrArgs, arg.Type);
  list<AMDGPUArg> AddrDefaultArgs = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_float_ty, llvm_i32_ty), arg.Type), arg.Name>);
  list<AMDGPUArg> AddrA16Args = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_half_ty, llvm_i16_ty), arg.Type), arg.Name>);
  string NAME = ?;
}
class AMDGPUDimProfileCopy<AMDGPUDimProfile AMDGPUDimProfileCopy:base = ?> {	// AMDGPUDimProfile
  AMDGPUDimProps Dim = AMDGPUDimProfileCopy:base.Dim;
  string OpMod = AMDGPUDimProfileCopy:base.OpMod;
  bit IsSample = AMDGPUDimProfileCopy:base.IsSample;
  bit IsAtomic = AMDGPUDimProfileCopy:base.IsAtomic;
  list<LLVMType> RetTypes = AMDGPUDimProfileCopy:base.RetTypes;
  list<AMDGPUArg> DataArgs = AMDGPUDimProfileCopy:base.DataArgs;
  list<AMDGPUArg> ExtraAddrArgs = AMDGPUDimProfileCopy:base.ExtraAddrArgs;
  bit Gradients = AMDGPUDimProfileCopy:base.Gradients;
  string LodClampMip = AMDGPUDimProfileCopy:base.LodClampMip;
  int NumRetAndDataAnyTypes = !foldl(0, !listconcat(RetTypes, !foreach(arg, DataArgs, arg.Type)), a, b, !add(a, b.isAny));
  list<AMDGPUArg> AddrArgs = arglistconcat<[ExtraAddrArgs, !if(Gradients, AMDGPUDimProfileCopy:base.Dim.GradientArgs, []), !listconcat(!if(IsSample, AMDGPUDimProfileCopy:base.Dim.CoordSliceArgs, AMDGPUDimProfileCopy:base.Dim.CoordSliceIntArgs), !if(!eq(LodClampMip, ""), [], [AMDGPUArg<anonymous_6, LodClampMip>]))], NumRetAndDataAnyTypes>.ret;
  list<LLVMType> AddrTypes = !foreach(arg, AddrArgs, arg.Type);
  list<AMDGPUArg> AddrDefaultArgs = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_float_ty, llvm_i32_ty), arg.Type), arg.Name>);
  list<AMDGPUArg> AddrA16Args = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_half_ty, llvm_i16_ty), arg.Type), arg.Name>);
  string NAME = ?;
}
class AMDGPUDimProps<string AMDGPUDimProps:name = ?, list<string> AMDGPUDimProps:coord_names = ?, list<string> AMDGPUDimProps:slice_names = ?> {
  string Name = AMDGPUDimProps:name;
  bit DA = 0;
  list<AMDGPUArg> CoordSliceArgs = makeArgList<!listconcat(AMDGPUDimProps:coord_names, AMDGPUDimProps:slice_names), llvm_anyfloat_ty>.ret;
  list<AMDGPUArg> CoordSliceIntArgs = makeArgList<!listconcat(AMDGPUDimProps:coord_names, AMDGPUDimProps:slice_names), llvm_anyint_ty>.ret;
  list<AMDGPUArg> GradientArgs = makeArgList<!listconcat(!foreach(name, AMDGPUDimProps:coord_names, !strconcat("d", !strconcat(name, "dh"))), !foreach(name, AMDGPUDimProps:coord_names, !strconcat("d", !strconcat(name, "dv")))), llvm_anyfloat_ty>.ret;
  string NAME = ?;
}
class AMDGPUDimSampleProfile<string AMDGPUDimSampleProfile:opmod = ?, AMDGPUDimProps AMDGPUDimSampleProfile:dim = ?, AMDGPUSampleVariant AMDGPUDimSampleProfile:sample = ?> {	// AMDGPUDimProfile
  AMDGPUDimProps Dim = AMDGPUDimSampleProfile:dim;
  string OpMod = AMDGPUDimSampleProfile:opmod;
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = AMDGPUDimSampleProfile:sample.ExtraAddrArgs;
  bit Gradients = AMDGPUDimSampleProfile:sample.Gradients;
  string LodClampMip = AMDGPUDimSampleProfile:sample.LodOrClamp;
  int NumRetAndDataAnyTypes = !foldl(0, !listconcat(RetTypes, !foreach(arg, DataArgs, arg.Type)), a, b, !add(a, b.isAny));
  list<AMDGPUArg> AddrArgs = arglistconcat<[ExtraAddrArgs, !if(Gradients, AMDGPUDimSampleProfile:dim.GradientArgs, []), !listconcat(!if(IsSample, AMDGPUDimSampleProfile:dim.CoordSliceArgs, AMDGPUDimSampleProfile:dim.CoordSliceIntArgs), !if(!eq(LodClampMip, ""), [], [AMDGPUArg<anonymous_6, LodClampMip>]))], NumRetAndDataAnyTypes>.ret;
  list<LLVMType> AddrTypes = !foreach(arg, AddrArgs, arg.Type);
  list<AMDGPUArg> AddrDefaultArgs = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_float_ty, llvm_i32_ty), arg.Type), arg.Name>);
  list<AMDGPUArg> AddrA16Args = !foreach(arg, AddrArgs, AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), !if(IsSample, llvm_half_ty, llvm_i16_ty), arg.Type), arg.Name>);
  string NAME = ?;
}
class AMDGPUImageAtomic {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
class AMDGPUImageDimIntrinsic<AMDGPUDimProfile AMDGPUImageDimIntrinsic:P_ = ?, list<IntrinsicProperty> AMDGPUImageDimIntrinsic:props = ?, list<SDNodeProperty> AMDGPUImageDimIntrinsic:sdnodeprops = ?> {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = AMDGPUImageDimIntrinsic:sdnodeprops;
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = AMDGPUImageDimIntrinsic:P_.RetTypes;
  list<LLVMType> ParamTypes = !listconcat(!foreach(arg, AMDGPUImageDimIntrinsic:P_.DataArgs, arg.Type), !listconcat(!if(AMDGPUImageDimIntrinsic:P_.IsAtomic, [], [llvm_i32_ty]), !listconcat(AMDGPUImageDimIntrinsic:P_.AddrTypes, !listconcat([llvm_v8i32_ty], !listconcat(!if(AMDGPUImageDimIntrinsic:P_.IsSample, [llvm_v4i32_ty, llvm_i1_ty], []), [llvm_i32_ty, llvm_i32_ty])))));
  list<IntrinsicProperty> IntrProperties = AMDGPUImageDimIntrinsic:props;
  bit isTarget = 0;
  int RsrcArg = !add(!size(AMDGPUImageDimIntrinsic:P_.DataArgs), !add(!size(AMDGPUImageDimIntrinsic:P_.AddrTypes), !if(AMDGPUImageDimIntrinsic:P_.IsAtomic, 0, 1)));
  bit IsImage = 1;
  AMDGPUDimProfile P = AMDGPUImageDimIntrinsic:P_;
  string NAME = ?;
}
class AMDGPUImageLoad<bit AMDGPUImageLoad:NoMem = 0> {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = !if(AMDGPUImageLoad:NoMem, [], [SDNPMemOperand]);
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_anyint_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = !if(AMDGPUImageLoad:NoMem, [IntrNoMem], [IntrReadMem]);
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
class AMDGPUImageSample<bit AMDGPUImageSample:NoMem = 0> {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = !if(AMDGPUImageSample:NoMem, [], [SDNPMemOperand]);
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = !if(AMDGPUImageSample:NoMem, [IntrNoMem], [IntrReadMem]);
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
class AMDGPUImageStore {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_anyint_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
class AMDGPULDSF32Intrin<string AMDGPULDSF32Intrin:clang_builtin = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = AMDGPULDSF32Intrin:clang_builtin;
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [anonymous_29, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
class AMDGPUReadPreloadRegisterIntrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
class AMDGPUReadPreloadRegisterIntrinsicNamed<string AMDGPUReadPreloadRegisterIntrinsicNamed:name = ?> {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = AMDGPUReadPreloadRegisterIntrinsicNamed:name;
  string NAME = ?;
}
class AMDGPURsrcIntrinsic<int AMDGPURsrcIntrinsic:rsrcarg = ?, bit AMDGPURsrcIntrinsic:isimage = 0> {
  int RsrcArg = AMDGPURsrcIntrinsic:rsrcarg;
  bit IsImage = AMDGPURsrcIntrinsic:isimage;
  string NAME = ?;
}
class AMDGPUSampleVariant<string AMDGPUSampleVariant:ucmod = ?, string AMDGPUSampleVariant:lcmod = ?, list<AMDGPUArg> AMDGPUSampleVariant:extra_addr = ?> {
  string UpperCaseMod = AMDGPUSampleVariant:ucmod;
  string LowerCaseMod = AMDGPUSampleVariant:lcmod;
  list<AMDGPUArg> ExtraAddrArgs = AMDGPUSampleVariant:extra_addr;
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
class AMiscA1I<bits<8> AMiscA1I:opcod = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> AMiscA1I:opc7_4 = { ?, ?, ?, ? }, dag AMiscA1I:oops = ?, dag AMiscA1I:iops = ?, InstrItinClass AMiscA1I:itin = ?, string AMiscA1I:opc = ?, string AMiscA1I:asm = ?, list<dag> AMiscA1I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AMiscA1I:opcod{7}, AMiscA1I:opcod{6}, AMiscA1I:opcod{5}, AMiscA1I:opcod{4}, AMiscA1I:opcod{3}, AMiscA1I:opcod{2}, AMiscA1I:opcod{1}, AMiscA1I:opcod{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, AMiscA1I:opc7_4{3}, AMiscA1I:opc7_4{2}, AMiscA1I:opc7_4{1}, AMiscA1I:opc7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMiscA1I:oops;
  dag InOperandList = !con(AMiscA1I:iops, (ins pred:$p));
  string AsmString = !strconcat(AMiscA1I:opc, !strconcat("${p}", AMiscA1I:asm));
  list<dag> Pattern = AMiscA1I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMiscA1I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ArithMiscFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMul1I<bits<7> AMul1I:opcod = { ?, ?, ?, ?, ?, ?, ? }, dag AMul1I:oops = ?, dag AMul1I:iops = ?, InstrItinClass AMul1I:itin = ?, string AMul1I:opc = ?, string AMul1I:asm = ?, list<dag> AMul1I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AMul1I:opcod{6}, AMul1I:opcod{5}, AMul1I:opcod{4}, AMul1I:opcod{3}, AMul1I:opcod{2}, AMul1I:opcod{1}, AMul1I:opcod{0}, 0, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, 1, 0, 0, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMul1I:oops;
  dag InOperandList = !con(AMul1I:iops, (ins pred:$p));
  string AsmString = !strconcat(AMul1I:opc, !strconcat("${p}", AMul1I:asm));
  list<dag> Pattern = AMul1I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMul1I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMul2I<bits<7> AMul2I:opcod = { ?, ?, ?, ?, ?, ?, ? }, bits<4> AMul2I:opc7_4 = { ?, ?, ?, ? }, dag AMul2I:oops = ?, dag AMul2I:iops = ?, InstrItinClass AMul2I:itin = ?, string AMul2I:opc = ?, string AMul2I:asm = ?, list<dag> AMul2I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AMul2I:opcod{6}, AMul2I:opcod{5}, AMul2I:opcod{4}, AMul2I:opcod{3}, AMul2I:opcod{2}, AMul2I:opcod{1}, AMul2I:opcod{0}, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, AMul2I:opc7_4{3}, AMul2I:opc7_4{2}, AMul2I:opc7_4{1}, AMul2I:opc7_4{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMul2I:oops;
  dag InOperandList = !con(AMul2I:iops, (ins pred:$p));
  string AsmString = !strconcat(AMul2I:opc, !strconcat("${p}", AMul2I:asm));
  list<dag> Pattern = AMul2I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMul2I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMul2Ia<bits<7> AMul2Ia:opcod = { ?, ?, ?, ?, ?, ?, ? }, bits<4> AMul2Ia:opc7_4 = { ?, ?, ?, ? }, dag AMul2Ia:oops = ?, dag AMul2Ia:iops = ?, InstrItinClass AMul2Ia:itin = ?, string AMul2Ia:opc = ?, string AMul2Ia:asm = ?, list<dag> AMul2Ia:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AMul2I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AMul2Ia:opcod{6}, AMul2Ia:opcod{5}, AMul2Ia:opcod{4}, AMul2Ia:opcod{3}, AMul2Ia:opcod{2}, AMul2Ia:opcod{1}, AMul2Ia:opcod{0}, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, AMul2Ia:opc7_4{3}, AMul2Ia:opc7_4{2}, AMul2Ia:opc7_4{1}, AMul2Ia:opc7_4{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMul2Ia:oops;
  dag InOperandList = !con(AMul2Ia:iops, (ins pred:$p));
  string AsmString = !strconcat(AMul2Ia:opc, !strconcat("${p}", AMul2Ia:asm));
  list<dag> Pattern = AMul2Ia:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMul2Ia:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMulDualI<bit AMulDualI:long = ?, bit AMulDualI:sub = ?, bit AMulDualI:swap = ?, dag AMulDualI:oops = ?, dag AMulDualI:iops = ?, InstrItinClass AMulDualI:itin = ?, string AMulDualI:opc = ?, string AMulDualI:asm = ?> {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, AMulDualI:long, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, AMulDualI:sub, AMulDualI:swap, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMulDualI:oops;
  dag InOperandList = !con(AMulDualI:iops, (ins pred:$p));
  string AsmString = !strconcat(AMulDualI:opc, !strconcat("${p}", AMulDualI:asm));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMulDualI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMulDualI64<bit AMulDualI64:long = ?, bit AMulDualI64:sub = ?, bit AMulDualI64:swap = ?, dag AMulDualI64:oops = ?, dag AMulDualI64:iops = ?, InstrItinClass AMulDualI64:itin = ?, string AMulDualI64:opc = ?, string AMulDualI64:asm = ?> {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, AMulDualI64:long, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, AMulDualI64:sub, AMulDualI64:swap, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMulDualI64:oops;
  dag InOperandList = !con(AMulDualI64:iops, (ins pred:$p));
  string AsmString = !strconcat(AMulDualI64:opc, !strconcat("${p}", AMulDualI64:asm));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMulDualI64:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMulDualIa<bit AMulDualIa:long = ?, bit AMulDualIa:sub = ?, bit AMulDualIa:swap = ?, dag AMulDualIa:oops = ?, dag AMulDualIa:iops = ?, InstrItinClass AMulDualIa:itin = ?, string AMulDualIa:opc = ?, string AMulDualIa:asm = ?> {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, AMulDualIa:long, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, AMulDualIa:sub, AMulDualIa:swap, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMulDualIa:oops;
  dag InOperandList = !con(AMulDualIa:iops, (ins pred:$p));
  string AsmString = !strconcat(AMulDualIa:opc, !strconcat("${p}", AMulDualIa:asm));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMulDualIa:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMulDualIbase<bit AMulDualIbase:long = ?, bit AMulDualIbase:sub = ?, bit AMulDualIbase:swap = ?, dag AMulDualIbase:oops = ?, dag AMulDualIbase:iops = ?, InstrItinClass AMulDualIbase:itin = ?, string AMulDualIbase:opc = ?, string AMulDualIbase:asm = ?> {	// Instruction InstTemplate Encoding InstARM I AI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, AMulDualIbase:long, 0, 0, ?, ?, ?, ?, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, AMulDualIbase:sub, AMulDualIbase:swap, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMulDualIbase:oops;
  dag InOperandList = !con(AMulDualIbase:iops, (ins pred:$p));
  string AsmString = !strconcat(AMulDualIbase:opc, !strconcat("${p}", AMulDualIbase:asm));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMulDualIbase:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMulxyI<bits<7> AMulxyI:opcod = { ?, ?, ?, ?, ?, ?, ? }, bits<2> AMulxyI:bit6_5 = { ?, ? }, dag AMulxyI:oops = ?, dag AMulxyI:iops = ?, InstrItinClass AMulxyI:itin = ?, string AMulxyI:opc = ?, string AMulxyI:asm = ?, list<dag> AMulxyI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AMulxyI:opcod{6}, AMulxyI:opcod{5}, AMulxyI:opcod{4}, AMulxyI:opcod{3}, AMulxyI:opcod{2}, AMulxyI:opcod{1}, AMulxyI:opcod{0}, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, AMulxyI:bit6_5{1}, AMulxyI:bit6_5{0}, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMulxyI:oops;
  dag InOperandList = !con(AMulxyI:iops, (ins pred:$p));
  string AsmString = !strconcat(AMulxyI:opc, !strconcat("${p}", AMulxyI:asm));
  list<dag> Pattern = AMulxyI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMulxyI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMulxyI64<bits<7> AMulxyI64:opcod = { ?, ?, ?, ?, ?, ?, ? }, bits<2> AMulxyI64:bit6_5 = { ?, ? }, dag AMulxyI64:oops = ?, dag AMulxyI64:iops = ?, InstrItinClass AMulxyI64:itin = ?, string AMulxyI64:opc = ?, string AMulxyI64:asm = ?, list<dag> AMulxyI64:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AMulxyI64:opcod{6}, AMulxyI64:opcod{5}, AMulxyI64:opcod{4}, AMulxyI64:opcod{3}, AMulxyI64:opcod{2}, AMulxyI64:opcod{1}, AMulxyI64:opcod{0}, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, AMulxyI64:bit6_5{1}, AMulxyI64:bit6_5{0}, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMulxyI64:oops;
  dag InOperandList = !con(AMulxyI64:iops, (ins pred:$p));
  string AsmString = !strconcat(AMulxyI64:opc, !strconcat("${p}", AMulxyI64:asm));
  list<dag> Pattern = AMulxyI64:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMulxyI64:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMulxyIa<bits<7> AMulxyIa:opcod = { ?, ?, ?, ?, ?, ?, ? }, bits<2> AMulxyIa:bit6_5 = { ?, ? }, dag AMulxyIa:oops = ?, dag AMulxyIa:iops = ?, InstrItinClass AMulxyIa:itin = ?, string AMulxyIa:opc = ?, string AMulxyIa:asm = ?, list<dag> AMulxyIa:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AMulxyIa:opcod{6}, AMulxyIa:opcod{5}, AMulxyIa:opcod{4}, AMulxyIa:opcod{3}, AMulxyIa:opcod{2}, AMulxyIa:opcod{1}, AMulxyIa:opcod{0}, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, AMulxyIa:bit6_5{1}, AMulxyIa:bit6_5{0}, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMulxyIa:oops;
  dag InOperandList = !con(AMulxyIa:iops, (ins pred:$p));
  string AsmString = !strconcat(AMulxyIa:opc, !strconcat("${p}", AMulxyIa:asm));
  list<dag> Pattern = AMulxyIa:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMulxyIa:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
class AMulxyIbase<bits<7> AMulxyIbase:opcod = { ?, ?, ?, ?, ?, ?, ? }, bits<2> AMulxyIbase:bit6_5 = { ?, ? }, dag AMulxyIbase:oops = ?, dag AMulxyIbase:iops = ?, InstrItinClass AMulxyIbase:itin = ?, string AMulxyIbase:opc = ?, string AMulxyIbase:asm = ?, list<dag> AMulxyIbase:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AMulxyIbase:opcod{6}, AMulxyIbase:opcod{5}, AMulxyIbase:opcod{4}, AMulxyIbase:opcod{3}, AMulxyIbase:opcod{2}, AMulxyIbase:opcod{1}, AMulxyIbase:opcod{0}, 0, ?, ?, ?, ?, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, AMulxyIbase:bit6_5{1}, AMulxyIbase:bit6_5{0}, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AMulxyIbase:oops;
  dag InOperandList = !con(AMulxyIbase:iops, (ins pred:$p));
  string AsmString = !strconcat(AMulxyIbase:opc, !strconcat("${p}", AMulxyIbase:asm));
  list<dag> Pattern = AMulxyIbase:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AMulxyIbase:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class APKHI<bits<8> APKHI:opcod = { ?, ?, ?, ?, ?, ?, ?, ? }, bit APKHI:tb = ?, dag APKHI:oops = ?, dag APKHI:iops = ?, InstrItinClass APKHI:itin = ?, string APKHI:opc = ?, string APKHI:asm = ?, list<dag> APKHI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, APKHI:opcod{7}, APKHI:opcod{6}, APKHI:opcod{5}, APKHI:opcod{4}, APKHI:opcod{3}, APKHI:opcod{2}, APKHI:opcod{1}, APKHI:opcod{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{4}, sh{3}, sh{2}, sh{1}, sh{0}, APKHI:tb, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = APKHI:oops;
  dag InOperandList = !con(APKHI:iops, (ins pred:$p));
  string AsmString = !strconcat(APKHI:opc, !strconcat("${p}", APKHI:asm));
  list<dag> Pattern = APKHI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = APKHI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ArithMiscFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> sh = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ARMAsmPseudo<string ARMAsmPseudo:asm = ?, dag ARMAsmPseudo:iops = ?, dag ARMAsmPseudo:oops = (outs)> {	// Instruction InstTemplate AsmPseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = ARMAsmPseudo:oops;
  dag InOperandList = ARMAsmPseudo:iops;
  string AsmString = ARMAsmPseudo:asm;
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class ARMFReg<bits<16> ARMFReg:Enc = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? }, string ARMFReg:n = ?> {	// Register
  string Namespace = "ARM";
  string AsmName = ARMFReg:n;
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { ARMFReg:Enc{15}, ARMFReg:Enc{14}, ARMFReg:Enc{13}, ARMFReg:Enc{12}, ARMFReg:Enc{11}, ARMFReg:Enc{10}, ARMFReg:Enc{9}, ARMFReg:Enc{8}, ARMFReg:Enc{7}, ARMFReg:Enc{6}, ARMFReg:Enc{5}, ARMFReg:Enc{4}, ARMFReg:Enc{3}, ARMFReg:Enc{2}, ARMFReg:Enc{1}, ARMFReg:Enc{0} };
  bit isArtificial = 0;
  string NAME = ?;
}
class ARMInstAlias<string ARMInstAlias:Asm = ?, dag ARMInstAlias:Result = ?, bit ARMInstAlias:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = ARMInstAlias:Asm;
  dag ResultInst = ARMInstAlias:Result;
  int EmitPriority = !cast<int>(ARMInstAlias:EmitPriority);
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class ARMInstSubst<string ARMInstSubst:Asm = ?, dag ARMInstSubst:Result = ?, bit ARMInstSubst:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = ARMInstSubst:Asm;
  dag ResultInst = ARMInstSubst:Result;
  int EmitPriority = !cast<int>(ARMInstSubst:EmitPriority);
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class ARMPat<dag ARMPat:pattern = ?, dag ARMPat:result = ?> {	// Pattern Pat
  dag PatternToMatch = ARMPat:pattern;
  list<dag> ResultInstrs = [ARMPat:result];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
class ARMPseudoExpand<dag ARMPseudoExpand:oops = ?, dag ARMPseudoExpand:iops = ?, int ARMPseudoExpand:sz = ?, InstrItinClass ARMPseudoExpand:itin = ?, list<dag> ARMPseudoExpand:pattern = ?, dag ARMPseudoExpand:Result = ?> {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion
  string Namespace = "ARM";
  dag OutOperandList = ARMPseudoExpand:oops;
  dag InOperandList = ARMPseudoExpand:iops;
  string AsmString = "";
  list<dag> Pattern = ARMPseudoExpand:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = ARMPseudoExpand:sz;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ARMPseudoExpand:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = ARMPseudoExpand:Result;
  string NAME = ?;
}
class ARMPseudoInst<dag ARMPseudoInst:oops = ?, dag ARMPseudoInst:iops = ?, int ARMPseudoInst:sz = ?, InstrItinClass ARMPseudoInst:itin = ?, list<dag> ARMPseudoInst:pattern = ?> {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = ARMPseudoInst:oops;
  dag InOperandList = ARMPseudoInst:iops;
  string AsmString = "";
  list<dag> Pattern = ARMPseudoInst:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = ARMPseudoInst:sz;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ARMPseudoInst:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class ARMReg<bits<16> ARMReg:Enc = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? }, string ARMReg:n = ?, list<Register> ARMReg:subregs = []> {	// Register
  string Namespace = "ARM";
  string AsmName = ARMReg:n;
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = ARMReg:subregs;
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { ARMReg:Enc{15}, ARMReg:Enc{14}, ARMReg:Enc{13}, ARMReg:Enc{12}, ARMReg:Enc{11}, ARMReg:Enc{10}, ARMReg:Enc{9}, ARMReg:Enc{8}, ARMReg:Enc{7}, ARMReg:Enc{6}, ARMReg:Enc{5}, ARMReg:Enc{4}, ARMReg:Enc{3}, ARMReg:Enc{2}, ARMReg:Enc{1}, ARMReg:Enc{0} };
  bit isArtificial = 0;
  string NAME = ?;
}
class ARMV5MOPat<dag ARMV5MOPat:pattern = ?, dag ARMV5MOPat:result = ?> {	// Pattern Pat
  dag PatternToMatch = ARMV5MOPat:pattern;
  list<dag> ResultInstrs = [ARMV5MOPat:result];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int AddedComplexity = 0;
  string NAME = ?;
}
class ARMV5TEPat<dag ARMV5TEPat:pattern = ?, dag ARMV5TEPat:result = ?> {	// Pattern Pat
  dag PatternToMatch = ARMV5TEPat:pattern;
  list<dag> ResultInstrs = [ARMV5TEPat:result];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
class ARMV5TPat<dag ARMV5TPat:pattern = ?, dag ARMV5TPat:result = ?> {	// Pattern Pat
  dag PatternToMatch = ARMV5TPat:pattern;
  list<dag> ResultInstrs = [ARMV5TPat:result];
  list<Predicate> Predicates = [IsARM, HasV5T];
  int AddedComplexity = 0;
  string NAME = ?;
}
class ARMV6Pat<dag ARMV6Pat:pattern = ?, dag ARMV6Pat:result = ?> {	// Pattern Pat
  dag PatternToMatch = ARMV6Pat:pattern;
  list<dag> ResultInstrs = [ARMV6Pat:result];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
class ASI5<bits<4> ASI5:opcod1 = { ?, ?, ?, ? }, bits<2> ASI5:opcod2 = { ?, ? }, dag ASI5:oops = ?, dag ASI5:iops = ?, InstrItinClass ASI5:itin = ?, string ASI5:opc = ?, string ASI5:asm = ?, list<dag> ASI5:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ASI5:opcod1{3}, ASI5:opcod1{2}, ASI5:opcod1{1}, ASI5:opcod1{0}, addr{8}, Sd{0}, ASI5:opcod2{1}, ASI5:opcod2{0}, addr{12}, addr{11}, addr{10}, addr{9}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ASI5:oops;
  dag InOperandList = !con(ASI5:iops, (ins pred:$p));
  string AsmString = !strconcat(ASI5:opc, !strconcat("${p}", ASI5:asm));
  list<dag> Pattern = ASI5:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ASI5:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode5;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ASbI<bits<5> ASbI:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ASbI:opcod2 = { ?, ? }, bit ASbI:op6 = ?, bit ASbI:op4 = ?, dag ASbI:oops = ?, dag ASbI:iops = ?, InstrItinClass ASbI:itin = ?, string ASbI:opc = ?, string ASbI:asm = ?, list<dag> ASbI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ASbI:opcod1{4}, ASbI:opcod1{3}, ASbI:opcod1{2}, ASbI:opcod1{1}, ASbI:opcod1{0}, Sd{0}, ASbI:opcod2{1}, ASbI:opcod2{0}, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, ASbI:op6, Sm{0}, ASbI:op4, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ASbI:oops;
  dag InOperandList = !con(ASbI:iops, (ins pred:$p));
  string AsmString = !strconcat(ASbI:opc, !strconcat("${p}", ASbI:asm));
  list<dag> Pattern = ASbI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ASbI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPBinaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ASbIn<bits<5> ASbIn:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ASbIn:opcod2 = { ?, ? }, bit ASbIn:op6 = ?, bit ASbIn:op4 = ?, dag ASbIn:oops = ?, dag ASbIn:iops = ?, InstrItinClass ASbIn:itin = ?, string ASbIn:opc = ?, string ASbIn:asm = ?, list<dag> ASbIn:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ASbIn:opcod1{4}, ASbIn:opcod1{3}, ASbIn:opcod1{2}, ASbIn:opcod1{1}, ASbIn:opcod1{0}, Sd{0}, ASbIn:opcod2{1}, ASbIn:opcod2{0}, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, ASbIn:op6, Sm{0}, ASbIn:op4, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ASbIn:oops;
  dag InOperandList = !con(ASbIn:iops, (ins pred:$p));
  string AsmString = !strconcat(ASbIn:opc, !strconcat("${p}", ASbIn:asm));
  list<dag> Pattern = ASbIn:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ASbIn:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPBinaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ASbInp<bits<5> ASbInp:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ASbInp:opcod2 = { ?, ? }, bit ASbInp:opcod3 = ?, dag ASbInp:oops = ?, dag ASbInp:iops = ?, InstrItinClass ASbInp:itin = ?, string ASbInp:asm = ?, list<dag> ASbInp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPXI
  field bits<32> Inst = { 1, 1, 1, 1, ASbInp:opcod1{4}, ASbInp:opcod1{3}, ASbInp:opcod1{2}, ASbInp:opcod1{1}, ASbInp:opcod1{0}, Sd{0}, ASbInp:opcod2{1}, ASbInp:opcod2{0}, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, ASbInp:opcod3, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ASbInp:oops;
  dag InOperandList = ASbInp:iops;
  string AsmString = ASbInp:asm;
  list<dag> Pattern = ASbInp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ASbInp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPBinaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ASuI<bits<5> ASuI:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ASuI:opcod2 = { ?, ? }, bits<4> ASuI:opcod3 = { ?, ?, ?, ? }, bits<2> ASuI:opcod4 = { ?, ? }, bit ASuI:opcod5 = ?, dag ASuI:oops = ?, dag ASuI:iops = ?, InstrItinClass ASuI:itin = ?, string ASuI:opc = ?, string ASuI:asm = ?, list<dag> ASuI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ASuI:opcod1{4}, ASuI:opcod1{3}, ASuI:opcod1{2}, ASuI:opcod1{1}, ASuI:opcod1{0}, Sd{0}, ASuI:opcod2{1}, ASuI:opcod2{0}, ASuI:opcod3{3}, ASuI:opcod3{2}, ASuI:opcod3{1}, ASuI:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, ASuI:opcod4{1}, ASuI:opcod4{0}, Sm{0}, ASuI:opcod5, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ASuI:oops;
  dag InOperandList = !con(ASuI:iops, (ins pred:$p));
  string AsmString = !strconcat(ASuI:opc, !strconcat("${p}", ASuI:asm));
  list<dag> Pattern = ASuI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ASuI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPUnaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ASuIn<bits<5> ASuIn:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ASuIn:opcod2 = { ?, ? }, bits<4> ASuIn:opcod3 = { ?, ?, ?, ? }, bits<2> ASuIn:opcod4 = { ?, ? }, bit ASuIn:opcod5 = ?, dag ASuIn:oops = ?, dag ASuIn:iops = ?, InstrItinClass ASuIn:itin = ?, string ASuIn:opc = ?, string ASuIn:asm = ?, list<dag> ASuIn:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ASuIn:opcod1{4}, ASuIn:opcod1{3}, ASuIn:opcod1{2}, ASuIn:opcod1{1}, ASuIn:opcod1{0}, Sd{0}, ASuIn:opcod2{1}, ASuIn:opcod2{0}, ASuIn:opcod3{3}, ASuIn:opcod3{2}, ASuIn:opcod3{1}, ASuIn:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, ASuIn:opcod4{1}, ASuIn:opcod4{0}, Sm{0}, ASuIn:opcod5, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ASuIn:oops;
  dag InOperandList = !con(ASuIn:iops, (ins pred:$p));
  string AsmString = !strconcat(ASuIn:opc, !strconcat("${p}", ASuIn:asm));
  list<dag> Pattern = ASuIn:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ASuIn:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPUnaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class ASuInp<bits<5> ASuInp:opcod1 = { ?, ?, ?, ?, ? }, bits<2> ASuInp:opcod2 = { ?, ? }, bits<4> ASuInp:opcod3 = { ?, ?, ?, ? }, bits<2> ASuInp:opcod4 = { ?, ? }, bit ASuInp:opcod5 = ?, dag ASuInp:oops = ?, dag ASuInp:iops = ?, InstrItinClass ASuInp:itin = ?, string ASuInp:asm = ?, list<dag> ASuInp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPXI
  field bits<32> Inst = { 1, 1, 1, 1, ASuInp:opcod1{4}, ASuInp:opcod1{3}, ASuInp:opcod1{2}, ASuInp:opcod1{1}, ASuInp:opcod1{0}, Sd{0}, ASuInp:opcod2{1}, ASuInp:opcod2{0}, ASuInp:opcod3{3}, ASuInp:opcod3{2}, ASuInp:opcod3{1}, ASuInp:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, ASuInp:opcod4{1}, ASuInp:opcod4{0}, Sm{0}, ASuInp:opcod5, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ASuInp:oops;
  dag InOperandList = ASuInp:iops;
  string AsmString = ASuInp:asm;
  list<dag> Pattern = ASuInp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ASuInp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPUnaryFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1I<bits<5> AVConv1I:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1I:opcod2 = { ?, ? }, bits<4> AVConv1I:opcod3 = { ?, ?, ?, ? }, bits<4> AVConv1I:opcod4 = { ?, ?, ?, ? }, dag AVConv1I:oops = ?, dag AVConv1I:iops = ?, InstrItinClass AVConv1I:itin = ?, string AVConv1I:opc = ?, string AVConv1I:asm = ?, list<dag> AVConv1I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1I:opcod1{4}, AVConv1I:opcod1{3}, AVConv1I:opcod1{2}, AVConv1I:opcod1{1}, AVConv1I:opcod1{0}, ?, AVConv1I:opcod2{1}, AVConv1I:opcod2{0}, AVConv1I:opcod3{3}, AVConv1I:opcod3{2}, AVConv1I:opcod3{1}, AVConv1I:opcod3{0}, ?, ?, ?, ?, AVConv1I:opcod4{3}, AVConv1I:opcod4{2}, AVConv1I:opcod4{1}, AVConv1I:opcod4{0}, ?, 1, ?, 0, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1I:oops;
  dag InOperandList = !con(AVConv1I:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1I:opc, !strconcat("${p}", AVConv1I:asm));
  list<dag> Pattern = AVConv1I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1IDs_Encode<bits<5> AVConv1IDs_Encode:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1IDs_Encode:opcod2 = { ?, ? }, bits<4> AVConv1IDs_Encode:opcod3 = { ?, ?, ?, ? }, bits<4> AVConv1IDs_Encode:opcod4 = { ?, ?, ?, ? }, dag AVConv1IDs_Encode:oops = ?, dag AVConv1IDs_Encode:iops = ?, InstrItinClass AVConv1IDs_Encode:itin = ?, string AVConv1IDs_Encode:opc = ?, string AVConv1IDs_Encode:asm = ?, list<dag> AVConv1IDs_Encode:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1IDs_Encode:opcod1{4}, AVConv1IDs_Encode:opcod1{3}, AVConv1IDs_Encode:opcod1{2}, AVConv1IDs_Encode:opcod1{1}, AVConv1IDs_Encode:opcod1{0}, Dd{4}, AVConv1IDs_Encode:opcod2{1}, AVConv1IDs_Encode:opcod2{0}, AVConv1IDs_Encode:opcod3{3}, AVConv1IDs_Encode:opcod3{2}, AVConv1IDs_Encode:opcod3{1}, AVConv1IDs_Encode:opcod3{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, AVConv1IDs_Encode:opcod4{3}, AVConv1IDs_Encode:opcod4{2}, AVConv1IDs_Encode:opcod4{1}, AVConv1IDs_Encode:opcod4{0}, ?, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1IDs_Encode:oops;
  dag InOperandList = !con(AVConv1IDs_Encode:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1IDs_Encode:opc, !strconcat("${p}", AVConv1IDs_Encode:asm));
  list<dag> Pattern = AVConv1IDs_Encode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1IDs_Encode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1IHs_Encode<bits<5> AVConv1IHs_Encode:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1IHs_Encode:opcod2 = { ?, ? }, bits<4> AVConv1IHs_Encode:opcod3 = { ?, ?, ?, ? }, bits<4> AVConv1IHs_Encode:opcod4 = { ?, ?, ?, ? }, dag AVConv1IHs_Encode:oops = ?, dag AVConv1IHs_Encode:iops = ?, InstrItinClass AVConv1IHs_Encode:itin = ?, string AVConv1IHs_Encode:opc = ?, string AVConv1IHs_Encode:asm = ?, list<dag> AVConv1IHs_Encode:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1IHs_Encode:opcod1{4}, AVConv1IHs_Encode:opcod1{3}, AVConv1IHs_Encode:opcod1{2}, AVConv1IHs_Encode:opcod1{1}, AVConv1IHs_Encode:opcod1{0}, Sd{0}, AVConv1IHs_Encode:opcod2{1}, AVConv1IHs_Encode:opcod2{0}, AVConv1IHs_Encode:opcod3{3}, AVConv1IHs_Encode:opcod3{2}, AVConv1IHs_Encode:opcod3{1}, AVConv1IHs_Encode:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, AVConv1IHs_Encode:opcod4{3}, AVConv1IHs_Encode:opcod4{2}, AVConv1IHs_Encode:opcod4{1}, AVConv1IHs_Encode:opcod4{0}, ?, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1IHs_Encode:oops;
  dag InOperandList = !con(AVConv1IHs_Encode:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1IHs_Encode:opc, !strconcat("${p}", AVConv1IHs_Encode:asm));
  list<dag> Pattern = AVConv1IHs_Encode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1IHs_Encode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1In<bits<5> AVConv1In:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1In:opcod2 = { ?, ? }, bits<4> AVConv1In:opcod3 = { ?, ?, ?, ? }, bits<4> AVConv1In:opcod4 = { ?, ?, ?, ? }, dag AVConv1In:oops = ?, dag AVConv1In:iops = ?, InstrItinClass AVConv1In:itin = ?, string AVConv1In:opc = ?, string AVConv1In:asm = ?, list<dag> AVConv1In:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1In:opcod1{4}, AVConv1In:opcod1{3}, AVConv1In:opcod1{2}, AVConv1In:opcod1{1}, AVConv1In:opcod1{0}, ?, AVConv1In:opcod2{1}, AVConv1In:opcod2{0}, AVConv1In:opcod3{3}, AVConv1In:opcod3{2}, AVConv1In:opcod3{1}, AVConv1In:opcod3{0}, ?, ?, ?, ?, AVConv1In:opcod4{3}, AVConv1In:opcod4{2}, AVConv1In:opcod4{1}, AVConv1In:opcod4{0}, ?, 1, ?, 0, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1In:oops;
  dag InOperandList = !con(AVConv1In:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1In:opc, !strconcat("${p}", AVConv1In:asm));
  list<dag> Pattern = AVConv1In:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1In:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1InSs_Encode<bits<5> AVConv1InSs_Encode:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1InSs_Encode:opcod2 = { ?, ? }, bits<4> AVConv1InSs_Encode:opcod3 = { ?, ?, ?, ? }, bits<4> AVConv1InSs_Encode:opcod4 = { ?, ?, ?, ? }, dag AVConv1InSs_Encode:oops = ?, dag AVConv1InSs_Encode:iops = ?, InstrItinClass AVConv1InSs_Encode:itin = ?, string AVConv1InSs_Encode:opc = ?, string AVConv1InSs_Encode:asm = ?, list<dag> AVConv1InSs_Encode:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1In
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1InSs_Encode:opcod1{4}, AVConv1InSs_Encode:opcod1{3}, AVConv1InSs_Encode:opcod1{2}, AVConv1InSs_Encode:opcod1{1}, AVConv1InSs_Encode:opcod1{0}, Sd{0}, AVConv1InSs_Encode:opcod2{1}, AVConv1InSs_Encode:opcod2{0}, AVConv1InSs_Encode:opcod3{3}, AVConv1InSs_Encode:opcod3{2}, AVConv1InSs_Encode:opcod3{1}, AVConv1InSs_Encode:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, AVConv1InSs_Encode:opcod4{3}, AVConv1InSs_Encode:opcod4{2}, AVConv1InSs_Encode:opcod4{1}, AVConv1InSs_Encode:opcod4{0}, ?, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1InSs_Encode:oops;
  dag InOperandList = !con(AVConv1InSs_Encode:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1InSs_Encode:opc, !strconcat("${p}", AVConv1InSs_Encode:asm));
  list<dag> Pattern = AVConv1InSs_Encode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1InSs_Encode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1InsS_Encode<bits<5> AVConv1InsS_Encode:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1InsS_Encode:opcod2 = { ?, ? }, bits<4> AVConv1InsS_Encode:opcod3 = { ?, ?, ?, ? }, bits<4> AVConv1InsS_Encode:opcod4 = { ?, ?, ?, ? }, dag AVConv1InsS_Encode:oops = ?, dag AVConv1InsS_Encode:iops = ?, InstrItinClass AVConv1InsS_Encode:itin = ?, string AVConv1InsS_Encode:opc = ?, string AVConv1InsS_Encode:asm = ?, list<dag> AVConv1InsS_Encode:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1In
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1InsS_Encode:opcod1{4}, AVConv1InsS_Encode:opcod1{3}, AVConv1InsS_Encode:opcod1{2}, AVConv1InsS_Encode:opcod1{1}, AVConv1InsS_Encode:opcod1{0}, Sd{0}, AVConv1InsS_Encode:opcod2{1}, AVConv1InsS_Encode:opcod2{0}, AVConv1InsS_Encode:opcod3{3}, AVConv1InsS_Encode:opcod3{2}, AVConv1InsS_Encode:opcod3{1}, AVConv1InsS_Encode:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, AVConv1InsS_Encode:opcod4{3}, AVConv1InsS_Encode:opcod4{2}, AVConv1InsS_Encode:opcod4{1}, AVConv1InsS_Encode:opcod4{0}, ?, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1InsS_Encode:oops;
  dag InOperandList = !con(AVConv1InsS_Encode:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1InsS_Encode:opc, !strconcat("${p}", AVConv1InsS_Encode:asm));
  list<dag> Pattern = AVConv1InsS_Encode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1InsS_Encode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1IsD_Encode<bits<5> AVConv1IsD_Encode:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1IsD_Encode:opcod2 = { ?, ? }, bits<4> AVConv1IsD_Encode:opcod3 = { ?, ?, ?, ? }, bits<4> AVConv1IsD_Encode:opcod4 = { ?, ?, ?, ? }, dag AVConv1IsD_Encode:oops = ?, dag AVConv1IsD_Encode:iops = ?, InstrItinClass AVConv1IsD_Encode:itin = ?, string AVConv1IsD_Encode:opc = ?, string AVConv1IsD_Encode:asm = ?, list<dag> AVConv1IsD_Encode:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1IsD_Encode:opcod1{4}, AVConv1IsD_Encode:opcod1{3}, AVConv1IsD_Encode:opcod1{2}, AVConv1IsD_Encode:opcod1{1}, AVConv1IsD_Encode:opcod1{0}, Sd{0}, AVConv1IsD_Encode:opcod2{1}, AVConv1IsD_Encode:opcod2{0}, AVConv1IsD_Encode:opcod3{3}, AVConv1IsD_Encode:opcod3{2}, AVConv1IsD_Encode:opcod3{1}, AVConv1IsD_Encode:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, AVConv1IsD_Encode:opcod4{3}, AVConv1IsD_Encode:opcod4{2}, AVConv1IsD_Encode:opcod4{1}, AVConv1IsD_Encode:opcod4{0}, ?, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1IsD_Encode:oops;
  dag InOperandList = !con(AVConv1IsD_Encode:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1IsD_Encode:opc, !strconcat("${p}", AVConv1IsD_Encode:asm));
  list<dag> Pattern = AVConv1IsD_Encode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1IsD_Encode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1IsH_Encode<bits<5> AVConv1IsH_Encode:opcod1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1IsH_Encode:opcod2 = { ?, ? }, bits<4> AVConv1IsH_Encode:opcod3 = { ?, ?, ?, ? }, bits<4> AVConv1IsH_Encode:opcod4 = { ?, ?, ?, ? }, dag AVConv1IsH_Encode:oops = ?, dag AVConv1IsH_Encode:iops = ?, InstrItinClass AVConv1IsH_Encode:itin = ?, string AVConv1IsH_Encode:opc = ?, string AVConv1IsH_Encode:asm = ?, list<dag> AVConv1IsH_Encode:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1IsH_Encode:opcod1{4}, AVConv1IsH_Encode:opcod1{3}, AVConv1IsH_Encode:opcod1{2}, AVConv1IsH_Encode:opcod1{1}, AVConv1IsH_Encode:opcod1{0}, Sd{0}, AVConv1IsH_Encode:opcod2{1}, AVConv1IsH_Encode:opcod2{0}, AVConv1IsH_Encode:opcod3{3}, AVConv1IsH_Encode:opcod3{2}, AVConv1IsH_Encode:opcod3{1}, AVConv1IsH_Encode:opcod3{0}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, AVConv1IsH_Encode:opcod4{3}, AVConv1IsH_Encode:opcod4{2}, AVConv1IsH_Encode:opcod4{1}, AVConv1IsH_Encode:opcod4{0}, ?, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1IsH_Encode:oops;
  dag InOperandList = !con(AVConv1IsH_Encode:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1IsH_Encode:opc, !strconcat("${p}", AVConv1IsH_Encode:asm));
  list<dag> Pattern = AVConv1IsH_Encode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1IsH_Encode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1XI<bits<5> AVConv1XI:op1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1XI:op2 = { ?, ? }, bits<4> AVConv1XI:op3 = { ?, ?, ?, ? }, bits<4> AVConv1XI:op4 = { ?, ?, ?, ? }, bit AVConv1XI:op5 = ?, dag AVConv1XI:oops = ?, dag AVConv1XI:iops = ?, InstrItinClass AVConv1XI:itin = ?, string AVConv1XI:opc = ?, string AVConv1XI:asm = ?, list<dag> AVConv1XI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1XI:op1{4}, AVConv1XI:op1{3}, AVConv1XI:op1{2}, AVConv1XI:op1{1}, AVConv1XI:op1{0}, ?, AVConv1XI:op2{1}, AVConv1XI:op2{0}, AVConv1XI:op3{3}, AVConv1XI:op3{2}, AVConv1XI:op3{1}, AVConv1XI:op3{0}, ?, ?, ?, ?, AVConv1XI:op4{3}, AVConv1XI:op4{2}, AVConv1XI:op4{1}, AVConv1XI:op4{0}, AVConv1XI:op5, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1XI:oops;
  dag InOperandList = !con(AVConv1XI:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1XI:opc, !strconcat("${p}", AVConv1XI:asm));
  list<dag> Pattern = AVConv1XI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1XI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1XInsD_Encode<bits<5> AVConv1XInsD_Encode:op1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1XInsD_Encode:op2 = { ?, ? }, bits<4> AVConv1XInsD_Encode:op3 = { ?, ?, ?, ? }, bits<4> AVConv1XInsD_Encode:op4 = { ?, ?, ?, ? }, bit AVConv1XInsD_Encode:op5 = ?, dag AVConv1XInsD_Encode:oops = ?, dag AVConv1XInsD_Encode:iops = ?, InstrItinClass AVConv1XInsD_Encode:itin = ?, string AVConv1XInsD_Encode:opc = ?, string AVConv1XInsD_Encode:asm = ?, list<dag> AVConv1XInsD_Encode:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1XInsD_Encode:op1{4}, AVConv1XInsD_Encode:op1{3}, AVConv1XInsD_Encode:op1{2}, AVConv1XInsD_Encode:op1{1}, AVConv1XInsD_Encode:op1{0}, dst{4}, AVConv1XInsD_Encode:op2{1}, AVConv1XInsD_Encode:op2{0}, AVConv1XInsD_Encode:op3{3}, AVConv1XInsD_Encode:op3{2}, AVConv1XInsD_Encode:op3{1}, AVConv1XInsD_Encode:op3{0}, dst{3}, dst{2}, dst{1}, dst{0}, AVConv1XInsD_Encode:op4{3}, AVConv1XInsD_Encode:op4{2}, AVConv1XInsD_Encode:op4{1}, AVConv1XInsD_Encode:op4{0}, AVConv1XInsD_Encode:op5, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1XInsD_Encode:oops;
  dag InOperandList = !con(AVConv1XInsD_Encode:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1XInsD_Encode:opc, !strconcat("${p}", AVConv1XInsD_Encode:asm));
  list<dag> Pattern = AVConv1XInsD_Encode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1XInsD_Encode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv1XInsS_Encode<bits<5> AVConv1XInsS_Encode:op1 = { ?, ?, ?, ?, ? }, bits<2> AVConv1XInsS_Encode:op2 = { ?, ? }, bits<4> AVConv1XInsS_Encode:op3 = { ?, ?, ?, ? }, bits<4> AVConv1XInsS_Encode:op4 = { ?, ?, ?, ? }, bit AVConv1XInsS_Encode:op5 = ?, dag AVConv1XInsS_Encode:oops = ?, dag AVConv1XInsS_Encode:iops = ?, InstrItinClass AVConv1XInsS_Encode:itin = ?, string AVConv1XInsS_Encode:opc = ?, string AVConv1XInsS_Encode:asm = ?, list<dag> AVConv1XInsS_Encode:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv1XInsS_Encode:op1{4}, AVConv1XInsS_Encode:op1{3}, AVConv1XInsS_Encode:op1{2}, AVConv1XInsS_Encode:op1{1}, AVConv1XInsS_Encode:op1{0}, dst{0}, AVConv1XInsS_Encode:op2{1}, AVConv1XInsS_Encode:op2{0}, AVConv1XInsS_Encode:op3{3}, AVConv1XInsS_Encode:op3{2}, AVConv1XInsS_Encode:op3{1}, AVConv1XInsS_Encode:op3{0}, dst{4}, dst{3}, dst{2}, dst{1}, AVConv1XInsS_Encode:op4{3}, AVConv1XInsS_Encode:op4{2}, AVConv1XInsS_Encode:op4{1}, AVConv1XInsS_Encode:op4{0}, AVConv1XInsS_Encode:op5, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv1XInsS_Encode:oops;
  dag InOperandList = !con(AVConv1XInsS_Encode:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv1XInsS_Encode:opc, !strconcat("${p}", AVConv1XInsS_Encode:asm));
  list<dag> Pattern = AVConv1XInsS_Encode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv1XInsS_Encode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv1Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv2I<bits<8> AVConv2I:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> AVConv2I:opcod2 = { ?, ?, ?, ? }, dag AVConv2I:oops = ?, dag AVConv2I:iops = ?, InstrItinClass AVConv2I:itin = ?, string AVConv2I:opc = ?, string AVConv2I:asm = ?, list<dag> AVConv2I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv2I:opcod1{7}, AVConv2I:opcod1{6}, AVConv2I:opcod1{5}, AVConv2I:opcod1{4}, AVConv2I:opcod1{3}, AVConv2I:opcod1{2}, AVConv2I:opcod1{1}, AVConv2I:opcod1{0}, ?, ?, ?, ?, ?, ?, ?, ?, AVConv2I:opcod2{3}, AVConv2I:opcod2{2}, AVConv2I:opcod2{1}, AVConv2I:opcod2{0}, ?, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv2I:oops;
  dag InOperandList = !con(AVConv2I:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv2I:opc, !strconcat("${p}", AVConv2I:asm));
  list<dag> Pattern = AVConv2I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv2I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv2Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv3I<bits<8> AVConv3I:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> AVConv3I:opcod2 = { ?, ?, ?, ? }, dag AVConv3I:oops = ?, dag AVConv3I:iops = ?, InstrItinClass AVConv3I:itin = ?, string AVConv3I:opc = ?, string AVConv3I:asm = ?, list<dag> AVConv3I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv3I:opcod1{7}, AVConv3I:opcod1{6}, AVConv3I:opcod1{5}, AVConv3I:opcod1{4}, AVConv3I:opcod1{3}, AVConv3I:opcod1{2}, AVConv3I:opcod1{1}, AVConv3I:opcod1{0}, ?, ?, ?, ?, ?, ?, ?, ?, AVConv3I:opcod2{3}, AVConv3I:opcod2{2}, AVConv3I:opcod2{1}, AVConv3I:opcod2{0}, ?, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv3I:oops;
  dag InOperandList = !con(AVConv3I:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv3I:opc, !strconcat("${p}", AVConv3I:asm));
  list<dag> Pattern = AVConv3I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv3I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv3Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv4I<bits<8> AVConv4I:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> AVConv4I:opcod2 = { ?, ?, ?, ? }, dag AVConv4I:oops = ?, dag AVConv4I:iops = ?, InstrItinClass AVConv4I:itin = ?, string AVConv4I:opc = ?, string AVConv4I:asm = ?, list<dag> AVConv4I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv4I:opcod1{7}, AVConv4I:opcod1{6}, AVConv4I:opcod1{5}, AVConv4I:opcod1{4}, AVConv4I:opcod1{3}, AVConv4I:opcod1{2}, AVConv4I:opcod1{1}, AVConv4I:opcod1{0}, ?, ?, ?, ?, ?, ?, ?, ?, AVConv4I:opcod2{3}, AVConv4I:opcod2{2}, AVConv4I:opcod2{1}, AVConv4I:opcod2{0}, ?, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv4I:oops;
  dag InOperandList = !con(AVConv4I:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv4I:opc, !strconcat("${p}", AVConv4I:asm));
  list<dag> Pattern = AVConv4I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv4I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv4Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AVConv5I<bits<8> AVConv5I:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> AVConv5I:opcod2 = { ?, ?, ?, ? }, dag AVConv5I:oops = ?, dag AVConv5I:iops = ?, InstrItinClass AVConv5I:itin = ?, string AVConv5I:opc = ?, string AVConv5I:asm = ?, list<dag> AVConv5I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConv5I:opcod1{7}, AVConv5I:opcod1{6}, AVConv5I:opcod1{5}, AVConv5I:opcod1{4}, AVConv5I:opcod1{3}, AVConv5I:opcod1{2}, AVConv5I:opcod1{1}, AVConv5I:opcod1{0}, ?, ?, ?, ?, ?, ?, ?, ?, AVConv5I:opcod2{3}, AVConv5I:opcod2{2}, AVConv5I:opcod2{1}, AVConv5I:opcod2{0}, ?, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConv5I:oops;
  dag InOperandList = !con(AVConv5I:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConv5I:opc, !strconcat("${p}", AVConv5I:asm));
  list<dag> Pattern = AVConv5I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConv5I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPConv5Frm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AVConvXI<bits<8> AVConvXI:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> AVConvXI:opcod2 = { ?, ?, ?, ? }, dag AVConvXI:oops = ?, dag AVConvXI:iops = ?, Format AVConvXI:f = ?, InstrItinClass AVConvXI:itin = ?, string AVConvXI:opc = ?, string AVConvXI:asm = ?, list<dag> AVConvXI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AVConvXI:opcod1{7}, AVConvXI:opcod1{6}, AVConvXI:opcod1{5}, AVConvXI:opcod1{4}, AVConvXI:opcod1{3}, AVConvXI:opcod1{2}, AVConvXI:opcod1{1}, AVConvXI:opcod1{0}, ?, ?, ?, ?, ?, ?, ?, ?, AVConvXI:opcod2{3}, AVConvXI:opcod2{2}, AVConvXI:opcod2{1}, AVConvXI:opcod2{0}, ?, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AVConvXI:oops;
  dag InOperandList = !con(AVConvXI:iops, (ins pred:$p));
  string AsmString = !strconcat(AVConvXI:opc, !strconcat("${p}", AVConvXI:asm));
  list<dag> Pattern = AVConvXI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AVConvXI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AVConvXI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AVConvXI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class AXDI4<dag AXDI4:oops = ?, dag AXDI4:iops = ?, IndexMode AXDI4:im = ?, InstrItinClass AXDI4:itin = ?, string AXDI4:asm = ?, string AXDI4:cstr = ?, list<dag> AXDI4:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPXI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, ?, ?, regs{12}, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AXDI4:oops;
  dag InOperandList = AXDI4:iops;
  string AsmString = AXDI4:asm;
  list<dag> Pattern = AXDI4:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AXDI4:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AXDI4:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = AXDI4:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AXI<dag AXI:oops = ?, dag AXI:iops = ?, Format AXI:f = ?, InstrItinClass AXI:itin = ?, string AXI:asm = ?, list<dag> AXI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM XI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AXI:oops;
  dag InOperandList = AXI:iops;
  string AsmString = AXI:asm;
  list<dag> Pattern = AXI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AXI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AXI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AXI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class AXI1<bits<4> AXI1:opcod = { ?, ?, ?, ? }, dag AXI1:oops = ?, dag AXI1:iops = ?, Format AXI1:f = ?, InstrItinClass AXI1:itin = ?, string AXI1:asm = ?, list<dag> AXI1:pattern = ?> {	// Instruction InstTemplate Encoding InstARM XI
  field bits<32> Inst = { ?, ?, ?, ?, 0, 0, ?, AXI1:opcod{3}, AXI1:opcod{2}, AXI1:opcod{1}, AXI1:opcod{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AXI1:oops;
  dag InOperandList = AXI1:iops;
  string AsmString = AXI1:asm;
  list<dag> Pattern = AXI1:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AXI1:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AXI1:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AXI1:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class AXI4<dag AXI4:oops = ?, dag AXI4:iops = ?, IndexMode AXI4:im = ?, Format AXI4:f = ?, InstrItinClass AXI4:itin = ?, string AXI4:asm = ?, string AXI4:cstr = ?, list<dag> AXI4:pattern = ?> {	// Instruction InstTemplate Encoding InstARM XI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, ?, ?, 0, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AXI4:oops;
  dag InOperandList = AXI4:iops;
  string AsmString = AXI4:asm;
  list<dag> Pattern = AXI4:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AXI4:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AXI4:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AXI4:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = AXI4:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AXI4:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
class AXIM<dag AXIM:oops = ?, dag AXIM:iops = ?, AddrMode AXIM:am = ?, Format AXIM:f = ?, InstrItinClass AXIM:itin = ?, string AXIM:asm = ?, list<dag> AXIM:pattern = ?> {	// Instruction InstTemplate Encoding InstARM XI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AXIM:oops;
  dag InOperandList = AXIM:iops;
  string AsmString = AXIM:asm;
  list<dag> Pattern = AXIM:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AXIM:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AXIM:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AXIM:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AXIM:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class AXSI4<dag AXSI4:oops = ?, dag AXSI4:iops = ?, IndexMode AXSI4:im = ?, InstrItinClass AXSI4:itin = ?, string AXSI4:asm = ?, string AXSI4:cstr = ?, list<dag> AXSI4:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPXI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, ?, ?, regs{8}, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{12}, regs{11}, regs{10}, regs{9}, 1, 0, 1, 0, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AXSI4:oops;
  dag InOperandList = AXSI4:iops;
  string AsmString = AXSI4:asm;
  list<dag> Pattern = AXSI4:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AXSI4:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AXSI4:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = AXSI4:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AXXI4<dag AXXI4:oops = ?, dag AXXI4:iops = ?, IndexMode AXXI4:im = ?, string AXXI4:asm = ?, string AXXI4:cstr = ?, list<dag> AXXI4:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPXI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, ?, ?, 0, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AXXI4:oops;
  dag InOperandList = AXXI4:iops;
  string AsmString = AXXI4:asm;
  list<dag> Pattern = AXXI4:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = AXXI4:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = AXXI4:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class AddrMode<bits<5> AddrMode:val = { ?, ?, ?, ?, ? }> {
  bits<5> Value = { AddrMode:val{4}, AddrMode:val{3}, AddrMode:val{2}, AddrMode:val{1}, AddrMode:val{0} };
  string NAME = ?;
}
class AddrMode3 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getAddrMode3OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode3AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 3;
  string SelectFunc = "SelectAddrMode3";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
class AddrMode5 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode5Operand";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getAddrMode5OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode5AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode5";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
class AddrMode5FP16 {	// DAGOperand Operand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode5FP16Operand";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getAddrMode5FP16OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops GPR:$base, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode5FP16AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode5FP16";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
class AddrMode6Align {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode6Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6AddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm:$align);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
class AddrMode6DupAlign {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6DupAddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
class AddrMode_Imm12 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrModeImm12Operand";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getAddrModeImm12OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm12OffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrModeImm12";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
class AdvSIMD_1Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_any_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1FloatArg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1IntArg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1IntArg_Narrow_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1Vec_Load_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1Vec_Store_Lane_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1VectorArg_Expand_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1VectorArg_Float_Across_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1VectorArg_Int_Across_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1VectorArg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1VectorArg_Long_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_1VectorArg_Narrow_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2Arg_FloatCompare_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2FloatArg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2IntArg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2Scalar_Float_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2Vec_Load_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2Vec_Load_Lane_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2Vec_Store_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2Vec_Store_Lane_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2Vector2Index_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, llvm_i64_ty, anonymous_6, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2VectorArg_Compare_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2VectorArg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2VectorArg_Long_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2VectorArg_Narrow_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_20, llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_2VectorArg_Wide_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_3Vec_Load_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_3Vec_Load_Lane_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_3Vec_Store_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_3Vec_Store_Lane_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_3VectorArg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_3VectorArg_Scalar_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_20, llvm_anyvector_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_20, llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_4Vec_Load_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_4Vec_Load_Lane_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_4Vec_Store_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6, anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_4Vec_Store_Lane_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_23];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_CvtFPToFx_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_CvtFxToFP_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_Dot_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_FPToIntRounding_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_Tbl1_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_Tbl2_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_Tbl3_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_Tbl4_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_Tbx1_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_Tbx2_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_Tbx3_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AdvSIMD_Tbx4_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class AlignedVEXTq<ValueType AlignedVEXTq:DestTy = ?, ValueType AlignedVEXTq:SrcTy = ?, SDNodeXForm AlignedVEXTq:LaneCVT = ?> {	// Pattern Pat
  dag PatternToMatch = (AlignedVEXTq:DestTy (vector_extract_subvec (AlignedVEXTq:SrcTy QPR:$src), (i32 imm:$start)));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (AlignedVEXTq:SrcTy QPR:$src), (AlignedVEXTq:LaneCVT imm:$start))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
class Architecture<string Architecture:fname = ?, string Architecture:aname = ?, list<SubtargetFeature> Architecture:features = ?> {	// SubtargetFeature
  string Name = Architecture:fname;
  string Attribute = "ARMArch";
  string Value = Architecture:aname;
  string Desc = !strconcat(Architecture:aname, " architecture");
  list<SubtargetFeature> Implies = Architecture:features;
  string NAME = ?;
}
class AsI<dag AsI:oops = ?, dag AsI:iops = ?, Format AsI:f = ?, InstrItinClass AsI:itin = ?, string AsI:opc = ?, string AsI:asm = ?, list<dag> AsI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM sI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ?, ?, ?, ?, ?, ?, ?, s{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AsI:oops;
  dag InOperandList = !con(AsI:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(AsI:opc, !strconcat("${s}${p}", AsI:asm));
  list<dag> Pattern = AsI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AsI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AsI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AsI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  string NAME = ?;
}
class AsI1<bits<4> AsI1:opcod = { ?, ?, ?, ? }, dag AsI1:oops = ?, dag AsI1:iops = ?, Format AsI1:f = ?, InstrItinClass AsI1:itin = ?, string AsI1:opc = ?, string AsI1:asm = ?, list<dag> AsI1:pattern = ?> {	// Instruction InstTemplate Encoding InstARM sI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, ?, AsI1:opcod{3}, AsI1:opcod{2}, AsI1:opcod{1}, AsI1:opcod{0}, s{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AsI1:oops;
  dag InOperandList = !con(AsI1:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(AsI1:opc, !strconcat("${s}${p}", AsI1:asm));
  list<dag> Pattern = AsI1:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(AsI1:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AsI1:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = AsI1:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  string NAME = ?;
}
class AsMla1I64<bits<7> AsMla1I64:opcod = { ?, ?, ?, ?, ?, ?, ? }, dag AsMla1I64:oops = ?, dag AsMla1I64:iops = ?, InstrItinClass AsMla1I64:itin = ?, string AsMla1I64:opc = ?, string AsMla1I64:asm = ?, list<dag> AsMla1I64:pattern = ?> {	// Instruction InstTemplate Encoding InstARM sI AsMul1I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AsMla1I64:opcod{6}, AsMla1I64:opcod{5}, AsMla1I64:opcod{4}, AsMla1I64:opcod{3}, AsMla1I64:opcod{2}, AsMla1I64:opcod{1}, AsMla1I64:opcod{0}, s{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AsMla1I64:oops;
  dag InOperandList = !con(AsMla1I64:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(AsMla1I64:opc, !strconcat("${s}${p}", AsMla1I64:asm));
  list<dag> Pattern = AsMla1I64:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AsMla1I64:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
class AsMul1I<bits<7> AsMul1I:opcod = { ?, ?, ?, ?, ?, ?, ? }, dag AsMul1I:oops = ?, dag AsMul1I:iops = ?, InstrItinClass AsMul1I:itin = ?, string AsMul1I:opc = ?, string AsMul1I:asm = ?, list<dag> AsMul1I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM sI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AsMul1I:opcod{6}, AsMul1I:opcod{5}, AsMul1I:opcod{4}, AsMul1I:opcod{3}, AsMul1I:opcod{2}, AsMul1I:opcod{1}, AsMul1I:opcod{0}, s{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, 1, 0, 0, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AsMul1I:oops;
  dag InOperandList = !con(AsMul1I:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(AsMul1I:opc, !strconcat("${s}${p}", AsMul1I:asm));
  list<dag> Pattern = AsMul1I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AsMul1I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  string NAME = ?;
}
class AsMul1I32<bits<7> AsMul1I32:opcod = { ?, ?, ?, ?, ?, ?, ? }, dag AsMul1I32:oops = ?, dag AsMul1I32:iops = ?, InstrItinClass AsMul1I32:itin = ?, string AsMul1I32:opc = ?, string AsMul1I32:asm = ?, list<dag> AsMul1I32:pattern = ?> {	// Instruction InstTemplate Encoding InstARM sI AsMul1I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AsMul1I32:opcod{6}, AsMul1I32:opcod{5}, AsMul1I32:opcod{4}, AsMul1I32:opcod{3}, AsMul1I32:opcod{2}, AsMul1I32:opcod{1}, AsMul1I32:opcod{0}, s{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AsMul1I32:oops;
  dag InOperandList = !con(AsMul1I32:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(AsMul1I32:opc, !strconcat("${s}${p}", AsMul1I32:asm));
  list<dag> Pattern = AsMul1I32:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AsMul1I32:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
class AsMul1I64<bits<7> AsMul1I64:opcod = { ?, ?, ?, ?, ?, ?, ? }, dag AsMul1I64:oops = ?, dag AsMul1I64:iops = ?, InstrItinClass AsMul1I64:itin = ?, string AsMul1I64:opc = ?, string AsMul1I64:asm = ?, list<dag> AsMul1I64:pattern = ?> {	// Instruction InstTemplate Encoding InstARM sI AsMul1I
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, AsMul1I64:opcod{6}, AsMul1I64:opcod{5}, AsMul1I64:opcod{4}, AsMul1I64:opcod{3}, AsMul1I64:opcod{2}, AsMul1I64:opcod{1}, AsMul1I64:opcod{0}, s{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = AsMul1I64:oops;
  dag InOperandList = !con(AsMul1I64:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(AsMul1I64:opc, !strconcat("${s}${p}", AsMul1I64:asm));
  list<dag> Pattern = AsMul1I64:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = AsMul1I64:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
class AsmOperandClass {
  string Name = ?;
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
class AsmParser {
  string AsmParserClassName = "AsmParser";
  string AsmParserInstCleanup = "";
  bit ShouldEmitMatchRegisterName = 1;
  bit ShouldEmitMatchRegisterAltName = 0;
  bit AllowDuplicateRegisterNames = 0;
  bit HasMnemonicFirst = 1;
  bit ReportMultipleNearMisses = 0;
  string NAME = ?;
}
class AsmParserVariant {
  int Variant = 0;
  string Name = "";
  string CommentDelimiter = "";
  string RegisterPrefix = "";
  string TokenizingCharacters = "[]*!";
  string SeparatorCharacters = " 	,";
  string BreakCharacters = "";
  string NAME = ?;
}
class AsmPseudoInst<string AsmPseudoInst:asm = ?, dag AsmPseudoInst:iops = ?, dag AsmPseudoInst:oops = (outs)> {	// Instruction InstTemplate
  string Namespace = "ARM";
  dag OutOperandList = AsmPseudoInst:oops;
  dag InOperandList = AsmPseudoInst:iops;
  string AsmString = AsmPseudoInst:asm;
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class AsmWriter {
  string AsmWriterClassName = "InstPrinter";
  int PassSubtarget = 0;
  int Variant = 0;
  string NAME = ?;
}
class AssemblerPredicate<string AssemblerPredicate:cond = ?, string AssemblerPredicate:name = ""> {
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = AssemblerPredicate:cond;
  string PredicateName = AssemblerPredicate:name;
  string NAME = ?;
}
class BankedReg<string BankedReg:name = ?, bits<8> BankedReg:enc = { ?, ?, ?, ?, ?, ?, ?, ? }> {	// SearchableTable
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = BankedReg:name;
  bits<8> Encoding = { BankedReg:enc{7}, BankedReg:enc{6}, BankedReg:enc{5}, BankedReg:enc{4}, BankedReg:enc{3}, BankedReg:enc{2}, BankedReg:enc{1}, BankedReg:enc{0} };
  string NAME = ?;
}
class BaseN3VCP8ComplexOdd<bit BaseN3VCP8ComplexOdd:op23 = ?, bit BaseN3VCP8ComplexOdd:op21 = ?, bit BaseN3VCP8ComplexOdd:op4 = ?, bit BaseN3VCP8ComplexOdd:s = ?, bit BaseN3VCP8ComplexOdd:q = ?, InstrItinClass BaseN3VCP8ComplexOdd:itin = ?, dag BaseN3VCP8ComplexOdd:oops = ?, dag BaseN3VCP8ComplexOdd:iops = ?, string BaseN3VCP8ComplexOdd:opc = ?, string BaseN3VCP8ComplexOdd:dt = ?, list<dag> BaseN3VCP8ComplexOdd:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{0}, BaseN3VCP8ComplexOdd:op23, Vd{4}, BaseN3VCP8ComplexOdd:op21, BaseN3VCP8ComplexOdd:s, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, BaseN3VCP8ComplexOdd:q, Vm{4}, BaseN3VCP8ComplexOdd:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = BaseN3VCP8ComplexOdd:oops;
  dag InOperandList = BaseN3VCP8ComplexOdd:iops;
  string AsmString = !strconcat(BaseN3VCP8ComplexOdd:opc, !strconcat(".", !strconcat(BaseN3VCP8ComplexOdd:dt, "	$Vd, $Vn, $Vm, $rot")));
  list<dag> Pattern = BaseN3VCP8ComplexOdd:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = BaseN3VCP8ComplexOdd:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegCplxFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<1> rot = { ? };
  string NAME = ?;
}
class BaseN3VCP8ComplexTied<bit BaseN3VCP8ComplexTied:op21 = ?, bit BaseN3VCP8ComplexTied:op4 = ?, bit BaseN3VCP8ComplexTied:s = ?, bit BaseN3VCP8ComplexTied:q = ?, InstrItinClass BaseN3VCP8ComplexTied:itin = ?, dag BaseN3VCP8ComplexTied:oops = ?, dag BaseN3VCP8ComplexTied:iops = ?, string BaseN3VCP8ComplexTied:opc = ?, string BaseN3VCP8ComplexTied:dt = ?, list<dag> BaseN3VCP8ComplexTied:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{1}, rot{0}, Vd{4}, BaseN3VCP8ComplexTied:op21, BaseN3VCP8ComplexTied:s, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, BaseN3VCP8ComplexTied:q, Vm{4}, BaseN3VCP8ComplexTied:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = BaseN3VCP8ComplexTied:oops;
  dag InOperandList = BaseN3VCP8ComplexTied:iops;
  string AsmString = !strconcat(BaseN3VCP8ComplexTied:opc, !strconcat(".", !strconcat(BaseN3VCP8ComplexTied:dt, "	$Vd, $Vn, $Vm, $rot")));
  list<dag> Pattern = BaseN3VCP8ComplexTied:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = BaseN3VCP8ComplexTied:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegCplxFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
class BaseN3VCP8ComplexTiedLane32<bit BaseN3VCP8ComplexTiedLane32:op4 = ?, bit BaseN3VCP8ComplexTiedLane32:s = ?, bit BaseN3VCP8ComplexTiedLane32:q = ?, InstrItinClass BaseN3VCP8ComplexTiedLane32:itin = ?, dag BaseN3VCP8ComplexTiedLane32:oops = ?, dag BaseN3VCP8ComplexTiedLane32:iops = ?, string BaseN3VCP8ComplexTiedLane32:opc = ?, string BaseN3VCP8ComplexTiedLane32:dt = ?, list<dag> BaseN3VCP8ComplexTiedLane32:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3VLaneCP8
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, BaseN3VCP8ComplexTiedLane32:s, Vd{4}, rot{1}, rot{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, BaseN3VCP8ComplexTiedLane32:q, lane, BaseN3VCP8ComplexTiedLane32:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = BaseN3VCP8ComplexTiedLane32:oops;
  dag InOperandList = BaseN3VCP8ComplexTiedLane32:iops;
  string AsmString = !strconcat(BaseN3VCP8ComplexTiedLane32:opc, !strconcat(".", !strconcat(BaseN3VCP8ComplexTiedLane32:dt, "	$Vd, $Vn, $Vm$lane, $rot")));
  list<dag> Pattern = BaseN3VCP8ComplexTiedLane32:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = BaseN3VCP8ComplexTiedLane32:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegCplxFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class BaseN3VCP8ComplexTiedLane64<bit BaseN3VCP8ComplexTiedLane64:op4 = ?, bit BaseN3VCP8ComplexTiedLane64:s = ?, bit BaseN3VCP8ComplexTiedLane64:q = ?, InstrItinClass BaseN3VCP8ComplexTiedLane64:itin = ?, dag BaseN3VCP8ComplexTiedLane64:oops = ?, dag BaseN3VCP8ComplexTiedLane64:iops = ?, string BaseN3VCP8ComplexTiedLane64:opc = ?, string BaseN3VCP8ComplexTiedLane64:dt = ?, list<dag> BaseN3VCP8ComplexTiedLane64:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3VLaneCP8
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, BaseN3VCP8ComplexTiedLane64:s, Vd{4}, rot{1}, rot{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, BaseN3VCP8ComplexTiedLane64:q, Vm{4}, BaseN3VCP8ComplexTiedLane64:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = BaseN3VCP8ComplexTiedLane64:oops;
  dag InOperandList = BaseN3VCP8ComplexTiedLane64:iops;
  string AsmString = !strconcat(BaseN3VCP8ComplexTiedLane64:opc, !strconcat(".", !strconcat(BaseN3VCP8ComplexTiedLane64:dt, "	$Vd, $Vn, $Vm$lane, $rot")));
  list<dag> Pattern = BaseN3VCP8ComplexTiedLane64:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = BaseN3VCP8ComplexTiedLane64:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeNEONComplexLane64Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegCplxFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class BinOpFrag<dag BinOpFrag:res = ?> {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = BinOpFrag:res;
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
class Bypass {
  string NAME = ?;
}
class CCAction {
  string NAME = ?;
}
class CCAssignToReg<list<Register> CCAssignToReg:regList = ?> {	// CCAction
  list<Register> RegList = CCAssignToReg:regList;
  string NAME = ?;
}
class CCAssignToRegWithShadow<list<Register> CCAssignToRegWithShadow:regList = ?, list<Register> CCAssignToRegWithShadow:shadowList = ?> {	// CCAction
  list<Register> RegList = CCAssignToRegWithShadow:regList;
  list<Register> ShadowRegList = CCAssignToRegWithShadow:shadowList;
  string NAME = ?;
}
class CCAssignToStack<int CCAssignToStack:size = ?, int CCAssignToStack:align = ?> {	// CCAction
  int Size = CCAssignToStack:size;
  int Align = CCAssignToStack:align;
  string NAME = ?;
}
class CCAssignToStackWithShadow<int CCAssignToStackWithShadow:size = ?, int CCAssignToStackWithShadow:align = ?, list<Register> CCAssignToStackWithShadow:shadowList = ?> {	// CCAction
  int Size = CCAssignToStackWithShadow:size;
  int Align = CCAssignToStackWithShadow:align;
  list<Register> ShadowRegList = CCAssignToStackWithShadow:shadowList;
  string NAME = ?;
}
class CCBitConvertToType<ValueType CCBitConvertToType:destTy = ?> {	// CCAction
  ValueType DestTy = CCBitConvertToType:destTy;
  string NAME = ?;
}
class CCCustom<string CCCustom:fn = ?> {	// CCAction
  string FuncName = CCCustom:fn;
  string NAME = ?;
}
class CCDelegateTo<CallingConv CCDelegateTo:cc = ?> {	// CCAction
  CallingConv CC = CCDelegateTo:cc;
  string NAME = ?;
}
class CCIf<string CCIf:predicate = ?, CCAction CCIf:A = ?> {	// CCAction CCPredicateAction
  CCAction SubAction = CCIf:A;
  string Predicate = CCIf:predicate;
  string NAME = ?;
}
class CCIfAlign<string CCIfAlign:Align = ?, CCAction CCIfAlign:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfAlign:A;
  string Predicate = !strconcat("ArgFlags.getOrigAlign() == ", CCIfAlign:Align);
  string NAME = ?;
}
class CCIfByVal<CCAction CCIfByVal:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfByVal:A;
  string Predicate = "ArgFlags.isByVal()";
  string NAME = ?;
}
class CCIfCC<string CCIfCC:CC = ?, CCAction CCIfCC:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfCC:A;
  string Predicate = !strconcat("State.getCallingConv() == ", CCIfCC:CC);
  string NAME = ?;
}
class CCIfConsecutiveRegs<CCAction CCIfConsecutiveRegs:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfConsecutiveRegs:A;
  string Predicate = "ArgFlags.isInConsecutiveRegs()";
  string NAME = ?;
}
class CCIfInReg<CCAction CCIfInReg:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfInReg:A;
  string Predicate = "ArgFlags.isInReg()";
  string NAME = ?;
}
class CCIfNest<CCAction CCIfNest:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfNest:A;
  string Predicate = "ArgFlags.isNest()";
  string NAME = ?;
}
class CCIfNotVarArg<CCAction CCIfNotVarArg:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfNotVarArg:A;
  string Predicate = "!State.isVarArg()";
  string NAME = ?;
}
class CCIfSRet<CCAction CCIfSRet:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfSRet:A;
  string Predicate = "ArgFlags.isSRet()";
  string NAME = ?;
}
class CCIfSplit<CCAction CCIfSplit:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfSplit:A;
  string Predicate = "ArgFlags.isSplit()";
  string NAME = ?;
}
class CCIfSwiftError<CCAction CCIfSwiftError:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfSwiftError:A;
  string Predicate = "ArgFlags.isSwiftError()";
  string NAME = ?;
}
class CCIfSwiftSelf<CCAction CCIfSwiftSelf:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfSwiftSelf:A;
  string Predicate = "ArgFlags.isSwiftSelf()";
  string NAME = ?;
}
class CCIfType<list<ValueType> CCIfType:vts = ?, CCAction CCIfType:A = ?> {	// CCAction CCPredicateAction
  CCAction SubAction = CCIfType:A;
  list<ValueType> VTs = CCIfType:vts;
  string NAME = ?;
}
class CCIfVarArg<CCAction CCIfVarArg:A = ?> {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = CCIfVarArg:A;
  string Predicate = "State.isVarArg()";
  string NAME = ?;
}
class CCPassByVal<int CCPassByVal:size = ?, int CCPassByVal:align = ?> {	// CCAction
  int Size = CCPassByVal:size;
  int Align = CCPassByVal:align;
  string NAME = ?;
}
class CCPassIndirect<ValueType CCPassIndirect:destTy = ?> {	// CCAction
  ValueType DestTy = CCPassIndirect:destTy;
  string NAME = ?;
}
class CCPredicateAction<CCAction CCPredicateAction:A = ?> {	// CCAction
  CCAction SubAction = CCPredicateAction:A;
  string NAME = ?;
}
class CCPromoteToType<ValueType CCPromoteToType:destTy = ?> {	// CCAction
  ValueType DestTy = CCPromoteToType:destTy;
  string NAME = ?;
}
class CCPromoteToUpperBitsInType<ValueType CCPromoteToUpperBitsInType:destTy = ?> {	// CCAction
  ValueType DestTy = CCPromoteToUpperBitsInType:destTy;
  string NAME = ?;
}
class CPS<dag CPS:iops = ?, string CPS:asm_ops = ?> {	// Instruction InstTemplate Encoding InstARM XI AXI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, imod{1}, imod{0}, M, 0, 0, 0, 0, 0, 0, 0, 0, iflags{2}, iflags{1}, iflags{0}, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = CPS:iops;
  string AsmString = !strconcat("cps", CPS:asm_ops);
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MiscFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<2> imod = { ?, ? };
  bits<3> iflags = { ?, ?, ? };
  bits<5> mode = { ?, ?, ?, ?, ? };
  bit M = ?;
  string NAME = ?;
}
class CalleeSavedRegs<dag CalleeSavedRegs:saves = ?> {
  dag SaveList = CalleeSavedRegs:saves;
  dag OtherPreserved = ?;
  string NAME = ?;
}
class CallingConv<list<CCAction> CallingConv:actions = ?> {
  list<CCAction> Actions = CallingConv:actions;
  bit Custom = 0;
  string NAME = ?;
}
class CodePatPred<code CodePatPred:predicate = ?> {	// PatPred
  code PredicateCode = CodePatPred:predicate;
  string NAME = ?;
}
class ComboFuncData<FuncUnit ComboFuncData:ComboFunc = ?, list<FuncUnit> ComboFuncData:funclist = ?> {
  FuncUnit TheComboFunc = ComboFuncData:ComboFunc;
  list<FuncUnit> FuncList = ComboFuncData:funclist;
  string NAME = ?;
}
class ComboFuncUnits<list<ComboFuncData> ComboFuncUnits:cfd = ?> {
  list<ComboFuncData> CFD = ComboFuncUnits:cfd;
  string NAME = ?;
}
class ComplexDeprecationPredicate<string ComplexDeprecationPredicate:dep = ?> {
  string ComplexDeprecationPredicate = ComplexDeprecationPredicate:dep;
  string NAME = ?;
}
class ComplexPattern<ValueType ComplexPattern:ty = ?, int ComplexPattern:numops = ?, string ComplexPattern:fn = ?, list<SDNode> ComplexPattern:roots = [], list<SDNodeProperty> ComplexPattern:props = [], int ComplexPattern:complexity = -1> {
  ValueType Ty = ComplexPattern:ty;
  int NumOperands = ComplexPattern:numops;
  string SelectFunc = ComplexPattern:fn;
  list<SDNode> RootNodes = ComplexPattern:roots;
  list<SDNodeProperty> Properties = ComplexPattern:props;
  int Complexity = ComplexPattern:complexity;
  string NAME = ?;
}
class ComplexRotationOperand<int ComplexRotationOperand:Angle = ?, int ComplexRotationOperand:Remainder = ?, string ComplexRotationOperand:Type = ?, string ComplexRotationOperand:Diag = ?> {	// AsmOperandClass
  string Name = !strconcat("ComplexRotation", ComplexRotationOperand:Type);
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = !strconcat("isComplexRotation<", !strconcat(!cast<string>(ComplexRotationOperand:Angle), !strconcat(", ", !strconcat(!cast<string>(ComplexRotationOperand:Remainder), ">"))));
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = !strconcat("complex rotation must be ", ComplexRotationOperand:Diag);
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
class ComposedSubRegIndex<SubRegIndex ComposedSubRegIndex:A = ?, SubRegIndex ComposedSubRegIndex:B = ?> {	// SubRegIndex
  string Namespace = "";
  int Size = ComposedSubRegIndex:B.Size;
  int Offset = !if(!eq(ComposedSubRegIndex:A.Offset, -1), -1, !if(!eq(ComposedSubRegIndex:B.Offset, -1), -1, !add(ComposedSubRegIndex:A.Offset, ComposedSubRegIndex:B.Offset)));
  list<SubRegIndex> ComposedOf = [ComposedSubRegIndex:A, ComposedSubRegIndex:B];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
class CondCode {
  string NAME = ?;
}
class Crypto_AES_DataKey_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Crypto_AES_Data_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Crypto_SHA_12Schedule_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Crypto_SHA_1Hash_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Crypto_SHA_5Hash4Schedule_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Crypto_SHA_8Hash4Schedule_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Crypto_SHA_8Schedule_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class CustomCallingConv {	// CallingConv
  list<CCAction> Actions = [];
  bit Custom = 1;
  string NAME = ?;
}
class DAGOperand {
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string NAME = ?;
}
class Deprecated<SubtargetFeature Deprecated:dep = ?> {
  SubtargetFeature DeprecatedFeatureMask = Deprecated:dep;
  string NAME = ?;
}
class Domain<bits<3> Domain:val = { ?, ?, ? }> {
  bits<3> Value = { Domain:val{2}, Domain:val{1}, Domain:val{0} };
  string NAME = ?;
}
class DwarfRegAlias<Register DwarfRegAlias:reg = ?> {
  Register DwarfAlias = DwarfRegAlias:reg;
  string NAME = ?;
}
class DwarfRegNum<list<int> DwarfRegNum:Numbers = ?> {
  list<int> DwarfNumbers = DwarfRegNum:Numbers;
  string NAME = ?;
}
class Encoding {
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class Encoding16 {	// Encoding
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class FP16Pat<dag FP16Pat:pattern = ?, dag FP16Pat:result = ?> {	// Pattern Pat
  dag PatternToMatch = FP16Pat:pattern;
  list<dag> ResultInstrs = [FP16Pat:result];
  list<Predicate> Predicates = [HasFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
class FPImmLeaf<ValueType FPImmLeaf:vt = ?, code FPImmLeaf:pred = ?, SDNodeXForm FPImmLeaf:xform = NOOP_SDNodeXForm> {	// SDPatternOperator PatFrag ImmLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (FPImmLeaf:vt fpimm);
  code PredicateCode = [{}];
  code ImmediateCode = FPImmLeaf:pred;
  SDNodeXForm OperandTransform = FPImmLeaf:xform;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 1;
  bit IsAPInt = 0;
  bit IsAPFloat = 1;
  string NAME = ?;
}
class Format<bits<6> Format:val = { ?, ?, ?, ?, ?, ? }> {
  bits<6> Value = { Format:val{5}, Format:val{4}, Format:val{3}, Format:val{2}, Format:val{1}, Format:val{0} };
  string NAME = ?;
}
class FullFP16Pat<dag FullFP16Pat:pattern = ?, dag FullFP16Pat:result = ?> {	// Pattern Pat
  dag PatternToMatch = FullFP16Pat:pattern;
  list<dag> ResultInstrs = [FullFP16Pat:result];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
class FuncUnit {
  string NAME = ?;
}
class GCCBuiltin<string GCCBuiltin:name = ?> {
  string GCCBuiltinName = GCCBuiltin:name;
  string NAME = ?;
}
class GIComplexOperandMatcher<LLT GIComplexOperandMatcher:type = ?, string GIComplexOperandMatcher:matcherfn = ?> {
  LLT Type = GIComplexOperandMatcher:type;
  string MatcherFn = GIComplexOperandMatcher:matcherfn;
  string NAME = ?;
}
class GIComplexPatternEquiv<ComplexPattern GIComplexPatternEquiv:seldag = ?> {
  ComplexPattern SelDAGEquivalent = GIComplexPatternEquiv:seldag;
  string NAME = ?;
}
class GICustomOperandRenderer<string GICustomOperandRenderer:rendererfn = ?> {
  string RendererFn = GICustomOperandRenderer:rendererfn;
  string NAME = ?;
}
class GINodeEquiv<Instruction GINodeEquiv:i = ?, SDNode GINodeEquiv:node = ?> {
  Instruction I = GINodeEquiv:i;
  SDNode Node = GINodeEquiv:node;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
class GISDNodeXFormEquiv<SDNodeXForm GISDNodeXFormEquiv:seldag = ?> {
  SDNodeXForm SelDAGEquivalent = GISDNodeXFormEquiv:seldag;
  string NAME = ?;
}
class G_ATOMICRMW_OP {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
class GenericInstruction {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = ?;
  dag InOperandList = ?;
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
class Hexagon_Intrinsic<string Hexagon_Intrinsic:GCCIntSuffix = ?, list<LLVMType> Hexagon_Intrinsic:ret_types = ?, list<LLVMType> Hexagon_Intrinsic:param_types = ?, list<IntrinsicProperty> Hexagon_Intrinsic:properties = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = Hexagon_Intrinsic:ret_types;
  list<LLVMType> ParamTypes = Hexagon_Intrinsic:param_types;
  list<IntrinsicProperty> IntrProperties = Hexagon_Intrinsic:properties;
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_LLiLLiLLi_Intrinsic<string Hexagon_LLiLLiLLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_LLiLLiLLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_LLiLLiLLii_Intrinsic<string Hexagon_LLiLLiLLii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_LLiLLiLLii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_LLiLLii_Intrinsic<string Hexagon_LLiLLii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_LLiLLii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_LLii_Intrinsic<string Hexagon_LLii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_LLii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_NonGCC_Intrinsic<list<LLVMType> Hexagon_NonGCC_Intrinsic:ret_types = ?, list<LLVMType> Hexagon_NonGCC_Intrinsic:param_types = ?, list<IntrinsicProperty> Hexagon_NonGCC_Intrinsic:properties = ?> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = Hexagon_NonGCC_Intrinsic:ret_types;
  list<LLVMType> ParamTypes = Hexagon_NonGCC_Intrinsic:param_types;
  list<IntrinsicProperty> IntrProperties = Hexagon_NonGCC_Intrinsic:properties;
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024i_Intrinsic<string Hexagon_V62_v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v1024i_Intrinsic<string Hexagon_V62_v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v1024v1024_Intrinsic<string Hexagon_V62_v1024v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v1024v1024i_Intrinsic<string Hexagon_V62_v1024v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<string Hexagon_V62_v1024v1024v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v1024v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v1024v128ii_Intrinsic<string Hexagon_V62_v1024v1024v128ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v1024v128ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v1024i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v1024v512v512_Intrinsic<string Hexagon_V62_v1024v1024v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v1024v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v1024v512v512i_Intrinsic<string Hexagon_V62_v1024v1024v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v1024v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v128ii_Intrinsic<string Hexagon_V62_v1024v128ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v128ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v128iv1024_Intrinsic<string Hexagon_V62_v1024v128iv1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v128iv1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v512v512_Intrinsic<string Hexagon_V62_v1024v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v1024v512v512i_Intrinsic<string Hexagon_V62_v1024v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v1024v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v128ii_Intrinsic<string Hexagon_V62_v128ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v128ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v128iv128iv128i_Intrinsic<string Hexagon_V62_v128iv128iv128i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v128iv128iv128i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v2048v1024v1024_Intrinsic<string Hexagon_V62_v2048v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v2048v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v2048v1024v1024i_Intrinsic<string Hexagon_V62_v2048v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v2048v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v2048v2048i_Intrinsic<string Hexagon_V62_v2048v2048i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v2048v2048i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v2048v2048v1024v1024_Intrinsic<string Hexagon_V62_v2048v2048v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v2048v2048v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<string Hexagon_V62_v2048v2048v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v2048v2048v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v2048v2048v2048_Intrinsic<string Hexagon_V62_v2048v2048v2048_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v2048v2048v2048_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v2048v2048v2048i_Intrinsic<string Hexagon_V62_v2048v2048v2048i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v2048v2048v2048i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v512i_Intrinsic<string Hexagon_V62_v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v512v512i_Intrinsic<string Hexagon_V62_v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v512v512v512_Intrinsic<string Hexagon_V62_v512v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v512v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v512v512v512i_Intrinsic<string Hexagon_V62_v512v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v512v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v512v512v512v512i_Intrinsic<string Hexagon_V62_v512v512v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v512v512v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v512v512v64ii_Intrinsic<string Hexagon_V62_v512v512v64ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v512v512v64ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v512i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v512v64ii_Intrinsic<string Hexagon_V62_v512v64ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v512v64ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v512v64iv512_Intrinsic<string Hexagon_V62_v512v64iv512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v512v64iv512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v64ii_Intrinsic<string Hexagon_V62_v64ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v64ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V62_v64iv64iv64i_Intrinsic<string Hexagon_V62_v64iv64iv64i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V62_v64iv64iv64i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_iLLiLLi_Intrinsic<string Hexagon_V65_iLLiLLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_iLLiLLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v1024LLi_Intrinsic<string Hexagon_V65_v1024v1024LLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v1024LLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v1024_Intrinsic<string Hexagon_V65_v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v1024i_Intrinsic<string Hexagon_V65_v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string Hexagon_V65_v1024v1024v1024LLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v1024v1024LLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v1024v1024_Intrinsic<string Hexagon_V65_v1024v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v1024v1024i_Intrinsic<string Hexagon_V65_v1024v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v1024v512LLi_Intrinsic<string Hexagon_V65_v1024v1024v512LLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v1024v512LLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v1024v512i_Intrinsic<string Hexagon_V65_v1024v1024v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v1024v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v128i_Intrinsic<string Hexagon_V65_v1024v128i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v128i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v1024v512LLi_Intrinsic<string Hexagon_V65_v1024v512LLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v1024v512LLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v2048_Intrinsic<string Hexagon_V65_v2048_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v2048_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v2048v1024LLi_Intrinsic<string Hexagon_V65_v2048v1024LLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v2048v1024LLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v2048v2048i_Intrinsic<string Hexagon_V65_v2048v2048i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v2048v2048i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string Hexagon_V65_v2048v2048v1024LLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v2048v2048v1024LLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v2048v2048v1024i_Intrinsic<string Hexagon_V65_v2048v2048v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v2048v2048v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v2048v2048v2048i_Intrinsic<string Hexagon_V65_v2048v2048v2048i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v2048v2048v2048i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v512v512LLi_Intrinsic<string Hexagon_V65_v512v512LLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v512v512LLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v512v512_Intrinsic<string Hexagon_V65_v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v512v512i_Intrinsic<string Hexagon_V65_v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v512v512v512LLi_Intrinsic<string Hexagon_V65_v512v512v512LLi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v512v512v512LLi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v512v512v512_Intrinsic<string Hexagon_V65_v512v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v512v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v512v512v512i_Intrinsic<string Hexagon_V65_v512v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v512v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_v512v64i_Intrinsic<string Hexagon_V65_v512v64i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_v512v64i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_viiv1024v1024_Intrinsic<string Hexagon_V65_viiv1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_viiv1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_viiv1024v512_Intrinsic<string Hexagon_V65_viiv1024v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_viiv1024v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_viiv2048v1024_Intrinsic<string Hexagon_V65_viiv2048v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_viiv2048v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v64i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_viiv512v512_Intrinsic<string Hexagon_V65_viiv512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_viiv512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string Hexagon_V65_vv128iiiv1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vv128iiiv1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string Hexagon_V65_vv128iiiv2048v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vv128iiiv2048v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v64i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string Hexagon_V65_vv64iiiv1024v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vv64iiiv1024v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vv64iiiv512v512_Intrinsic<string Hexagon_V65_vv64iiiv512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vv64iiiv512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vvmemiiv1024_Intrinsic<string Hexagon_V65_vvmemiiv1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vvmemiiv1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vvmemiiv2048_Intrinsic<string Hexagon_V65_vvmemiiv2048_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vvmemiiv2048_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vvmemiiv512_Intrinsic<string Hexagon_V65_vvmemiiv512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vvmemiiv512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string Hexagon_V65_vvmemv128iiiv1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vvmemv128iiiv1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string Hexagon_V65_vvmemv128iiiv2048_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vvmemv128iiiv2048_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string Hexagon_V65_vvmemv64iiiv1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vvmemv64iiiv1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string Hexagon_V65_vvmemv64iiiv512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_V65_vvmemv64iiiv512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_custom_brev_ld_Intrinsic<LLVMType Hexagon_custom_brev_ld_Intrinsic:ElTy = ?> {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [Hexagon_custom_brev_ld_Intrinsic:ElTy, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_df_df_Intrinsic<string Hexagon_df_df_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_df_df_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_df_dfdf_Intrinsic<string Hexagon_df_dfdf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_df_dfdf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_df_dfdfdf_Intrinsic<string Hexagon_df_dfdfdf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_df_dfdfdf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_df_dfdfdfqi_Intrinsic<string Hexagon_df_dfdfdfqi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_df_dfdfdfqi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty, llvm_double_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_df_di_Intrinsic<string Hexagon_df_di_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_df_di_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_df_sf_Intrinsic<string Hexagon_df_sf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_df_sf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_df_si_Intrinsic<string Hexagon_df_si_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_df_si_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_df_Intrinsic<string Hexagon_di_df_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_df_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_di_Intrinsic<string Hexagon_di_di_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_di_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_didi_Intrinsic<string Hexagon_di_didi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_didi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_dididi_Intrinsic<string Hexagon_di_dididi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_dididi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_dididisi_Intrinsic<string Hexagon_di_dididisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_dididisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_didiqi_Intrinsic<string Hexagon_di_didiqi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_didiqi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_didisi_Intrinsic<string Hexagon_di_didisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_didisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_didisisi_Intrinsic<string Hexagon_di_didisisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_didisisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_disi_Intrinsic<string Hexagon_di_disi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_disi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_disisi_Intrinsic<string Hexagon_di_disisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_disisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_qi_Intrinsic<string Hexagon_di_qi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_qi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_qididi_Intrinsic<string Hexagon_di_qididi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_qididi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_qisisi_Intrinsic<string Hexagon_di_qisisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_qisisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_sf_Intrinsic<string Hexagon_di_sf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_sf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_si_Intrinsic<string Hexagon_di_si_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_si_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_sidi_Intrinsic<string Hexagon_di_sidi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_sidi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_sisi_Intrinsic<string Hexagon_di_sisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_sisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_di_sisisi_Intrinsic<string Hexagon_di_sisisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_di_sisisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_hi_si_Intrinsic<string Hexagon_hi_si_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_hi_si_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_iii_Intrinsic<string Hexagon_iii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_iii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_iiii_Intrinsic<string Hexagon_iiii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_iiii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_iv1024i_Intrinsic<string Hexagon_iv1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_iv1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_iv512i_Intrinsic<string Hexagon_iv512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_iv512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_mem_memdisi_Intrinsic<string Hexagon_mem_memdisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_mem_memdisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_mem_memdisisi_Intrinsic<string Hexagon_mem_memdisisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_mem_memdisisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_mem_memmemsi_Intrinsic<string Hexagon_mem_memmemsi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_mem_memmemsi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_mem_memmemsisi_Intrinsic<string Hexagon_mem_memmemsisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_mem_memmemsisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_mem_memsisi_Intrinsic<string Hexagon_mem_memsisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_mem_memsisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_mem_memsisisi_Intrinsic<string Hexagon_mem_memsisisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_mem_memsisisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_didi_Intrinsic<string Hexagon_qi_didi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_didi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_disi_Intrinsic<string Hexagon_qi_disi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_disi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_mem_Intrinsic<string Hexagon_qi_mem_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_mem_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_qi_Intrinsic<string Hexagon_qi_qi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_qi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_qiqi_Intrinsic<string Hexagon_qi_qiqi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_qiqi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_qiqiqi_Intrinsic<string Hexagon_qi_qiqiqi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_qiqiqi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_sfqi_Intrinsic<string Hexagon_qi_sfqi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_sfqi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_si_Intrinsic<string Hexagon_qi_si_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_si_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_sidi_Intrinsic<string Hexagon_qi_sidi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_sidi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_qi_sisi_Intrinsic<string Hexagon_qi_sisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_qi_sisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_sf_df_Intrinsic<string Hexagon_sf_df_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_sf_df_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_sf_di_Intrinsic<string Hexagon_sf_di_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_sf_di_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_sf_sf_Intrinsic<string Hexagon_sf_sf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_sf_sf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_sf_sfsf_Intrinsic<string Hexagon_sf_sfsf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_sf_sfsf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_sf_sfsfsf_Intrinsic<string Hexagon_sf_sfsfsf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_sf_sfsfsf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_sf_sfsfsfqi_Intrinsic<string Hexagon_sf_sfsfsfqi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_sf_sfsfsfqi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_sf_si_Intrinsic<string Hexagon_sf_si_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_sf_si_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_df_Intrinsic<string Hexagon_si_df_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_df_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_dfdf_Intrinsic<string Hexagon_si_dfdf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_dfdf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_dfsi_Intrinsic<string Hexagon_si_dfsi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_dfsi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_di_Intrinsic<string Hexagon_si_di_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_di_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_didi_Intrinsic<string Hexagon_si_didi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_didi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_disi_Intrinsic<string Hexagon_si_disi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_disi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_disisi_Intrinsic<string Hexagon_si_disisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_disisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_qi_Intrinsic<string Hexagon_si_qi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_qi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_qiqi_Intrinsic<string Hexagon_si_qiqi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_qiqi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_qisi_Intrinsic<string Hexagon_si_qisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_qisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_qisisi_Intrinsic<string Hexagon_si_qisisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_qisisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sf_Intrinsic<string Hexagon_si_sf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sfsf_Intrinsic<string Hexagon_si_sfsf_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sfsf_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sfsi_Intrinsic<string Hexagon_si_sfsi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sfsi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_si_Intrinsic<string Hexagon_si_si_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_si_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sidi_Intrinsic<string Hexagon_si_sidi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sidi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sididi_Intrinsic<string Hexagon_si_sididi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sididi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sidisi_Intrinsic<string Hexagon_si_sidisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sidisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sisi_Intrinsic<string Hexagon_si_sisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sisidi_Intrinsic<string Hexagon_si_sisidi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sisidi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sisisi_Intrinsic<string Hexagon_si_sisisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sisisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_si_sisisisi_Intrinsic<string Hexagon_si_sisisisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_si_sisisisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_udi_didi_Intrinsic<string Hexagon_udi_didi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_udi_didi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_udi_sisi_Intrinsic<string Hexagon_udi_sisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_udi_sisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_usi_sisi_Intrinsic<string Hexagon_usi_sisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_usi_sisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024_Intrinsic<string Hexagon_v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024i_Intrinsic<string Hexagon_v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024_Intrinsic<string Hexagon_v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024_Intrinsic_T<string Hexagon_v1024v1024_Intrinsic_T:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024_Intrinsic_T:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024i_Intrinsic<string Hexagon_v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024ii_Intrinsic<string Hexagon_v1024v1024ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v1024_Intrinsic<string Hexagon_v1024v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v1024i_Intrinsic<string Hexagon_v1024v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v1024ii_Intrinsic<string Hexagon_v1024v1024v1024ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v1024ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v1024v1024_Intrinsic<string Hexagon_v1024v1024v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v1024v1024i_Intrinsic<string Hexagon_v1024v1024v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v128ii_Intrinsic<string Hexagon_v1024v1024v128ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v128ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v1024i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v2048i_Intrinsic<string Hexagon_v1024v1024v2048i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v2048i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v512_Intrinsic<string Hexagon_v1024v1024v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v512i_Intrinsic<string Hexagon_v1024v1024v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v512v512_Intrinsic<string Hexagon_v1024v1024v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v1024v512v512i_Intrinsic<string Hexagon_v1024v1024v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v1024v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v128ii_Intrinsic<string Hexagon_v1024v128ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v128ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v128iv1024v1024_Intrinsic<string Hexagon_v1024v128iv1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v128iv1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string Hexagon_v1024v128iv1024v1024v128i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v128iv1024v1024v128i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty, llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v2048_Intrinsic_T<string Hexagon_v1024v2048_Intrinsic_T:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v2048_Intrinsic_T:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v2048i_Intrinsic<string Hexagon_v1024v2048i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v2048i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v512_Intrinsic<string Hexagon_v1024v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v512i_Intrinsic<string Hexagon_v1024v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v512v512_Intrinsic<string Hexagon_v1024v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v512v512i_Intrinsic<string Hexagon_v1024v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v1024v64iv512v512_Intrinsic<string Hexagon_v1024v64iv512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v1024v64iv512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v128ii_Intrinsic<string Hexagon_v128ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v128ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v128iv1024i_Intrinsic<string Hexagon_v128iv1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v128iv1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v128iv1024v1024_Intrinsic<string Hexagon_v128iv1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v128iv1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v128iv128i_Intrinsic<string Hexagon_v128iv128i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v128iv128i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v128iv128iv1024i_Intrinsic<string Hexagon_v128iv128iv1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v128iv128iv1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v128iv128iv1024v1024_Intrinsic<string Hexagon_v128iv128iv1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v128iv128iv1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v128iv128iv128i_Intrinsic<string Hexagon_v128iv128iv128i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v128iv128iv128i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v1024_Intrinsic<string Hexagon_v2048v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v1024i_Intrinsic<string Hexagon_v2048v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v1024v1024_Intrinsic<string Hexagon_v2048v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v1024v1024i_Intrinsic<string Hexagon_v2048v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v128iv1024v1024_Intrinsic<string Hexagon_v2048v128iv1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v128iv1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048_Intrinsic_T<string Hexagon_v2048v2048_Intrinsic_T:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048_Intrinsic_T:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048i_Intrinsic<string Hexagon_v2048v2048i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048ii_Intrinsic<string Hexagon_v2048v2048ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048v1024_Intrinsic<string Hexagon_v2048v2048v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048v1024i_Intrinsic<string Hexagon_v2048v2048v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048v1024v1024_Intrinsic<string Hexagon_v2048v2048v1024v1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048v1024v1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048v1024v1024i_Intrinsic<string Hexagon_v2048v2048v1024v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048v1024v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048v2048_Intrinsic<string Hexagon_v2048v2048v2048_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048v2048_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048v2048i_Intrinsic<string Hexagon_v2048v2048v2048i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048v2048i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v2048v2048v2048ii_Intrinsic<string Hexagon_v2048v2048v2048ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v2048v2048v2048ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v256_v256v256_Intrinsic<string Hexagon_v256_v256v256_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v256_v256v256_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512_Intrinsic<string Hexagon_v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512i_Intrinsic<string Hexagon_v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v1024_Intrinsic_T<string Hexagon_v512v1024_Intrinsic_T:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v1024_Intrinsic_T:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v1024i_Intrinsic<string Hexagon_v512v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v512_Intrinsic<string Hexagon_v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v512i_Intrinsic<string Hexagon_v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v512v1024i_Intrinsic<string Hexagon_v512v512v1024i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v512v1024i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v512v512_Intrinsic<string Hexagon_v512v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v512v512i_Intrinsic<string Hexagon_v512v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v512v512v512_Intrinsic<string Hexagon_v512v512v512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v512v512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v512v512v512i_Intrinsic<string Hexagon_v512v512v512v512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v512v512v512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v512v64ii_Intrinsic<string Hexagon_v512v512v64ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v512v64ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v512i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v64ii_Intrinsic<string Hexagon_v512v64ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v64ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v64iv512v512_Intrinsic<string Hexagon_v512v64iv512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v64iv512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v512v64iv512v512v64i_Intrinsic<string Hexagon_v512v64iv512v512v64i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v512v64iv512v512v64i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty, llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v64ii_Intrinsic<string Hexagon_v64ii_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v64ii_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v64iv512i_Intrinsic<string Hexagon_v64iv512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v64iv512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v64iv512v512_Intrinsic<string Hexagon_v64iv512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v64iv512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v64iv64i_Intrinsic<string Hexagon_v64iv64i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v64iv64i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v64iv64iv512i_Intrinsic<string Hexagon_v64iv64iv512i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v64iv64iv512i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v64iv64iv512v512_Intrinsic<string Hexagon_v64iv64iv512v512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v64iv64iv512v512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_v64iv64iv64i_Intrinsic<string Hexagon_v64iv64iv64i_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_v64iv64iv64i_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_void_sisi_Intrinsic<string Hexagon_void_sisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_void_sisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_void_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_void_sisisi_Intrinsic<string Hexagon_void_sisisi_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_void_sisisi_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_void_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_vv128ivmemv1024_Intrinsic<string Hexagon_vv128ivmemv1024_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_vv128ivmemv1024_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_ptr_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class Hexagon_vv64ivmemv512_Intrinsic<string Hexagon_vv64ivmemv512_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_", Hexagon_vv64ivmemv512_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_ptr_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class HwMode<string HwMode:FS = ?> {
  string Features = HwMode:FS;
  string NAME = ?;
}
class HwModeSelect<list<HwMode> HwModeSelect:Ms = ?> {
  list<HwMode> Modes = HwModeSelect:Ms;
  string NAME = ?;
}
class I<dag I:oops = ?, dag I:iops = ?, AddrMode I:am = ?, int I:sz = ?, IndexMode I:im = ?, Format I:f = ?, InstrItinClass I:itin = ?, string I:opc = ?, string I:asm = ?, string I:cstr = ?, list<dag> I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = I:oops;
  dag InOperandList = !con(I:iops, (ins pred:$p));
  string AsmString = !strconcat(I:opc, !strconcat("${p}", I:asm));
  list<dag> Pattern = I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = I:sz;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(I:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = I:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = I:am;
  IndexMode IM = I:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = I:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class ImmAsmOperand<int ImmAsmOperand:Low = ?, int ImmAsmOperand:High = ?> {	// AsmOperandClass
  string Name = ?;
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = !strconcat("isImmediate<", !strconcat(!cast<string>(ImmAsmOperand:Low), !strconcat(",", !strconcat(!cast<string>(ImmAsmOperand:High), ">"))));
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = !strconcat("operand must be an immediate in the range [", !strconcat(!cast<string>(ImmAsmOperand:Low), !strconcat(",", !strconcat(!cast<string>(ImmAsmOperand:High), "]"))));
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
class ImmAsmOperandMinusOne<int ImmAsmOperandMinusOne:Low = ?, int ImmAsmOperandMinusOne:High = ?> {	// AsmOperandClass
  string Name = ?;
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = !strconcat("isImmediate<", !strconcat(!cast<string>(ImmAsmOperandMinusOne:Low), !strconcat(",", !strconcat(!cast<string>(ImmAsmOperandMinusOne:High), ">"))));
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = !strconcat("ImmRange", !strconcat(!cast<string>(ImmAsmOperandMinusOne:Low), !strconcat("_", !cast<string>(ImmAsmOperandMinusOne:High))));
  string DiagnosticString = !strconcat("operand must be an immediate in the range [", !strconcat(!cast<string>(ImmAsmOperandMinusOne:Low), !strconcat(",", !strconcat(!cast<string>(ImmAsmOperandMinusOne:High), "]"))));
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
class ImmLeaf<ValueType ImmLeaf:vt = ?, code ImmLeaf:pred = ?, SDNodeXForm ImmLeaf:xform = NOOP_SDNodeXForm, SDNode ImmLeaf:ImmNode = imm> {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (ImmLeaf:vt ImmLeaf:ImmNode);
  code PredicateCode = [{}];
  code ImmediateCode = ImmLeaf:pred;
  SDNodeXForm OperandTransform = ImmLeaf:xform;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
class IndexMode<bits<2> IndexMode:val = { ?, ? }> {
  bits<2> Value = { IndexMode:val{1}, IndexMode:val{0} };
  string NAME = ?;
}
class InoP<dag InoP:oops = ?, dag InoP:iops = ?, AddrMode InoP:am = ?, int InoP:sz = ?, IndexMode InoP:im = ?, Format InoP:f = ?, InstrItinClass InoP:itin = ?, string InoP:opc = ?, string InoP:asm = ?, string InoP:cstr = ?, list<dag> InoP:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = InoP:oops;
  dag InOperandList = InoP:iops;
  string AsmString = !strconcat(InoP:opc, InoP:asm);
  list<dag> Pattern = InoP:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = InoP:sz;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(InoP:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = InoP:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = InoP:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = InoP:am;
  IndexMode IM = InoP:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = InoP:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class InstARM<AddrMode InstARM:am = ?, int InstARM:sz = ?, IndexMode InstARM:im = ?, Format InstARM:f = ?, Domain InstARM:d = ?, string InstARM:cstr = ?, InstrItinClass InstARM:itin = ?> {	// Instruction InstTemplate Encoding
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ?;
  dag InOperandList = ?;
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = InstARM:sz;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(InstARM:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = InstARM:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = InstARM:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = InstARM:am;
  IndexMode IM = InstARM:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = InstARM:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = InstARM:d;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class InstAlias<string InstAlias:Asm = ?, dag InstAlias:Result = ?, int InstAlias:Emit = 1, string InstAlias:VariantName = ""> {
  string AsmString = InstAlias:Asm;
  dag ResultInst = InstAlias:Result;
  int EmitPriority = InstAlias:Emit;
  list<Predicate> Predicates = [];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = InstAlias:VariantName;
  string NAME = ?;
}
class InstRW<list<SchedReadWrite> InstRW:rw = ?, dag InstRW:instrlist = ?> {
  list<SchedReadWrite> OperandReadWrites = InstRW:rw;
  dag Instrs = InstRW:instrlist;
  SchedMachineModel SchedModel = ?;
  bit Unsupported = 0;
  string NAME = ?;
}
class InstTemplate<AddrMode InstTemplate:am = ?, int InstTemplate:sz = ?, IndexMode InstTemplate:im = ?, Format InstTemplate:f = ?, Domain InstTemplate:d = ?, string InstTemplate:cstr = ?, InstrItinClass InstTemplate:itin = ?> {	// Instruction
  string Namespace = "ARM";
  dag OutOperandList = ?;
  dag InOperandList = ?;
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = InstTemplate:sz;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(InstTemplate:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = InstTemplate:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = InstTemplate:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = InstTemplate:am;
  IndexMode IM = InstTemplate:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = InstTemplate:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = InstTemplate:d;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class InstThumb<AddrMode InstThumb:am = ?, int InstThumb:sz = ?, IndexMode InstThumb:im = ?, Format InstThumb:f = ?, Domain InstThumb:d = ?, string InstThumb:cstr = ?, InstrItinClass InstThumb:itin = ?> {	// Instruction InstTemplate
  string Namespace = "ARM";
  dag OutOperandList = ?;
  dag InOperandList = ?;
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = InstThumb:sz;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(InstThumb:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = InstThumb:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = InstThumb:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = InstThumb:am;
  IndexMode IM = InstThumb:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = InstThumb:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = InstThumb:d;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class InstrInfo {
  bit isLittleEndianEncoding = 0;
  bit guessInstructionProperties = 1;
  bit decodePositionallyEncodedOperands = 0;
  bit noNamedPositionallyEncodedOperands = 0;
  string NAME = ?;
}
class InstrItinClass {
  string NAME = ?;
}
class InstrItinData<InstrItinClass InstrItinData:Class = ?, list<InstrStage> InstrItinData:stages = ?, list<int> InstrItinData:operandcycles = [], list<Bypass> InstrItinData:bypasses = [], int InstrItinData:uops = 1> {
  InstrItinClass TheClass = InstrItinData:Class;
  int NumMicroOps = InstrItinData:uops;
  list<InstrStage> Stages = InstrItinData:stages;
  list<int> OperandCycles = InstrItinData:operandcycles;
  list<Bypass> Bypasses = InstrItinData:bypasses;
  string NAME = ?;
}
class InstrMapping {
  string FilterClass = ?;
  list<string> RowFields = [];
  list<string> ColFields = [];
  list<string> KeyCol = [];
  list<list<string>> ValueCols = [];
  string NAME = ?;
}
class InstrStage<int InstrStage:cycles = ?, list<FuncUnit> InstrStage:units = ?, int InstrStage:timeinc = -1, ReservationKind InstrStage:kind = Required> {
  int Cycles = InstrStage:cycles;
  list<FuncUnit> Units = InstrStage:units;
  int TimeInc = InstrStage:timeinc;
  int Kind = InstrStage:kind.Value;
  string NAME = ?;
}
class Instruction {
  string Namespace = "";
  dag OutOperandList = ?;
  dag InOperandList = ?;
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
class IntImmLeaf<ValueType IntImmLeaf:vt = ?, code IntImmLeaf:pred = ?, SDNodeXForm IntImmLeaf:xform = NOOP_SDNodeXForm> {	// SDPatternOperator PatFrag ImmLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (IntImmLeaf:vt imm);
  code PredicateCode = [{}];
  code ImmediateCode = IntImmLeaf:pred;
  SDNodeXForm OperandTransform = IntImmLeaf:xform;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 1;
  bit IsAPInt = 1;
  bit IsAPFloat = 0;
  string NAME = ?;
}
class Intrinsic<list<LLVMType> Intrinsic:ret_types = ?, list<LLVMType> Intrinsic:param_types = [], list<IntrinsicProperty> Intrinsic:intr_properties = [], string Intrinsic:name = "", list<SDNodeProperty> Intrinsic:sd_properties = []> {	// SDPatternOperator
  list<SDNodeProperty> Properties = Intrinsic:sd_properties;
  string LLVMName = Intrinsic:name;
  string TargetPrefix = "";
  list<LLVMType> RetTypes = Intrinsic:ret_types;
  list<LLVMType> ParamTypes = Intrinsic:param_types;
  list<IntrinsicProperty> IntrProperties = Intrinsic:intr_properties;
  bit isTarget = 0;
  string NAME = ?;
}
class IntrinsicProperty {
  string NAME = ?;
}
class ItinRW<list<SchedReadWrite> ItinRW:rw = ?, list<InstrItinClass> ItinRW:iic = ?> {
  list<InstrItinClass> MatchedItinClasses = ItinRW:iic;
  list<SchedReadWrite> OperandReadWrites = ItinRW:rw;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class JTI<dag JTI:oops = ?, dag JTI:iops = ?, InstrItinClass JTI:itin = ?, string JTI:asm = ?, list<dag> JTI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM XI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = JTI:oops;
  dag InOperandList = JTI:iops;
  string AsmString = JTI:asm;
  list<dag> Pattern = JTI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = JTI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrMiscFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class LLT {
  string NAME = ?;
}
class LLVMAnyPointerType<LLVMType LLVMAnyPointerType:elty = ?> {	// LLVMType
  ValueType VT = iPTRAny;
  int isAny = 1;
  LLVMType ElTy = LLVMAnyPointerType:elty;
  string NAME = ?;
}
class LLVMExtendedType<int LLVMExtendedType:num = ?> {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = LLVMExtendedType:num;
  string NAME = ?;
}
class LLVMHalfElementsVectorType<int LLVMHalfElementsVectorType:num = ?> {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = LLVMHalfElementsVectorType:num;
  string NAME = ?;
}
class LLVMMatchType<int LLVMMatchType:num = ?> {	// LLVMType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = LLVMMatchType:num;
  string NAME = ?;
}
class LLVMPointerTo<int LLVMPointerTo:num = ?> {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = LLVMPointerTo:num;
  string NAME = ?;
}
class LLVMPointerToElt<int LLVMPointerToElt:num = ?> {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = LLVMPointerToElt:num;
  string NAME = ?;
}
class LLVMPointerType<LLVMType LLVMPointerType:elty = ?> {	// LLVMType LLVMQualPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = LLVMPointerType:elty;
  int AddrSpace = 0;
  string NAME = ?;
}
class LLVMQualPointerType<LLVMType LLVMQualPointerType:elty = ?, int LLVMQualPointerType:addrspace = ?> {	// LLVMType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = LLVMQualPointerType:elty;
  int AddrSpace = LLVMQualPointerType:addrspace;
  string NAME = ?;
}
class LLVMTruncatedType<int LLVMTruncatedType:num = ?> {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = LLVMTruncatedType:num;
  string NAME = ?;
}
class LLVMType<ValueType LLVMType:vt = ?> {
  ValueType VT = LLVMType:vt;
  int isAny = 0;
  string NAME = ?;
}
class LLVMVectorOfAnyPointersToElt<int LLVMVectorOfAnyPointersToElt:num = ?> {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = LLVMVectorOfAnyPointersToElt:num;
  string NAME = ?;
}
class LLVMVectorSameWidth<int LLVMVectorSameWidth:num = ?, LLVMType LLVMVectorSameWidth:elty = ?> {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = LLVMVectorSameWidth:num;
  ValueType ElTy = LLVMVectorSameWidth:elty.VT;
  string NAME = ?;
}
class MClassSysReg<bits<1> MClassSysReg:UniqMask1 = { ? }, bits<1> MClassSysReg:UniqMask2 = { ? }, bits<1> MClassSysReg:UniqMask3 = { ? }, bits<12> MClassSysReg:Enc12 = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? }, string MClassSysReg:name = ?> {	// SearchableTable
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = MClassSysReg:name;
  bits<13> M1Encoding12 = { MClassSysReg:UniqMask1{0}, MClassSysReg:Enc12{11}, MClassSysReg:Enc12{10}, MClassSysReg:Enc12{9}, MClassSysReg:Enc12{8}, MClassSysReg:Enc12{7}, MClassSysReg:Enc12{6}, MClassSysReg:Enc12{5}, MClassSysReg:Enc12{4}, MClassSysReg:Enc12{3}, MClassSysReg:Enc12{2}, MClassSysReg:Enc12{1}, MClassSysReg:Enc12{0} };
  bits<10> M2M3Encoding8 = { MClassSysReg:UniqMask2{0}, MClassSysReg:UniqMask3{0}, MClassSysReg:Enc12{7}, MClassSysReg:Enc12{6}, MClassSysReg:Enc12{5}, MClassSysReg:Enc12{4}, MClassSysReg:Enc12{3}, MClassSysReg:Enc12{2}, MClassSysReg:Enc12{1}, MClassSysReg:Enc12{0} };
  bits<12> Encoding = { MClassSysReg:Enc12{11}, MClassSysReg:Enc12{10}, MClassSysReg:Enc12{9}, MClassSysReg:Enc12{8}, MClassSysReg:Enc12{7}, MClassSysReg:Enc12{6}, MClassSysReg:Enc12{5}, MClassSysReg:Enc12{4}, MClassSysReg:Enc12{3}, MClassSysReg:Enc12{2}, MClassSysReg:Enc12{1}, MClassSysReg:Enc12{0} };
  code Requires = [{ {} }];
  string NAME = ?;
}
class MOVCCShPseudo<SDPatternOperator MOVCCShPseudo:opnode = ?, Operand MOVCCShPseudo:ty = ?> {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMcmov rGPR:$false, (MOVCCShPseudo:opnode rGPR:$Rm, (i32 MOVCCShPseudo:ty:$imm)), cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class MSBuiltin<string MSBuiltin:name = ?> {
  string MSBuiltinName = MSBuiltin:name;
  string NAME = ?;
}
class MemOperand {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
class MnemonicAlias<string MnemonicAlias:From = ?, string MnemonicAlias:To = ?, string MnemonicAlias:VariantName = ""> {
  string FromMnemonic = MnemonicAlias:From;
  string ToMnemonic = MnemonicAlias:To;
  string AsmVariantName = MnemonicAlias:VariantName;
  list<Predicate> Predicates = [];
  string NAME = ?;
}
class MovFromVFP<bits<4> MovFromVFP:opc19_16 = { ?, ?, ?, ? }, dag MovFromVFP:oops = ?, dag MovFromVFP:iops = ?, string MovFromVFP:opc = ?, string MovFromVFP:asm = ?, list<dag> MovFromVFP:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, MovFromVFP:opc19_16{3}, MovFromVFP:opc19_16{2}, MovFromVFP:opc19_16{1}, MovFromVFP:opc19_16{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = MovFromVFP:oops;
  dag InOperandList = !con(MovFromVFP:iops, (ins pred:$p));
  string AsmString = !strconcat(MovFromVFP:opc, !strconcat("${p}", MovFromVFP:asm));
  list<dag> Pattern = MovFromVFP:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPMiscFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
class MovRCopro<string MovRCopro:opc = ?, bit MovRCopro:direction = ?, dag MovRCopro:oops = ?, dag MovRCopro:iops = ?, list<dag> MovRCopro:pattern = ?> {	// Instruction InstTemplate Encoding InstARM I ABI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, MovRCopro:direction, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = MovRCopro:oops;
  dag InOperandList = !con(MovRCopro:iops, (ins pred:$p));
  string AsmString = !strconcat(MovRCopro:opc, "${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2");
  list<dag> Pattern = MovRCopro:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string NAME = ?;
}
class MovRCopro2<string MovRCopro2:opc = ?, bit MovRCopro2:direction = ?, dag MovRCopro2:oops = ?, dag MovRCopro2:iops = ?, list<dag> MovRCopro2:pattern = ?> {	// Instruction InstTemplate Encoding InstARM XI ABXI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, MovRCopro2:direction, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = MovRCopro2:oops;
  dag InOperandList = MovRCopro2:iops;
  string AsmString = !strconcat(MovRCopro2:opc, "	$cop, $opc1, $Rt, $CRn, $CRm, $opc2");
  list<dag> Pattern = MovRCopro2:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string NAME = ?;
}
class MovRRCopro<string MovRRCopro:opc = ?, bit MovRRCopro:direction = ?, dag MovRRCopro:oops = ?, dag MovRRCopro:iops = ?, list<dag> MovRRCopro:pattern = []> {	// Instruction InstTemplate Encoding InstARM I ABI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 0, 1, 0, MovRRCopro:direction, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = MovRRCopro:oops;
  dag InOperandList = !con(MovRRCopro:iops, (ins pred:$p));
  string AsmString = !strconcat(MovRRCopro:opc, "${p}	$cop, $opc1, $Rt, $Rt2, $CRm");
  list<dag> Pattern = MovRRCopro:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
class MovRRCopro2<string MovRRCopro2:opc = ?, bit MovRRCopro2:direction = ?, dag MovRRCopro2:oops = ?, dag MovRRCopro2:iops = ?, list<dag> MovRRCopro2:pattern = []> {	// Instruction InstTemplate Encoding InstARM XI ABXI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, MovRRCopro2:direction, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = MovRRCopro2:oops;
  dag InOperandList = MovRRCopro2:iops;
  string AsmString = !strconcat(MovRRCopro2:opc, "	$cop, $opc1, $Rt, $Rt2, $CRm");
  list<dag> Pattern = MovRRCopro2:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecoderForMRRC2AndMCRR2";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
class MovToVFP<bits<4> MovToVFP:opc19_16 = { ?, ?, ?, ? }, dag MovToVFP:oops = ?, dag MovToVFP:iops = ?, string MovToVFP:opc = ?, string MovToVFP:asm = ?, list<dag> MovToVFP:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 0, MovToVFP:opc19_16{3}, MovToVFP:opc19_16{2}, MovToVFP:opc19_16{1}, MovToVFP:opc19_16{0}, src{3}, src{2}, src{1}, src{0}, 1, 0, 1, 0, 0, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = MovToVFP:oops;
  dag InOperandList = !con(MovToVFP:iops, (ins pred:$p));
  string AsmString = !strconcat(MovToVFP:opc, !strconcat("${p}", MovToVFP:asm));
  list<dag> Pattern = MovToVFP:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPMiscFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> src = { ?, ?, ?, ? };
  string NAME = ?;
}
class N1ModImm<bit N1ModImm:op23 = ?, bits<3> N1ModImm:op21_19 = { ?, ?, ? }, bits<4> N1ModImm:op11_8 = { ?, ?, ?, ? }, bit N1ModImm:op7 = ?, bit N1ModImm:op6 = ?, bit N1ModImm:op5 = ?, bit N1ModImm:op4 = ?, dag N1ModImm:oops = ?, dag N1ModImm:iops = ?, InstrItinClass N1ModImm:itin = ?, string N1ModImm:opc = ?, string N1ModImm:dt = ?, string N1ModImm:asm = ?, string N1ModImm:cstr = ?, list<dag> N1ModImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, N1ModImm:op23, Vd{4}, N1ModImm:op21_19{2}, N1ModImm:op21_19{1}, N1ModImm:op21_19{0}, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N1ModImm:op11_8{3}, N1ModImm:op11_8{2}, N1ModImm:op11_8{1}, N1ModImm:op11_8{0}, N1ModImm:op7, N1ModImm:op6, N1ModImm:op5, N1ModImm:op4, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N1ModImm:oops;
  dag InOperandList = !con(N1ModImm:iops, (ins pred:$p));
  string AsmString = !strconcat(N1ModImm:opc, !strconcat("${p}", !strconcat(".", !strconcat(N1ModImm:dt, !strconcat("	", N1ModImm:asm)))));
  list<dag> Pattern = N1ModImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N1ModImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N1ModImm:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N1RegModImmFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2SHA<string N2SHA:op = ?, bits<2> N2SHA:op17_16 = { ?, ? }, bits<3> N2SHA:op10_8 = { ?, ?, ? }, bit N2SHA:op7 = ?, bit N2SHA:op6 = ?, SDPatternOperator N2SHA:Int = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntXnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, N2SHA:op17_16{1}, N2SHA:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, N2SHA:op10_8{2}, N2SHA:op10_8{1}, N2SHA:op10_8{0}, N2SHA:op7, N2SHA:op6, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = !strconcat(!strconcat("sha", N2SHA:op), ".32	$Vd, $Vm");
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (N2SHA:Int (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2SHA2Op<string N2SHA2Op:op = ?, bits<2> N2SHA2Op:op17_16 = { ?, ? }, bits<3> N2SHA2Op:op10_8 = { ?, ?, ? }, bit N2SHA2Op:op7 = ?, bit N2SHA2Op:op6 = ?, SDPatternOperator N2SHA2Op:Int = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntX2np Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, N2SHA2Op:op17_16{1}, N2SHA2Op:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, N2SHA2Op:op10_8{2}, N2SHA2Op:op10_8{1}, N2SHA2Op:op10_8{0}, N2SHA2Op:op7, N2SHA2Op:op6, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vm);
  string AsmString = !strconcat(!strconcat("sha", N2SHA2Op:op), ".32	$Vd, $Vm");
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (N2SHA2Op:Int (v4i32 QPR:$src), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2V<bits<2> N2V:op24_23 = { ?, ? }, bits<2> N2V:op21_20 = { ?, ? }, bits<2> N2V:op19_18 = { ?, ? }, bits<2> N2V:op17_16 = { ?, ? }, bits<5> N2V:op11_7 = { ?, ?, ?, ?, ? }, bit N2V:op6 = ?, bit N2V:op4 = ?, dag N2V:oops = ?, dag N2V:iops = ?, InstrItinClass N2V:itin = ?, string N2V:opc = ?, string N2V:dt = ?, string N2V:asm = ?, string N2V:cstr = ?, list<dag> N2V:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2V:op24_23{1}, N2V:op24_23{0}, Vd{4}, N2V:op21_20{1}, N2V:op21_20{0}, N2V:op19_18{1}, N2V:op19_18{0}, N2V:op17_16{1}, N2V:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2V:op11_7{4}, N2V:op11_7{3}, N2V:op11_7{2}, N2V:op11_7{1}, N2V:op11_7{0}, N2V:op6, Vm{4}, N2V:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N2V:oops;
  dag InOperandList = !con(N2V:iops, (ins pred:$p));
  string AsmString = !strconcat(N2V:opc, !strconcat("${p}", !strconcat(".", !strconcat(N2V:dt, !strconcat("	", N2V:asm)))));
  list<dag> Pattern = N2V:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2V:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N2V:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VCvtD<bit N2VCvtD:op24 = ?, bit N2VCvtD:op23 = ?, bits<4> N2VCvtD:op11_8 = { ?, ?, ?, ? }, bit N2VCvtD:op7 = ?, bit N2VCvtD:op4 = ?, string N2VCvtD:OpcodeStr = ?, string N2VCvtD:Dt = ?, ValueType N2VCvtD:ResTy = ?, ValueType N2VCvtD:OpTy = ?, SDPatternOperator N2VCvtD:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VCvtD:op24, N2VCvtD:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VCvtD:op11_8{3}, N2VCvtD:op11_8{2}, N2VCvtD:op11_8{1}, N2VCvtD:op11_8{0}, N2VCvtD:op7, 0, Vm{4}, N2VCvtD:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VCvtD:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VCvtD:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VCvtD:ResTy (N2VCvtD:IntOp (N2VCvtD:OpTy DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVCVTFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VCvtQ<bit N2VCvtQ:op24 = ?, bit N2VCvtQ:op23 = ?, bits<4> N2VCvtQ:op11_8 = { ?, ?, ?, ? }, bit N2VCvtQ:op7 = ?, bit N2VCvtQ:op4 = ?, string N2VCvtQ:OpcodeStr = ?, string N2VCvtQ:Dt = ?, ValueType N2VCvtQ:ResTy = ?, ValueType N2VCvtQ:OpTy = ?, SDPatternOperator N2VCvtQ:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VCvtQ:op24, N2VCvtQ:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VCvtQ:op11_8{3}, N2VCvtQ:op11_8{2}, N2VCvtQ:op11_8{1}, N2VCvtQ:op11_8{0}, N2VCvtQ:op7, 1, Vm{4}, N2VCvtQ:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VCvtQ:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VCvtQ:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VCvtQ:ResTy (N2VCvtQ:IntOp (N2VCvtQ:OpTy QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVCVTFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VD<bits<2> N2VD:op24_23 = { ?, ? }, bits<2> N2VD:op21_20 = { ?, ? }, bits<2> N2VD:op19_18 = { ?, ? }, bits<2> N2VD:op17_16 = { ?, ? }, bits<5> N2VD:op11_7 = { ?, ?, ?, ?, ? }, bit N2VD:op4 = ?, string N2VD:OpcodeStr = ?, string N2VD:Dt = ?, ValueType N2VD:ResTy = ?, ValueType N2VD:OpTy = ?, SDNode N2VD:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VD:op24_23{1}, N2VD:op24_23{0}, Vd{4}, N2VD:op21_20{1}, N2VD:op21_20{0}, N2VD:op19_18{1}, N2VD:op19_18{0}, N2VD:op17_16{1}, N2VD:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VD:op11_7{4}, N2VD:op11_7{3}, N2VD:op11_7{2}, N2VD:op11_7{1}, N2VD:op11_7{0}, 0, Vm{4}, N2VD:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VD:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VD:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VD:ResTy (N2VD:OpNode (N2VD:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VDInt<bits<2> N2VDInt:op24_23 = { ?, ? }, bits<2> N2VDInt:op21_20 = { ?, ? }, bits<2> N2VDInt:op19_18 = { ?, ? }, bits<2> N2VDInt:op17_16 = { ?, ? }, bits<5> N2VDInt:op11_7 = { ?, ?, ?, ?, ? }, bit N2VDInt:op4 = ?, InstrItinClass N2VDInt:itin = ?, string N2VDInt:OpcodeStr = ?, string N2VDInt:Dt = ?, ValueType N2VDInt:ResTy = ?, ValueType N2VDInt:OpTy = ?, SDPatternOperator N2VDInt:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VDInt:op24_23{1}, N2VDInt:op24_23{0}, Vd{4}, N2VDInt:op21_20{1}, N2VDInt:op21_20{0}, N2VDInt:op19_18{1}, N2VDInt:op19_18{0}, N2VDInt:op17_16{1}, N2VDInt:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VDInt:op11_7{4}, N2VDInt:op11_7{3}, N2VDInt:op11_7{2}, N2VDInt:op11_7{1}, N2VDInt:op11_7{0}, 0, Vm{4}, N2VDInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VDInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VDInt:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VDInt:ResTy (N2VDInt:IntOp (N2VDInt:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VDInt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VDIntnp<bits<2> N2VDIntnp:op19_18 = { ?, ? }, bits<2> N2VDIntnp:op17_16 = { ?, ? }, bits<3> N2VDIntnp:op10_8 = { ?, ?, ? }, bit N2VDIntnp:op7 = ?, InstrItinClass N2VDIntnp:itin = ?, string N2VDIntnp:OpcodeStr = ?, string N2VDIntnp:Dt = ?, ValueType N2VDIntnp:ResTy = ?, ValueType N2VDIntnp:OpTy = ?, SDPatternOperator N2VDIntnp:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, N2VDIntnp:op19_18{1}, N2VDIntnp:op19_18{0}, N2VDIntnp:op17_16{1}, N2VDIntnp:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, N2VDIntnp:op10_8{2}, N2VDIntnp:op10_8{1}, N2VDIntnp:op10_8{0}, N2VDIntnp:op7, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = !strconcat(N2VDIntnp:OpcodeStr, !strconcat(".", !strconcat(N2VDIntnp:Dt, "	$Vd, $Vm")));
  list<dag> Pattern = [(set DPR:$Vd, (N2VDIntnp:ResTy (N2VDIntnp:IntOp (N2VDIntnp:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VDIntnp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VDPLInt<bits<2> N2VDPLInt:op24_23 = { ?, ? }, bits<2> N2VDPLInt:op21_20 = { ?, ? }, bits<2> N2VDPLInt:op19_18 = { ?, ? }, bits<2> N2VDPLInt:op17_16 = { ?, ? }, bits<5> N2VDPLInt:op11_7 = { ?, ?, ?, ?, ? }, bit N2VDPLInt:op4 = ?, string N2VDPLInt:OpcodeStr = ?, string N2VDPLInt:Dt = ?, ValueType N2VDPLInt:ResTy = ?, ValueType N2VDPLInt:OpTy = ?, SDPatternOperator N2VDPLInt:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VDPLInt:op24_23{1}, N2VDPLInt:op24_23{0}, Vd{4}, N2VDPLInt:op21_20{1}, N2VDPLInt:op21_20{0}, N2VDPLInt:op19_18{1}, N2VDPLInt:op19_18{0}, N2VDPLInt:op17_16{1}, N2VDPLInt:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VDPLInt:op11_7{4}, N2VDPLInt:op11_7{3}, N2VDPLInt:op11_7{2}, N2VDPLInt:op11_7{1}, N2VDPLInt:op11_7{0}, 0, Vm{4}, N2VDPLInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VDPLInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VDPLInt:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VDPLInt:ResTy (N2VDPLInt:IntOp (N2VDPLInt:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VDPLInt2<bits<2> N2VDPLInt2:op24_23 = { ?, ? }, bits<2> N2VDPLInt2:op21_20 = { ?, ? }, bits<2> N2VDPLInt2:op19_18 = { ?, ? }, bits<2> N2VDPLInt2:op17_16 = { ?, ? }, bits<5> N2VDPLInt2:op11_7 = { ?, ?, ?, ?, ? }, bit N2VDPLInt2:op4 = ?, string N2VDPLInt2:OpcodeStr = ?, string N2VDPLInt2:Dt = ?, ValueType N2VDPLInt2:ResTy = ?, ValueType N2VDPLInt2:OpTy = ?, SDPatternOperator N2VDPLInt2:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VDPLInt2:op24_23{1}, N2VDPLInt2:op24_23{0}, Vd{4}, N2VDPLInt2:op21_20{1}, N2VDPLInt2:op21_20{0}, N2VDPLInt2:op19_18{1}, N2VDPLInt2:op19_18{0}, N2VDPLInt2:op17_16{1}, N2VDPLInt2:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VDPLInt2:op11_7{4}, N2VDPLInt2:op11_7{3}, N2VDPLInt2:op11_7{2}, N2VDPLInt2:op11_7{1}, N2VDPLInt2:op11_7{0}, 0, Vm{4}, N2VDPLInt2:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VDPLInt2:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VDPLInt2:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VDPLInt2:ResTy (N2VDPLInt2:IntOp (N2VDPLInt2:ResTy DPR:$src1), (N2VDPLInt2:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VDSh<bit N2VDSh:op24 = ?, bit N2VDSh:op23 = ?, bits<4> N2VDSh:op11_8 = { ?, ?, ?, ? }, bit N2VDSh:op7 = ?, bit N2VDSh:op4 = ?, Format N2VDSh:f = ?, InstrItinClass N2VDSh:itin = ?, Operand N2VDSh:ImmTy = ?, string N2VDSh:OpcodeStr = ?, string N2VDSh:Dt = ?, ValueType N2VDSh:Ty = ?, SDNode N2VDSh:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VDSh:op24, N2VDSh:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VDSh:op11_8{3}, N2VDSh:op11_8{2}, N2VDSh:op11_8{1}, N2VDSh:op11_8{0}, N2VDSh:op7, 0, Vm{4}, N2VDSh:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, N2VDSh:ImmTy:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VDSh:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VDSh:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VDSh:Ty (N2VDSh:OpNode (N2VDSh:Ty DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N2VDSh:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VDSh:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2VDSh:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VDShAdd<bit N2VDShAdd:op24 = ?, bit N2VDShAdd:op23 = ?, bits<4> N2VDShAdd:op11_8 = { ?, ?, ?, ? }, bit N2VDShAdd:op7 = ?, bit N2VDShAdd:op4 = ?, Operand N2VDShAdd:ImmTy = ?, string N2VDShAdd:OpcodeStr = ?, string N2VDShAdd:Dt = ?, ValueType N2VDShAdd:Ty = ?, SDNode N2VDShAdd:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VDShAdd:op24, N2VDShAdd:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VDShAdd:op11_8{3}, N2VDShAdd:op11_8{2}, N2VDShAdd:op11_8{1}, N2VDShAdd:op11_8{0}, N2VDShAdd:op7, 0, Vm{4}, N2VDShAdd:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, N2VDShAdd:ImmTy:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VDShAdd:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VDShAdd:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VDShAdd:Ty (add DPR:$src1, (N2VDShAdd:Ty (N2VDShAdd:ShOp DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegVShRFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VDShIns<bit N2VDShIns:op24 = ?, bit N2VDShIns:op23 = ?, bits<4> N2VDShIns:op11_8 = { ?, ?, ?, ? }, bit N2VDShIns:op7 = ?, bit N2VDShIns:op4 = ?, Operand N2VDShIns:ImmTy = ?, Format N2VDShIns:f = ?, string N2VDShIns:OpcodeStr = ?, string N2VDShIns:Dt = ?, ValueType N2VDShIns:Ty = ?, SDNode N2VDShIns:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VDShIns:op24, N2VDShIns:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VDShIns:op11_8{3}, N2VDShIns:op11_8{2}, N2VDShIns:op11_8{1}, N2VDShIns:op11_8{0}, N2VDShIns:op7, 0, Vm{4}, N2VDShIns:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, N2VDShIns:ImmTy:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VDShIns:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VDShIns:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VDShIns:Ty (N2VDShIns:ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N2VDShIns:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2VDShIns:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VDShuffle<bits<2> N2VDShuffle:op19_18 = { ?, ? }, bits<5> N2VDShuffle:op11_7 = { ?, ?, ?, ?, ? }, string N2VDShuffle:OpcodeStr = ?, string N2VDShuffle:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, N2VDShuffle:op19_18{1}, N2VDShuffle:op19_18{0}, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VDShuffle:op11_7{4}, N2VDShuffle:op11_7{3}, N2VDShuffle:op11_7{2}, N2VDShuffle:op11_7{1}, N2VDShuffle:op11_7{0}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$Vm);
  dag InOperandList = (ins DPR:$src1, DPR:$src2, pred:$p);
  string AsmString = !strconcat(N2VDShuffle:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VDShuffle:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VImm<bit N2VImm:op24 = ?, bit N2VImm:op23 = ?, bits<4> N2VImm:op11_8 = { ?, ?, ?, ? }, bit N2VImm:op7 = ?, bit N2VImm:op6 = ?, bit N2VImm:op4 = ?, dag N2VImm:oops = ?, dag N2VImm:iops = ?, Format N2VImm:f = ?, InstrItinClass N2VImm:itin = ?, string N2VImm:opc = ?, string N2VImm:dt = ?, string N2VImm:asm = ?, string N2VImm:cstr = ?, list<dag> N2VImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VImm:op24, N2VImm:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VImm:op11_8{3}, N2VImm:op11_8{2}, N2VImm:op11_8{1}, N2VImm:op11_8{0}, N2VImm:op7, N2VImm:op6, Vm{4}, N2VImm:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N2VImm:oops;
  dag InOperandList = !con(N2VImm:iops, (ins pred:$p));
  string AsmString = !strconcat(N2VImm:opc, !strconcat("${p}", !strconcat(".", !strconcat(N2VImm:dt, !strconcat("	", N2VImm:asm)))));
  list<dag> Pattern = N2VImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N2VImm:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N2VImm:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2VImm:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VL<bits<2> N2VL:op24_23 = { ?, ? }, bits<2> N2VL:op21_20 = { ?, ? }, bits<2> N2VL:op19_18 = { ?, ? }, bits<2> N2VL:op17_16 = { ?, ? }, bits<5> N2VL:op11_7 = { ?, ?, ?, ?, ? }, bit N2VL:op6 = ?, bit N2VL:op4 = ?, InstrItinClass N2VL:itin = ?, string N2VL:OpcodeStr = ?, string N2VL:Dt = ?, ValueType N2VL:TyQ = ?, ValueType N2VL:TyD = ?, SDNode N2VL:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VL:op24_23{1}, N2VL:op24_23{0}, Vd{4}, N2VL:op21_20{1}, N2VL:op21_20{0}, N2VL:op19_18{1}, N2VL:op19_18{0}, N2VL:op17_16{1}, N2VL:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VL:op11_7{4}, N2VL:op11_7{3}, N2VL:op11_7{2}, N2VL:op11_7{1}, N2VL:op11_7{0}, N2VL:op6, Vm{4}, N2VL:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VL:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VL:TyQ (N2VL:OpNode (N2VL:TyD DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VLInt<bits<2> N2VLInt:op24_23 = { ?, ? }, bits<2> N2VLInt:op21_20 = { ?, ? }, bits<2> N2VLInt:op19_18 = { ?, ? }, bits<2> N2VLInt:op17_16 = { ?, ? }, bits<5> N2VLInt:op11_7 = { ?, ?, ?, ?, ? }, bit N2VLInt:op6 = ?, bit N2VLInt:op4 = ?, InstrItinClass N2VLInt:itin = ?, string N2VLInt:OpcodeStr = ?, string N2VLInt:Dt = ?, ValueType N2VLInt:TyQ = ?, ValueType N2VLInt:TyD = ?, SDPatternOperator N2VLInt:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VLInt:op24_23{1}, N2VLInt:op24_23{0}, Vd{4}, N2VLInt:op21_20{1}, N2VLInt:op21_20{0}, N2VLInt:op19_18{1}, N2VLInt:op19_18{0}, N2VLInt:op17_16{1}, N2VLInt:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VLInt:op11_7{4}, N2VLInt:op11_7{3}, N2VLInt:op11_7{2}, N2VLInt:op11_7{1}, N2VLInt:op11_7{0}, N2VLInt:op6, Vm{4}, N2VLInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VLInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VLInt:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VLInt:TyQ (N2VLInt:IntOp (N2VLInt:TyD DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VLInt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VLSh<bit N2VLSh:op24 = ?, bit N2VLSh:op23 = ?, bits<4> N2VLSh:op11_8 = { ?, ?, ?, ? }, bit N2VLSh:op7 = ?, bit N2VLSh:op6 = ?, bit N2VLSh:op4 = ?, string N2VLSh:OpcodeStr = ?, string N2VLSh:Dt = ?, ValueType N2VLSh:ResTy = ?, ValueType N2VLSh:OpTy = ?, Operand N2VLSh:ImmTy = ?, SDPatternOperator N2VLSh:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VLSh:op24, N2VLSh:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VLSh:op11_8{3}, N2VLSh:op11_8{2}, N2VLSh:op11_8{1}, N2VLSh:op11_8{0}, N2VLSh:op7, N2VLSh:op6, Vm{4}, N2VLSh:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, N2VLSh:ImmTy:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VLSh:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VLSh:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VLSh:ResTy (N2VLSh:OpNode (N2VLSh:OpTy DPR:$Vm), N2VLSh:ImmTy:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegVShLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VLShMax<bit N2VLShMax:op24 = ?, bit N2VLShMax:op23 = ?, bits<6> N2VLShMax:op21_16 = { ?, ?, ?, ?, ?, ? }, bits<4> N2VLShMax:op11_8 = { ?, ?, ?, ? }, bit N2VLShMax:op7 = ?, bit N2VLShMax:op6 = ?, bit N2VLShMax:op4 = ?, string N2VLShMax:OpcodeStr = ?, string N2VLShMax:Dt = ?, ValueType N2VLShMax:ResTy = ?, ValueType N2VLShMax:OpTy = ?, Operand N2VLShMax:ImmTy = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VLShMax:op24, N2VLShMax:op23, Vd{4}, N2VLShMax:op21_16{5}, N2VLShMax:op21_16{4}, N2VLShMax:op21_16{3}, N2VLShMax:op21_16{2}, N2VLShMax:op21_16{1}, N2VLShMax:op21_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VLShMax:op11_8{3}, N2VLShMax:op11_8{2}, N2VLShMax:op11_8{1}, N2VLShMax:op11_8{0}, N2VLShMax:op7, N2VLShMax:op6, Vm{4}, N2VLShMax:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, N2VLShMax:ImmTy:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VLShMax:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VLShMax:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VLShMax:ResTy (null_frag (N2VLShMax:OpTy DPR:$Vm), N2VLShMax:ImmTy:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVSHLMaxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegVShLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VN<bits<2> N2VN:op24_23 = { ?, ? }, bits<2> N2VN:op21_20 = { ?, ? }, bits<2> N2VN:op19_18 = { ?, ? }, bits<2> N2VN:op17_16 = { ?, ? }, bits<5> N2VN:op11_7 = { ?, ?, ?, ?, ? }, bit N2VN:op6 = ?, bit N2VN:op4 = ?, InstrItinClass N2VN:itin = ?, string N2VN:OpcodeStr = ?, string N2VN:Dt = ?, ValueType N2VN:TyD = ?, ValueType N2VN:TyQ = ?, SDNode N2VN:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VN:op24_23{1}, N2VN:op24_23{0}, Vd{4}, N2VN:op21_20{1}, N2VN:op21_20{0}, N2VN:op19_18{1}, N2VN:op19_18{0}, N2VN:op17_16{1}, N2VN:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VN:op11_7{4}, N2VN:op11_7{3}, N2VN:op11_7{2}, N2VN:op11_7{1}, N2VN:op11_7{0}, N2VN:op6, Vm{4}, N2VN:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VN:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VN:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VN:TyD (N2VN:OpNode (N2VN:TyQ QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VN:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VNInt<bits<2> N2VNInt:op24_23 = { ?, ? }, bits<2> N2VNInt:op21_20 = { ?, ? }, bits<2> N2VNInt:op19_18 = { ?, ? }, bits<2> N2VNInt:op17_16 = { ?, ? }, bits<5> N2VNInt:op11_7 = { ?, ?, ?, ?, ? }, bit N2VNInt:op6 = ?, bit N2VNInt:op4 = ?, InstrItinClass N2VNInt:itin = ?, string N2VNInt:OpcodeStr = ?, string N2VNInt:Dt = ?, ValueType N2VNInt:TyD = ?, ValueType N2VNInt:TyQ = ?, SDPatternOperator N2VNInt:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VNInt:op24_23{1}, N2VNInt:op24_23{0}, Vd{4}, N2VNInt:op21_20{1}, N2VNInt:op21_20{0}, N2VNInt:op19_18{1}, N2VNInt:op19_18{0}, N2VNInt:op17_16{1}, N2VNInt:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VNInt:op11_7{4}, N2VNInt:op11_7{3}, N2VNInt:op11_7{2}, N2VNInt:op11_7{1}, N2VNInt:op11_7{0}, N2VNInt:op6, Vm{4}, N2VNInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VNInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VNInt:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VNInt:TyD (N2VNInt:IntOp (N2VNInt:TyQ QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VNInt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VNSh<bit N2VNSh:op24 = ?, bit N2VNSh:op23 = ?, bits<4> N2VNSh:op11_8 = { ?, ?, ?, ? }, bit N2VNSh:op7 = ?, bit N2VNSh:op6 = ?, bit N2VNSh:op4 = ?, InstrItinClass N2VNSh:itin = ?, string N2VNSh:OpcodeStr = ?, string N2VNSh:Dt = ?, ValueType N2VNSh:ResTy = ?, ValueType N2VNSh:OpTy = ?, Operand N2VNSh:ImmTy = ?, SDPatternOperator N2VNSh:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VNSh:op24, N2VNSh:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VNSh:op11_8{3}, N2VNSh:op11_8{2}, N2VNSh:op11_8{1}, N2VNSh:op11_8{0}, N2VNSh:op7, N2VNSh:op6, Vm{4}, N2VNSh:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, N2VNSh:ImmTy:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VNSh:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VNSh:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set DPR:$Vd, (N2VNSh:ResTy (N2VNSh:OpNode (N2VNSh:OpTy QPR:$Vm), (i32 N2VNSh:ImmTy:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VNSh:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegVShRFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQ<bits<2> N2VQ:op24_23 = { ?, ? }, bits<2> N2VQ:op21_20 = { ?, ? }, bits<2> N2VQ:op19_18 = { ?, ? }, bits<2> N2VQ:op17_16 = { ?, ? }, bits<5> N2VQ:op11_7 = { ?, ?, ?, ?, ? }, bit N2VQ:op4 = ?, string N2VQ:OpcodeStr = ?, string N2VQ:Dt = ?, ValueType N2VQ:ResTy = ?, ValueType N2VQ:OpTy = ?, SDNode N2VQ:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VQ:op24_23{1}, N2VQ:op24_23{0}, Vd{4}, N2VQ:op21_20{1}, N2VQ:op21_20{0}, N2VQ:op19_18{1}, N2VQ:op19_18{0}, N2VQ:op17_16{1}, N2VQ:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VQ:op11_7{4}, N2VQ:op11_7{3}, N2VQ:op11_7{2}, N2VQ:op11_7{1}, N2VQ:op11_7{0}, 1, Vm{4}, N2VQ:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VQ:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VQ:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQ:ResTy (N2VQ:OpNode (N2VQ:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQInt<bits<2> N2VQInt:op24_23 = { ?, ? }, bits<2> N2VQInt:op21_20 = { ?, ? }, bits<2> N2VQInt:op19_18 = { ?, ? }, bits<2> N2VQInt:op17_16 = { ?, ? }, bits<5> N2VQInt:op11_7 = { ?, ?, ?, ?, ? }, bit N2VQInt:op4 = ?, InstrItinClass N2VQInt:itin = ?, string N2VQInt:OpcodeStr = ?, string N2VQInt:Dt = ?, ValueType N2VQInt:ResTy = ?, ValueType N2VQInt:OpTy = ?, SDPatternOperator N2VQInt:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VQInt:op24_23{1}, N2VQInt:op24_23{0}, Vd{4}, N2VQInt:op21_20{1}, N2VQInt:op21_20{0}, N2VQInt:op19_18{1}, N2VQInt:op19_18{0}, N2VQInt:op17_16{1}, N2VQInt:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VQInt:op11_7{4}, N2VQInt:op11_7{3}, N2VQInt:op11_7{2}, N2VQInt:op11_7{1}, N2VQInt:op11_7{0}, 1, Vm{4}, N2VQInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VQInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VQInt:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQInt:ResTy (N2VQInt:IntOp (N2VQInt:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VQInt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQIntX2np<bits<2> N2VQIntX2np:op19_18 = { ?, ? }, bits<2> N2VQIntX2np:op17_16 = { ?, ? }, bits<3> N2VQIntX2np:op10_8 = { ?, ?, ? }, bit N2VQIntX2np:op6 = ?, bit N2VQIntX2np:op7 = ?, InstrItinClass N2VQIntX2np:itin = ?, string N2VQIntX2np:OpcodeStr = ?, string N2VQIntX2np:Dt = ?, ValueType N2VQIntX2np:ResTy = ?, ValueType N2VQIntX2np:OpTy = ?, SDPatternOperator N2VQIntX2np:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, N2VQIntX2np:op19_18{1}, N2VQIntX2np:op19_18{0}, N2VQIntX2np:op17_16{1}, N2VQIntX2np:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, N2VQIntX2np:op10_8{2}, N2VQIntX2np:op10_8{1}, N2VQIntX2np:op10_8{0}, N2VQIntX2np:op7, N2VQIntX2np:op6, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vm);
  string AsmString = !strconcat(N2VQIntX2np:OpcodeStr, !strconcat(".", !strconcat(N2VQIntX2np:Dt, "	$Vd, $Vm")));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQIntX2np:ResTy (N2VQIntX2np:IntOp (N2VQIntX2np:OpTy QPR:$src), (N2VQIntX2np:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VQIntX2np:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQIntXnp<bits<2> N2VQIntXnp:op19_18 = { ?, ? }, bits<2> N2VQIntXnp:op17_16 = { ?, ? }, bits<3> N2VQIntXnp:op10_8 = { ?, ?, ? }, bit N2VQIntXnp:op6 = ?, bit N2VQIntXnp:op7 = ?, InstrItinClass N2VQIntXnp:itin = ?, string N2VQIntXnp:OpcodeStr = ?, string N2VQIntXnp:Dt = ?, ValueType N2VQIntXnp:ResTy = ?, ValueType N2VQIntXnp:OpTy = ?, SDPatternOperator N2VQIntXnp:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, N2VQIntXnp:op19_18{1}, N2VQIntXnp:op19_18{0}, N2VQIntXnp:op17_16{1}, N2VQIntXnp:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, N2VQIntXnp:op10_8{2}, N2VQIntXnp:op10_8{1}, N2VQIntXnp:op10_8{0}, N2VQIntXnp:op7, N2VQIntXnp:op6, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = !strconcat(N2VQIntXnp:OpcodeStr, !strconcat(".", !strconcat(N2VQIntXnp:Dt, "	$Vd, $Vm")));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQIntXnp:ResTy (N2VQIntXnp:IntOp (N2VQIntXnp:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VQIntXnp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQIntnp<bits<2> N2VQIntnp:op19_18 = { ?, ? }, bits<2> N2VQIntnp:op17_16 = { ?, ? }, bits<3> N2VQIntnp:op10_8 = { ?, ?, ? }, bit N2VQIntnp:op7 = ?, InstrItinClass N2VQIntnp:itin = ?, string N2VQIntnp:OpcodeStr = ?, string N2VQIntnp:Dt = ?, ValueType N2VQIntnp:ResTy = ?, ValueType N2VQIntnp:OpTy = ?, SDPatternOperator N2VQIntnp:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, N2VQIntnp:op19_18{1}, N2VQIntnp:op19_18{0}, N2VQIntnp:op17_16{1}, N2VQIntnp:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, N2VQIntnp:op10_8{2}, N2VQIntnp:op10_8{1}, N2VQIntnp:op10_8{0}, N2VQIntnp:op7, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = !strconcat(N2VQIntnp:OpcodeStr, !strconcat(".", !strconcat(N2VQIntnp:Dt, "	$Vd, $Vm")));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQIntnp:ResTy (N2VQIntnp:IntOp (N2VQIntnp:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VQIntnp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQPLInt<bits<2> N2VQPLInt:op24_23 = { ?, ? }, bits<2> N2VQPLInt:op21_20 = { ?, ? }, bits<2> N2VQPLInt:op19_18 = { ?, ? }, bits<2> N2VQPLInt:op17_16 = { ?, ? }, bits<5> N2VQPLInt:op11_7 = { ?, ?, ?, ?, ? }, bit N2VQPLInt:op4 = ?, string N2VQPLInt:OpcodeStr = ?, string N2VQPLInt:Dt = ?, ValueType N2VQPLInt:ResTy = ?, ValueType N2VQPLInt:OpTy = ?, SDPatternOperator N2VQPLInt:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VQPLInt:op24_23{1}, N2VQPLInt:op24_23{0}, Vd{4}, N2VQPLInt:op21_20{1}, N2VQPLInt:op21_20{0}, N2VQPLInt:op19_18{1}, N2VQPLInt:op19_18{0}, N2VQPLInt:op17_16{1}, N2VQPLInt:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VQPLInt:op11_7{4}, N2VQPLInt:op11_7{3}, N2VQPLInt:op11_7{2}, N2VQPLInt:op11_7{1}, N2VQPLInt:op11_7{0}, 1, Vm{4}, N2VQPLInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VQPLInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VQPLInt:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQPLInt:ResTy (N2VQPLInt:IntOp (N2VQPLInt:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQPLInt2<bits<2> N2VQPLInt2:op24_23 = { ?, ? }, bits<2> N2VQPLInt2:op21_20 = { ?, ? }, bits<2> N2VQPLInt2:op19_18 = { ?, ? }, bits<2> N2VQPLInt2:op17_16 = { ?, ? }, bits<5> N2VQPLInt2:op11_7 = { ?, ?, ?, ?, ? }, bit N2VQPLInt2:op4 = ?, string N2VQPLInt2:OpcodeStr = ?, string N2VQPLInt2:Dt = ?, ValueType N2VQPLInt2:ResTy = ?, ValueType N2VQPLInt2:OpTy = ?, SDPatternOperator N2VQPLInt2:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VQPLInt2:op24_23{1}, N2VQPLInt2:op24_23{0}, Vd{4}, N2VQPLInt2:op21_20{1}, N2VQPLInt2:op21_20{0}, N2VQPLInt2:op19_18{1}, N2VQPLInt2:op19_18{0}, N2VQPLInt2:op17_16{1}, N2VQPLInt2:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VQPLInt2:op11_7{4}, N2VQPLInt2:op11_7{3}, N2VQPLInt2:op11_7{2}, N2VQPLInt2:op11_7{1}, N2VQPLInt2:op11_7{0}, 1, Vm{4}, N2VQPLInt2:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N2VQPLInt2:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VQPLInt2:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQPLInt2:ResTy (N2VQPLInt2:IntOp (N2VQPLInt2:ResTy QPR:$src1), (N2VQPLInt2:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQSh<bit N2VQSh:op24 = ?, bit N2VQSh:op23 = ?, bits<4> N2VQSh:op11_8 = { ?, ?, ?, ? }, bit N2VQSh:op7 = ?, bit N2VQSh:op4 = ?, Format N2VQSh:f = ?, InstrItinClass N2VQSh:itin = ?, Operand N2VQSh:ImmTy = ?, string N2VQSh:OpcodeStr = ?, string N2VQSh:Dt = ?, ValueType N2VQSh:Ty = ?, SDNode N2VQSh:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VQSh:op24, N2VQSh:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VQSh:op11_8{3}, N2VQSh:op11_8{2}, N2VQSh:op11_8{1}, N2VQSh:op11_8{0}, N2VQSh:op7, 1, Vm{4}, N2VQSh:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, N2VQSh:ImmTy:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VQSh:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VQSh:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQSh:Ty (N2VQSh:OpNode (N2VQSh:Ty QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N2VQSh:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VQSh:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2VQSh:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQShAdd<bit N2VQShAdd:op24 = ?, bit N2VQShAdd:op23 = ?, bits<4> N2VQShAdd:op11_8 = { ?, ?, ?, ? }, bit N2VQShAdd:op7 = ?, bit N2VQShAdd:op4 = ?, Operand N2VQShAdd:ImmTy = ?, string N2VQShAdd:OpcodeStr = ?, string N2VQShAdd:Dt = ?, ValueType N2VQShAdd:Ty = ?, SDNode N2VQShAdd:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VQShAdd:op24, N2VQShAdd:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VQShAdd:op11_8{3}, N2VQShAdd:op11_8{2}, N2VQShAdd:op11_8{1}, N2VQShAdd:op11_8{0}, N2VQShAdd:op7, 1, Vm{4}, N2VQShAdd:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, N2VQShAdd:ImmTy:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VQShAdd:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VQShAdd:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQShAdd:Ty (add QPR:$src1, (N2VQShAdd:Ty (N2VQShAdd:ShOp QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegVShRFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQShIns<bit N2VQShIns:op24 = ?, bit N2VQShIns:op23 = ?, bits<4> N2VQShIns:op11_8 = { ?, ?, ?, ? }, bit N2VQShIns:op7 = ?, bit N2VQShIns:op4 = ?, Operand N2VQShIns:ImmTy = ?, Format N2VQShIns:f = ?, string N2VQShIns:OpcodeStr = ?, string N2VQShIns:Dt = ?, ValueType N2VQShIns:Ty = ?, SDNode N2VQShIns:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VQShIns:op24, N2VQShIns:op23, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VQShIns:op11_8{3}, N2VQShIns:op11_8{2}, N2VQShIns:op11_8{1}, N2VQShIns:op11_8{0}, N2VQShIns:op7, 1, Vm{4}, N2VQShIns:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, N2VQShIns:ImmTy:$SIMM, pred:$p);
  string AsmString = !strconcat(N2VQShIns:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VQShIns:Dt, "	$Vd, $Vm, $SIMM"))));
  list<dag> Pattern = [(set QPR:$Vd, (N2VQShIns:Ty (N2VQShIns:ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N2VQShIns:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2VQShIns:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VQShuffle<bits<2> N2VQShuffle:op19_18 = { ?, ? }, bits<5> N2VQShuffle:op11_7 = { ?, ?, ?, ?, ? }, InstrItinClass N2VQShuffle:itin = ?, string N2VQShuffle:OpcodeStr = ?, string N2VQShuffle:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, N2VQShuffle:op19_18{1}, N2VQShuffle:op19_18{0}, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VQShuffle:op11_7{4}, N2VQShuffle:op11_7{3}, N2VQShuffle:op11_7{2}, N2VQShuffle:op11_7{1}, N2VQShuffle:op11_7{0}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = !strconcat(N2VQShuffle:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N2VQShuffle:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VQShuffle:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2VSPat<SDNode N2VSPat:OpNode = ?, NeonI N2VSPat:Inst = ?> {	// Pattern Pat NEONFPPat
  dag PatternToMatch = (f32 (N2VSPat:OpNode SPR:$a));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (N2VSPat:Inst (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class N2VX<bits<2> N2VX:op24_23 = { ?, ? }, bits<2> N2VX:op21_20 = { ?, ? }, bits<2> N2VX:op19_18 = { ?, ? }, bits<2> N2VX:op17_16 = { ?, ? }, bits<5> N2VX:op11_7 = { ?, ?, ?, ?, ? }, bit N2VX:op6 = ?, bit N2VX:op4 = ?, dag N2VX:oops = ?, dag N2VX:iops = ?, InstrItinClass N2VX:itin = ?, string N2VX:opc = ?, string N2VX:asm = ?, string N2VX:cstr = ?, list<dag> N2VX:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N2VX:op24_23{1}, N2VX:op24_23{0}, Vd{4}, N2VX:op21_20{1}, N2VX:op21_20{0}, N2VX:op19_18{1}, N2VX:op19_18{0}, N2VX:op17_16{1}, N2VX:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N2VX:op11_7{4}, N2VX:op11_7{3}, N2VX:op11_7{2}, N2VX:op11_7{1}, N2VX:op11_7{0}, N2VX:op6, Vm{4}, N2VX:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N2VX:oops;
  dag InOperandList = !con(N2VX:iops, (ins pred:$p));
  string AsmString = !strconcat(N2VX:opc, !strconcat("${p}", !strconcat("	", N2VX:asm)));
  list<dag> Pattern = N2VX:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2VX:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N2VX:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N2Vnp<bits<2> N2Vnp:op19_18 = { ?, ? }, bits<2> N2Vnp:op17_16 = { ?, ? }, bits<3> N2Vnp:op10_8 = { ?, ?, ? }, bit N2Vnp:op7 = ?, bit N2Vnp:op6 = ?, dag N2Vnp:oops = ?, dag N2Vnp:iops = ?, InstrItinClass N2Vnp:itin = ?, string N2Vnp:OpcodeStr = ?, string N2Vnp:Dt = ?, list<dag> N2Vnp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, N2Vnp:op19_18{1}, N2Vnp:op19_18{0}, N2Vnp:op17_16{1}, N2Vnp:op17_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, N2Vnp:op10_8{2}, N2Vnp:op10_8{1}, N2Vnp:op10_8{0}, N2Vnp:op7, N2Vnp:op6, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N2Vnp:oops;
  dag InOperandList = N2Vnp:iops;
  string AsmString = !strconcat(N2Vnp:OpcodeStr, !strconcat(".", !strconcat(N2Vnp:Dt, "	$Vd, $Vm")));
  list<dag> Pattern = N2Vnp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N2Vnp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3SHA3Op<string N3SHA3Op:op = ?, bits<5> N3SHA3Op:op27_23 = { ?, ?, ?, ?, ? }, bits<2> N3SHA3Op:op21_20 = { ?, ? }, SDPatternOperator N3SHA3Op:Int = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQInt3np Requires
  field bits<32> Inst = { 1, 1, 1, 1, N3SHA3Op:op27_23{4}, N3SHA3Op:op27_23{3}, N3SHA3Op:op27_23{2}, N3SHA3Op:op27_23{1}, N3SHA3Op:op27_23{0}, Vd{4}, N3SHA3Op:op21_20{1}, N3SHA3Op:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vn, QPR:$Vm);
  string AsmString = !strconcat(!strconcat("sha", N3SHA3Op:op), ".32	$Vd, $Vn, $Vm");
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (N3SHA3Op:Int (v4i32 QPR:$src), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3V<bit N3V:op24 = ?, bit N3V:op23 = ?, bits<2> N3V:op21_20 = { ?, ? }, bits<4> N3V:op11_8 = { ?, ?, ?, ? }, bit N3V:op6 = ?, bit N3V:op4 = ?, dag N3V:oops = ?, dag N3V:iops = ?, Format N3V:f = ?, InstrItinClass N3V:itin = ?, string N3V:opc = ?, string N3V:dt = ?, string N3V:asm = ?, string N3V:cstr = ?, list<dag> N3V:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3V:op24, N3V:op23, Vd{4}, N3V:op21_20{1}, N3V:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3V:op11_8{3}, N3V:op11_8{2}, N3V:op11_8{1}, N3V:op11_8{0}, Vn{4}, N3V:op6, Vm{4}, N3V:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N3V:oops;
  dag InOperandList = !con(N3V:iops, (ins pred:$p));
  string AsmString = !strconcat(N3V:opc, !strconcat("${p}", !strconcat(".", !strconcat(N3V:dt, !strconcat("	", N3V:asm)))));
  list<dag> Pattern = N3V:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3V:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3V:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N3V:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3V:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VCP8<bits<2> N3VCP8:op24_23 = { ?, ? }, bits<2> N3VCP8:op21_20 = { ?, ? }, bit N3VCP8:op6 = ?, bit N3VCP8:op4 = ?, dag N3VCP8:oops = ?, dag N3VCP8:iops = ?, InstrItinClass N3VCP8:itin = ?, string N3VCP8:opc = ?, string N3VCP8:dt = ?, string N3VCP8:asm = ?, string N3VCP8:cstr = ?, list<dag> N3VCP8:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, N3VCP8:op24_23{1}, N3VCP8:op24_23{0}, Vd{4}, N3VCP8:op21_20{1}, N3VCP8:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, N3VCP8:op6, Vm{4}, N3VCP8:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N3VCP8:oops;
  dag InOperandList = N3VCP8:iops;
  string AsmString = !strconcat(N3VCP8:opc, !strconcat(".", !strconcat(N3VCP8:dt, !strconcat("	", N3VCP8:asm))));
  list<dag> Pattern = N3VCP8:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VCP8:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N3VCP8:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegCplxFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VCommon<bit N3VCommon:op24 = ?, bit N3VCommon:op23 = ?, bits<2> N3VCommon:op21_20 = { ?, ? }, bits<4> N3VCommon:op11_8 = { ?, ?, ?, ? }, bit N3VCommon:op6 = ?, bit N3VCommon:op4 = ?, dag N3VCommon:oops = ?, dag N3VCommon:iops = ?, Format N3VCommon:f = ?, InstrItinClass N3VCommon:itin = ?, string N3VCommon:opc = ?, string N3VCommon:dt = ?, string N3VCommon:asm = ?, string N3VCommon:cstr = ?, list<dag> N3VCommon:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VCommon:op24, N3VCommon:op23, ?, N3VCommon:op21_20{1}, N3VCommon:op21_20{0}, ?, ?, ?, ?, ?, ?, ?, ?, N3VCommon:op11_8{3}, N3VCommon:op11_8{2}, N3VCommon:op11_8{1}, N3VCommon:op11_8{0}, ?, N3VCommon:op6, ?, N3VCommon:op4, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N3VCommon:oops;
  dag InOperandList = !con(N3VCommon:iops, (ins pred:$p));
  string AsmString = !strconcat(N3VCommon:opc, !strconcat("${p}", !strconcat(".", !strconcat(N3VCommon:dt, !strconcat("	", N3VCommon:asm)))));
  list<dag> Pattern = N3VCommon:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VCommon:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VCommon:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N3VCommon:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VCommon:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class N3VD<bit N3VD:op24 = ?, bit N3VD:op23 = ?, bits<2> N3VD:op21_20 = { ?, ? }, bits<4> N3VD:op11_8 = { ?, ?, ?, ? }, bit N3VD:op4 = ?, InstrItinClass N3VD:itin = ?, string N3VD:OpcodeStr = ?, string N3VD:Dt = ?, ValueType N3VD:ResTy = ?, ValueType N3VD:OpTy = ?, SDNode N3VD:OpNode = ?, bit N3VD:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VD:op24, N3VD:op23, Vd{4}, N3VD:op21_20{1}, N3VD:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VD:op11_8{3}, N3VD:op11_8{2}, N3VD:op11_8{1}, N3VD:op11_8{0}, Vn{4}, 0, Vm{4}, N3VD:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VD:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VD:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N3VD:ResTy (N3VD:OpNode (N3VD:OpTy DPR:$Vn), (N3VD:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VD:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VD:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VDInt<bit N3VDInt:op24 = ?, bit N3VDInt:op23 = ?, bits<2> N3VDInt:op21_20 = { ?, ? }, bits<4> N3VDInt:op11_8 = { ?, ?, ?, ? }, bit N3VDInt:op4 = ?, Format N3VDInt:f = ?, InstrItinClass N3VDInt:itin = ?, string N3VDInt:OpcodeStr = ?, string N3VDInt:Dt = ?, ValueType N3VDInt:ResTy = ?, ValueType N3VDInt:OpTy = ?, SDPatternOperator N3VDInt:IntOp = ?, bit N3VDInt:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VDInt:op24, N3VDInt:op23, Vd{4}, N3VDInt:op21_20{1}, N3VDInt:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDInt:op11_8{3}, N3VDInt:op11_8{2}, N3VDInt:op11_8{1}, N3VDInt:op11_8{0}, Vn{4}, 0, Vm{4}, N3VDInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VDInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDInt:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N3VDInt:ResTy (N3VDInt:IntOp (N3VDInt:OpTy DPR:$Vn), (N3VDInt:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VDInt:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VDInt:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDInt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VDInt:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VDInt3<bit N3VDInt3:op24 = ?, bit N3VDInt3:op23 = ?, bits<2> N3VDInt3:op21_20 = { ?, ? }, bits<4> N3VDInt3:op11_8 = { ?, ?, ?, ? }, bit N3VDInt3:op4 = ?, InstrItinClass N3VDInt3:itin = ?, string N3VDInt3:OpcodeStr = ?, string N3VDInt3:Dt = ?, ValueType N3VDInt3:ResTy = ?, ValueType N3VDInt3:OpTy = ?, SDPatternOperator N3VDInt3:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VDInt3:op24, N3VDInt3:op23, Vd{4}, N3VDInt3:op21_20{1}, N3VDInt3:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDInt3:op11_8{3}, N3VDInt3:op11_8{2}, N3VDInt3:op11_8{1}, N3VDInt3:op11_8{0}, Vn{4}, 0, Vm{4}, N3VDInt3:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VDInt3:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDInt3:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N3VDInt3:ResTy (N3VDInt3:IntOp (N3VDInt3:OpTy DPR:$src1), (N3VDInt3:OpTy DPR:$Vn), (N3VDInt3:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDInt3:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VDIntOp<bit N3VDIntOp:op24 = ?, bit N3VDIntOp:op23 = ?, bits<2> N3VDIntOp:op21_20 = { ?, ? }, bits<4> N3VDIntOp:op11_8 = { ?, ?, ?, ? }, bit N3VDIntOp:op4 = ?, InstrItinClass N3VDIntOp:itin = ?, string N3VDIntOp:OpcodeStr = ?, string N3VDIntOp:Dt = ?, ValueType N3VDIntOp:Ty = ?, SDPatternOperator N3VDIntOp:IntOp = ?, SDNode N3VDIntOp:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VDIntOp:op24, N3VDIntOp:op23, Vd{4}, N3VDIntOp:op21_20{1}, N3VDIntOp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDIntOp:op11_8{3}, N3VDIntOp:op11_8{2}, N3VDIntOp:op11_8{1}, N3VDIntOp:op11_8{0}, Vn{4}, 0, Vm{4}, N3VDIntOp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VDIntOp:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDIntOp:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N3VDIntOp:Ty (N3VDIntOp:OpNode DPR:$src1, (N3VDIntOp:Ty (N3VDIntOp:IntOp (N3VDIntOp:Ty DPR:$Vn), (N3VDIntOp:Ty DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDIntOp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VDIntSL<bits<2> N3VDIntSL:op21_20 = { ?, ? }, bits<4> N3VDIntSL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VDIntSL:itin = ?, string N3VDIntSL:OpcodeStr = ?, string N3VDIntSL:Dt = ?, ValueType N3VDIntSL:Ty = ?, SDPatternOperator N3VDIntSL:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, N3VDIntSL:op21_20{1}, N3VDIntSL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDIntSL:op11_8{3}, N3VDIntSL:op11_8{2}, N3VDIntSL:op11_8{1}, N3VDIntSL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VDIntSL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDIntSL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VDIntSL:Ty DPR:$Vd), (N3VDIntSL:Ty (N3VDIntSL:IntOp (N3VDIntSL:Ty DPR:$Vn), (N3VDIntSL:Ty (NEONvduplane (N3VDIntSL:Ty DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDIntSL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VDIntSL16<bits<2> N3VDIntSL16:op21_20 = { ?, ? }, bits<4> N3VDIntSL16:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VDIntSL16:itin = ?, string N3VDIntSL16:OpcodeStr = ?, string N3VDIntSL16:Dt = ?, ValueType N3VDIntSL16:Ty = ?, SDPatternOperator N3VDIntSL16:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, N3VDIntSL16:op21_20{1}, N3VDIntSL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDIntSL16:op11_8{3}, N3VDIntSL16:op11_8{2}, N3VDIntSL16:op11_8{1}, N3VDIntSL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VDIntSL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDIntSL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VDIntSL16:Ty DPR:$Vd), (N3VDIntSL16:Ty (N3VDIntSL16:IntOp (N3VDIntSL16:Ty DPR:$Vn), (N3VDIntSL16:Ty (NEONvduplane (N3VDIntSL16:Ty DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDIntSL16:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VDIntSh<bit N3VDIntSh:op24 = ?, bit N3VDIntSh:op23 = ?, bits<2> N3VDIntSh:op21_20 = { ?, ? }, bits<4> N3VDIntSh:op11_8 = { ?, ?, ?, ? }, bit N3VDIntSh:op4 = ?, Format N3VDIntSh:f = ?, InstrItinClass N3VDIntSh:itin = ?, string N3VDIntSh:OpcodeStr = ?, string N3VDIntSh:Dt = ?, ValueType N3VDIntSh:ResTy = ?, ValueType N3VDIntSh:OpTy = ?, SDPatternOperator N3VDIntSh:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VDIntSh:op24, N3VDIntSh:op23, Vd{4}, N3VDIntSh:op21_20{1}, N3VDIntSh:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDIntSh:op11_8{3}, N3VDIntSh:op11_8{2}, N3VDIntSh:op11_8{1}, N3VDIntSh:op11_8{0}, Vn{4}, 0, Vm{4}, N3VDIntSh:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = !strconcat(N3VDIntSh:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDIntSh:Dt, "	$Vd, $Vm, $Vn"))));
  list<dag> Pattern = [(set DPR:$Vd, (N3VDIntSh:ResTy (N3VDIntSh:IntOp (N3VDIntSh:OpTy DPR:$Vm), (N3VDIntSh:OpTy DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VDIntSh:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDIntSh:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VDIntSh:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VDIntnp<bits<5> N3VDIntnp:op27_23 = { ?, ?, ?, ?, ? }, bits<2> N3VDIntnp:op21_20 = { ?, ? }, bits<4> N3VDIntnp:op11_8 = { ?, ?, ?, ? }, bit N3VDIntnp:op6 = ?, bit N3VDIntnp:op4 = ?, Format N3VDIntnp:f = ?, InstrItinClass N3VDIntnp:itin = ?, string N3VDIntnp:OpcodeStr = ?, string N3VDIntnp:Dt = ?, ValueType N3VDIntnp:ResTy = ?, ValueType N3VDIntnp:OpTy = ?, SDPatternOperator N3VDIntnp:IntOp = ?, bit N3VDIntnp:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp
  field bits<32> Inst = { 1, 1, 1, 1, N3VDIntnp:op27_23{4}, N3VDIntnp:op27_23{3}, N3VDIntnp:op27_23{2}, N3VDIntnp:op27_23{1}, N3VDIntnp:op27_23{0}, Vd{4}, N3VDIntnp:op21_20{1}, N3VDIntnp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDIntnp:op11_8{3}, N3VDIntnp:op11_8{2}, N3VDIntnp:op11_8{1}, N3VDIntnp:op11_8{0}, Vn{4}, N3VDIntnp:op6, Vm{4}, N3VDIntnp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm);
  string AsmString = !strconcat(N3VDIntnp:OpcodeStr, !strconcat(".", !strconcat(N3VDIntnp:Dt, "	$Vd, $Vn, $Vm")));
  list<dag> Pattern = [(set DPR:$Vd, (N3VDIntnp:ResTy (N3VDIntnp:IntOp (N3VDIntnp:OpTy DPR:$Vn), (N3VDIntnp:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDIntnp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VDMulOp<bit N3VDMulOp:op24 = ?, bit N3VDMulOp:op23 = ?, bits<2> N3VDMulOp:op21_20 = { ?, ? }, bits<4> N3VDMulOp:op11_8 = { ?, ?, ?, ? }, bit N3VDMulOp:op4 = ?, InstrItinClass N3VDMulOp:itin = ?, string N3VDMulOp:OpcodeStr = ?, string N3VDMulOp:Dt = ?, ValueType N3VDMulOp:Ty = ?, SDPatternOperator N3VDMulOp:MulOp = ?, SDPatternOperator N3VDMulOp:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VDMulOp:op24, N3VDMulOp:op23, Vd{4}, N3VDMulOp:op21_20{1}, N3VDMulOp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDMulOp:op11_8{3}, N3VDMulOp:op11_8{2}, N3VDMulOp:op11_8{1}, N3VDMulOp:op11_8{0}, Vn{4}, 0, Vm{4}, N3VDMulOp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VDMulOp:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDMulOp:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N3VDMulOp:Ty (N3VDMulOp:OpNode DPR:$src1, (N3VDMulOp:Ty (N3VDMulOp:MulOp DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDMulOp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VDMulOpSL<bits<2> N3VDMulOpSL:op21_20 = { ?, ? }, bits<4> N3VDMulOpSL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VDMulOpSL:itin = ?, string N3VDMulOpSL:OpcodeStr = ?, string N3VDMulOpSL:Dt = ?, ValueType N3VDMulOpSL:Ty = ?, SDPatternOperator N3VDMulOpSL:MulOp = ?, SDPatternOperator N3VDMulOpSL:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, N3VDMulOpSL:op21_20{1}, N3VDMulOpSL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDMulOpSL:op11_8{3}, N3VDMulOpSL:op11_8{2}, N3VDMulOpSL:op11_8{1}, N3VDMulOpSL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VDMulOpSL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDMulOpSL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VDMulOpSL:Ty DPR:$Vd), (N3VDMulOpSL:Ty (N3VDMulOpSL:ShOp (N3VDMulOpSL:Ty DPR:$src1), (N3VDMulOpSL:Ty (N3VDMulOpSL:MulOp DPR:$Vn, (N3VDMulOpSL:Ty (NEONvduplane (N3VDMulOpSL:Ty DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDMulOpSL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VDMulOpSL16<bits<2> N3VDMulOpSL16:op21_20 = { ?, ? }, bits<4> N3VDMulOpSL16:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VDMulOpSL16:itin = ?, string N3VDMulOpSL16:OpcodeStr = ?, string N3VDMulOpSL16:Dt = ?, ValueType N3VDMulOpSL16:Ty = ?, SDPatternOperator N3VDMulOpSL16:MulOp = ?, SDPatternOperator N3VDMulOpSL16:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, N3VDMulOpSL16:op21_20{1}, N3VDMulOpSL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDMulOpSL16:op11_8{3}, N3VDMulOpSL16:op11_8{2}, N3VDMulOpSL16:op11_8{1}, N3VDMulOpSL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VDMulOpSL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDMulOpSL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VDMulOpSL16:Ty DPR:$Vd), (N3VDMulOpSL16:Ty (N3VDMulOpSL16:ShOp (N3VDMulOpSL16:Ty DPR:$src1), (N3VDMulOpSL16:Ty (N3VDMulOpSL16:MulOp DPR:$Vn, (N3VDMulOpSL16:Ty (NEONvduplane (N3VDMulOpSL16:Ty DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDMulOpSL16:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VDSL<bits<2> N3VDSL:op21_20 = { ?, ? }, bits<4> N3VDSL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VDSL:itin = ?, string N3VDSL:OpcodeStr = ?, string N3VDSL:Dt = ?, ValueType N3VDSL:Ty = ?, SDNode N3VDSL:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, N3VDSL:op21_20{1}, N3VDSL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDSL:op11_8{3}, N3VDSL:op11_8{2}, N3VDSL:op11_8{1}, N3VDSL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VDSL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDSL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VDSL:Ty DPR:$Vd), (N3VDSL:Ty (N3VDSL:ShOp (N3VDSL:Ty DPR:$Vn), (N3VDSL:Ty (NEONvduplane (N3VDSL:Ty DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDSL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VDSL16<bits<2> N3VDSL16:op21_20 = { ?, ? }, bits<4> N3VDSL16:op11_8 = { ?, ?, ?, ? }, string N3VDSL16:OpcodeStr = ?, string N3VDSL16:Dt = ?, ValueType N3VDSL16:Ty = ?, SDNode N3VDSL16:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, N3VDSL16:op21_20{1}, N3VDSL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDSL16:op11_8{3}, N3VDSL16:op11_8{2}, N3VDSL16:op11_8{1}, N3VDSL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VDSL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VDSL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VDSL16:Ty DPR:$Vd), (N3VDSL16:Ty (N3VDSL16:ShOp (N3VDSL16:Ty DPR:$Vn), (N3VDSL16:Ty (NEONvduplane (N3VDSL16:Ty DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VDX<bit N3VDX:op24 = ?, bit N3VDX:op23 = ?, bits<2> N3VDX:op21_20 = { ?, ? }, bits<4> N3VDX:op11_8 = { ?, ?, ?, ? }, bit N3VDX:op4 = ?, InstrItinClass N3VDX:itin = ?, string N3VDX:OpcodeStr = ?, ValueType N3VDX:ResTy = ?, ValueType N3VDX:OpTy = ?, SDNode N3VDX:OpNode = ?, bit N3VDX:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VDX:op24, N3VDX:op23, Vd{4}, N3VDX:op21_20{1}, N3VDX:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VDX:op11_8{3}, N3VDX:op11_8{2}, N3VDX:op11_8{1}, N3VDX:op11_8{0}, Vn{4}, 0, Vm{4}, N3VDX:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VDX:OpcodeStr, "${p}	$Vd, $Vn, $Vm");
  list<dag> Pattern = [(set DPR:$Vd, (N3VDX:ResTy (N3VDX:OpNode (N3VDX:OpTy DPR:$Vn), (N3VDX:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VDX:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VDX:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VL<bit N3VL:op24 = ?, bit N3VL:op23 = ?, bits<2> N3VL:op21_20 = { ?, ? }, bits<4> N3VL:op11_8 = { ?, ?, ?, ? }, bit N3VL:op4 = ?, InstrItinClass N3VL:itin = ?, string N3VL:OpcodeStr = ?, string N3VL:Dt = ?, ValueType N3VL:TyQ = ?, ValueType N3VL:TyD = ?, SDNode N3VL:OpNode = ?, bit N3VL:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VL:op24, N3VL:op23, Vd{4}, N3VL:op21_20{1}, N3VL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VL:op11_8{3}, N3VL:op11_8{2}, N3VL:op11_8{1}, N3VL:op11_8{0}, Vn{4}, 0, Vm{4}, N3VL:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VL:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VL:TyQ (N3VL:OpNode (N3VL:TyD DPR:$Vn), (N3VL:TyD DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VL:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VLExt<bit N3VLExt:op24 = ?, bit N3VLExt:op23 = ?, bits<2> N3VLExt:op21_20 = { ?, ? }, bits<4> N3VLExt:op11_8 = { ?, ?, ?, ? }, bit N3VLExt:op4 = ?, InstrItinClass N3VLExt:itin = ?, string N3VLExt:OpcodeStr = ?, string N3VLExt:Dt = ?, ValueType N3VLExt:TyQ = ?, ValueType N3VLExt:TyD = ?, SDNode N3VLExt:OpNode = ?, SDNode N3VLExt:ExtOp = ?, bit N3VLExt:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLExt:op24, N3VLExt:op23, Vd{4}, N3VLExt:op21_20{1}, N3VLExt:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLExt:op11_8{3}, N3VLExt:op11_8{2}, N3VLExt:op11_8{1}, N3VLExt:op11_8{0}, Vn{4}, 0, Vm{4}, N3VLExt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VLExt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLExt:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLExt:OpNode (N3VLExt:TyQ (N3VLExt:ExtOp (N3VLExt:TyD DPR:$Vn))), (N3VLExt:TyQ (N3VLExt:ExtOp (N3VLExt:TyD DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VLExt:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLExt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VLInt<bit N3VLInt:op24 = ?, bit N3VLInt:op23 = ?, bits<2> N3VLInt:op21_20 = { ?, ? }, bits<4> N3VLInt:op11_8 = { ?, ?, ?, ? }, bit N3VLInt:op4 = ?, InstrItinClass N3VLInt:itin = ?, string N3VLInt:OpcodeStr = ?, string N3VLInt:Dt = ?, ValueType N3VLInt:TyQ = ?, ValueType N3VLInt:TyD = ?, SDPatternOperator N3VLInt:IntOp = ?, bit N3VLInt:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLInt:op24, N3VLInt:op23, Vd{4}, N3VLInt:op21_20{1}, N3VLInt:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLInt:op11_8{3}, N3VLInt:op11_8{2}, N3VLInt:op11_8{1}, N3VLInt:op11_8{0}, Vn{4}, 0, Vm{4}, N3VLInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VLInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLInt:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLInt:TyQ (N3VLInt:IntOp (N3VLInt:TyD DPR:$Vn), (N3VLInt:TyD DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VLInt:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLInt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VLInt3<bit N3VLInt3:op24 = ?, bit N3VLInt3:op23 = ?, bits<2> N3VLInt3:op21_20 = { ?, ? }, bits<4> N3VLInt3:op11_8 = { ?, ?, ?, ? }, bit N3VLInt3:op4 = ?, InstrItinClass N3VLInt3:itin = ?, string N3VLInt3:OpcodeStr = ?, string N3VLInt3:Dt = ?, ValueType N3VLInt3:TyQ = ?, ValueType N3VLInt3:TyD = ?, SDPatternOperator N3VLInt3:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLInt3:op24, N3VLInt3:op23, Vd{4}, N3VLInt3:op21_20{1}, N3VLInt3:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLInt3:op11_8{3}, N3VLInt3:op11_8{2}, N3VLInt3:op11_8{1}, N3VLInt3:op11_8{0}, Vn{4}, 0, Vm{4}, N3VLInt3:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VLInt3:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLInt3:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLInt3:TyQ (N3VLInt3:IntOp (N3VLInt3:TyQ QPR:$src1), (N3VLInt3:TyD DPR:$Vn), (N3VLInt3:TyD DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLInt3:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VLInt3SL<bit N3VLInt3SL:op24 = ?, bits<2> N3VLInt3SL:op21_20 = { ?, ? }, bits<4> N3VLInt3SL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VLInt3SL:itin = ?, string N3VLInt3SL:OpcodeStr = ?, string N3VLInt3SL:Dt = ?, ValueType N3VLInt3SL:ResTy = ?, ValueType N3VLInt3SL:OpTy = ?, SDPatternOperator N3VLInt3SL:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLInt3SL:op24, 1, Vd{4}, N3VLInt3SL:op21_20{1}, N3VLInt3SL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLInt3SL:op11_8{3}, N3VLInt3SL:op11_8{2}, N3VLInt3SL:op11_8{1}, N3VLInt3SL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VLInt3SL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLInt3SL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VLInt3SL:ResTy QPR:$Vd), (N3VLInt3SL:ResTy (N3VLInt3SL:IntOp (N3VLInt3SL:ResTy QPR:$src1), (N3VLInt3SL:OpTy DPR:$Vn), (N3VLInt3SL:OpTy (NEONvduplane (N3VLInt3SL:OpTy DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLInt3SL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VLInt3SL16<bit N3VLInt3SL16:op24 = ?, bits<2> N3VLInt3SL16:op21_20 = { ?, ? }, bits<4> N3VLInt3SL16:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VLInt3SL16:itin = ?, string N3VLInt3SL16:OpcodeStr = ?, string N3VLInt3SL16:Dt = ?, ValueType N3VLInt3SL16:ResTy = ?, ValueType N3VLInt3SL16:OpTy = ?, SDPatternOperator N3VLInt3SL16:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLInt3SL16:op24, 1, Vd{4}, N3VLInt3SL16:op21_20{1}, N3VLInt3SL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLInt3SL16:op11_8{3}, N3VLInt3SL16:op11_8{2}, N3VLInt3SL16:op11_8{1}, N3VLInt3SL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VLInt3SL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLInt3SL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VLInt3SL16:ResTy QPR:$Vd), (N3VLInt3SL16:ResTy (N3VLInt3SL16:IntOp (N3VLInt3SL16:ResTy QPR:$src1), (N3VLInt3SL16:OpTy DPR:$Vn), (N3VLInt3SL16:OpTy (NEONvduplane (N3VLInt3SL16:OpTy DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLInt3SL16:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VLIntExt<bit N3VLIntExt:op24 = ?, bit N3VLIntExt:op23 = ?, bits<2> N3VLIntExt:op21_20 = { ?, ? }, bits<4> N3VLIntExt:op11_8 = { ?, ?, ?, ? }, bit N3VLIntExt:op4 = ?, InstrItinClass N3VLIntExt:itin = ?, string N3VLIntExt:OpcodeStr = ?, string N3VLIntExt:Dt = ?, ValueType N3VLIntExt:TyQ = ?, ValueType N3VLIntExt:TyD = ?, SDPatternOperator N3VLIntExt:IntOp = ?, SDNode N3VLIntExt:ExtOp = ?, bit N3VLIntExt:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLIntExt:op24, N3VLIntExt:op23, Vd{4}, N3VLIntExt:op21_20{1}, N3VLIntExt:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLIntExt:op11_8{3}, N3VLIntExt:op11_8{2}, N3VLIntExt:op11_8{1}, N3VLIntExt:op11_8{0}, Vn{4}, 0, Vm{4}, N3VLIntExt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VLIntExt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLIntExt:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLIntExt:TyQ (N3VLIntExt:ExtOp (N3VLIntExt:TyD (N3VLIntExt:IntOp (N3VLIntExt:TyD DPR:$Vn), (N3VLIntExt:TyD DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VLIntExt:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLIntExt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VLIntExtOp<bit N3VLIntExtOp:op24 = ?, bit N3VLIntExtOp:op23 = ?, bits<2> N3VLIntExtOp:op21_20 = { ?, ? }, bits<4> N3VLIntExtOp:op11_8 = { ?, ?, ?, ? }, bit N3VLIntExtOp:op4 = ?, InstrItinClass N3VLIntExtOp:itin = ?, string N3VLIntExtOp:OpcodeStr = ?, string N3VLIntExtOp:Dt = ?, ValueType N3VLIntExtOp:TyQ = ?, ValueType N3VLIntExtOp:TyD = ?, SDPatternOperator N3VLIntExtOp:IntOp = ?, SDNode N3VLIntExtOp:ExtOp = ?, SDNode N3VLIntExtOp:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLIntExtOp:op24, N3VLIntExtOp:op23, Vd{4}, N3VLIntExtOp:op21_20{1}, N3VLIntExtOp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLIntExtOp:op11_8{3}, N3VLIntExtOp:op11_8{2}, N3VLIntExtOp:op11_8{1}, N3VLIntExtOp:op11_8{0}, Vn{4}, 0, Vm{4}, N3VLIntExtOp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VLIntExtOp:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLIntExtOp:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLIntExtOp:OpNode (N3VLIntExtOp:TyQ QPR:$src1), (N3VLIntExtOp:TyQ (N3VLIntExtOp:ExtOp (N3VLIntExtOp:TyD (N3VLIntExtOp:IntOp (N3VLIntExtOp:TyD DPR:$Vn), (N3VLIntExtOp:TyD DPR:$Vm)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLIntExtOp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VLIntSL<bit N3VLIntSL:op24 = ?, bits<2> N3VLIntSL:op21_20 = { ?, ? }, bits<4> N3VLIntSL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VLIntSL:itin = ?, string N3VLIntSL:OpcodeStr = ?, string N3VLIntSL:Dt = ?, ValueType N3VLIntSL:ResTy = ?, ValueType N3VLIntSL:OpTy = ?, SDPatternOperator N3VLIntSL:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLIntSL:op24, 1, Vd{4}, N3VLIntSL:op21_20{1}, N3VLIntSL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLIntSL:op11_8{3}, N3VLIntSL:op11_8{2}, N3VLIntSL:op11_8{1}, N3VLIntSL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VLIntSL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLIntSL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VLIntSL:ResTy QPR:$Vd), (N3VLIntSL:ResTy (N3VLIntSL:IntOp (N3VLIntSL:OpTy DPR:$Vn), (N3VLIntSL:OpTy (NEONvduplane (N3VLIntSL:OpTy DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLIntSL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VLIntSL16<bit N3VLIntSL16:op24 = ?, bits<2> N3VLIntSL16:op21_20 = { ?, ? }, bits<4> N3VLIntSL16:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VLIntSL16:itin = ?, string N3VLIntSL16:OpcodeStr = ?, string N3VLIntSL16:Dt = ?, ValueType N3VLIntSL16:ResTy = ?, ValueType N3VLIntSL16:OpTy = ?, SDPatternOperator N3VLIntSL16:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLIntSL16:op24, 1, Vd{4}, N3VLIntSL16:op21_20{1}, N3VLIntSL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLIntSL16:op11_8{3}, N3VLIntSL16:op11_8{2}, N3VLIntSL16:op11_8{1}, N3VLIntSL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VLIntSL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLIntSL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VLIntSL16:ResTy QPR:$Vd), (N3VLIntSL16:ResTy (N3VLIntSL16:IntOp (N3VLIntSL16:OpTy DPR:$Vn), (N3VLIntSL16:OpTy (NEONvduplane (N3VLIntSL16:OpTy DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLIntSL16:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VLIntnp<bits<5> N3VLIntnp:op27_23 = { ?, ?, ?, ?, ? }, bits<2> N3VLIntnp:op21_20 = { ?, ? }, bits<4> N3VLIntnp:op11_8 = { ?, ?, ?, ? }, bit N3VLIntnp:op6 = ?, bit N3VLIntnp:op4 = ?, InstrItinClass N3VLIntnp:itin = ?, string N3VLIntnp:OpcodeStr = ?, string N3VLIntnp:Dt = ?, ValueType N3VLIntnp:ResTy = ?, ValueType N3VLIntnp:OpTy = ?, SDPatternOperator N3VLIntnp:IntOp = ?, bit N3VLIntnp:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp
  field bits<32> Inst = { 1, 1, 1, 1, N3VLIntnp:op27_23{4}, N3VLIntnp:op27_23{3}, N3VLIntnp:op27_23{2}, N3VLIntnp:op27_23{1}, N3VLIntnp:op27_23{0}, Vd{4}, N3VLIntnp:op21_20{1}, N3VLIntnp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLIntnp:op11_8{3}, N3VLIntnp:op11_8{2}, N3VLIntnp:op11_8{1}, N3VLIntnp:op11_8{0}, Vn{4}, N3VLIntnp:op6, Vm{4}, N3VLIntnp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm);
  string AsmString = !strconcat(N3VLIntnp:OpcodeStr, !strconcat(".", !strconcat(N3VLIntnp:Dt, "	$Vd, $Vn, $Vm")));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLIntnp:ResTy (N3VLIntnp:IntOp (N3VLIntnp:OpTy DPR:$Vn), (N3VLIntnp:OpTy DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLIntnp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VLMulOp<bit N3VLMulOp:op24 = ?, bit N3VLMulOp:op23 = ?, bits<2> N3VLMulOp:op21_20 = { ?, ? }, bits<4> N3VLMulOp:op11_8 = { ?, ?, ?, ? }, bit N3VLMulOp:op4 = ?, InstrItinClass N3VLMulOp:itin = ?, string N3VLMulOp:OpcodeStr = ?, string N3VLMulOp:Dt = ?, ValueType N3VLMulOp:TyQ = ?, ValueType N3VLMulOp:TyD = ?, SDNode N3VLMulOp:MulOp = ?, SDNode N3VLMulOp:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLMulOp:op24, N3VLMulOp:op23, Vd{4}, N3VLMulOp:op21_20{1}, N3VLMulOp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLMulOp:op11_8{3}, N3VLMulOp:op11_8{2}, N3VLMulOp:op11_8{1}, N3VLMulOp:op11_8{0}, Vn{4}, 0, Vm{4}, N3VLMulOp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VLMulOp:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLMulOp:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLMulOp:OpNode (N3VLMulOp:TyQ QPR:$src1), (N3VLMulOp:TyQ (N3VLMulOp:MulOp (N3VLMulOp:TyD DPR:$Vn), (N3VLMulOp:TyD DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLMulOp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VLMulOpSL<bit N3VLMulOpSL:op24 = ?, bits<2> N3VLMulOpSL:op21_20 = { ?, ? }, bits<4> N3VLMulOpSL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VLMulOpSL:itin = ?, string N3VLMulOpSL:OpcodeStr = ?, string N3VLMulOpSL:Dt = ?, ValueType N3VLMulOpSL:TyQ = ?, ValueType N3VLMulOpSL:TyD = ?, SDNode N3VLMulOpSL:MulOp = ?, SDNode N3VLMulOpSL:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLMulOpSL:op24, 1, Vd{4}, N3VLMulOpSL:op21_20{1}, N3VLMulOpSL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLMulOpSL:op11_8{3}, N3VLMulOpSL:op11_8{2}, N3VLMulOpSL:op11_8{1}, N3VLMulOpSL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VLMulOpSL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLMulOpSL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLMulOpSL:OpNode (N3VLMulOpSL:TyQ QPR:$src1), (N3VLMulOpSL:TyQ (N3VLMulOpSL:MulOp (N3VLMulOpSL:TyD DPR:$Vn), (N3VLMulOpSL:TyD (NEONvduplane (N3VLMulOpSL:TyD DPR_VFP2:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLMulOpSL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VLMulOpSL16<bit N3VLMulOpSL16:op24 = ?, bits<2> N3VLMulOpSL16:op21_20 = { ?, ? }, bits<4> N3VLMulOpSL16:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VLMulOpSL16:itin = ?, string N3VLMulOpSL16:OpcodeStr = ?, string N3VLMulOpSL16:Dt = ?, ValueType N3VLMulOpSL16:TyQ = ?, ValueType N3VLMulOpSL16:TyD = ?, SDNode N3VLMulOpSL16:MulOp = ?, SDNode N3VLMulOpSL16:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLMulOpSL16:op24, 1, Vd{4}, N3VLMulOpSL16:op21_20{1}, N3VLMulOpSL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLMulOpSL16:op11_8{3}, N3VLMulOpSL16:op11_8{2}, N3VLMulOpSL16:op11_8{1}, N3VLMulOpSL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VLMulOpSL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLMulOpSL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLMulOpSL16:OpNode (N3VLMulOpSL16:TyQ QPR:$src1), (N3VLMulOpSL16:TyQ (N3VLMulOpSL16:MulOp (N3VLMulOpSL16:TyD DPR:$Vn), (N3VLMulOpSL16:TyD (NEONvduplane (N3VLMulOpSL16:TyD DPR_8:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLMulOpSL16:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VLSL<bit N3VLSL:op24 = ?, bits<2> N3VLSL:op21_20 = { ?, ? }, bits<4> N3VLSL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VLSL:itin = ?, string N3VLSL:OpcodeStr = ?, string N3VLSL:Dt = ?, ValueType N3VLSL:TyQ = ?, ValueType N3VLSL:TyD = ?, SDNode N3VLSL:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLSL:op24, 1, Vd{4}, N3VLSL:op21_20{1}, N3VLSL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLSL:op11_8{3}, N3VLSL:op11_8{2}, N3VLSL:op11_8{1}, N3VLSL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VLSL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLSL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLSL:TyQ (N3VLSL:OpNode (N3VLSL:TyD DPR:$Vn), (N3VLSL:TyD (NEONvduplane (N3VLSL:TyD DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLSL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VLSL16<bit N3VLSL16:op24 = ?, bits<2> N3VLSL16:op21_20 = { ?, ? }, bits<4> N3VLSL16:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VLSL16:itin = ?, string N3VLSL16:OpcodeStr = ?, string N3VLSL16:Dt = ?, ValueType N3VLSL16:TyQ = ?, ValueType N3VLSL16:TyD = ?, SDNode N3VLSL16:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLSL16:op24, 1, Vd{4}, N3VLSL16:op21_20{1}, N3VLSL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLSL16:op11_8{3}, N3VLSL16:op11_8{2}, N3VLSL16:op11_8{1}, N3VLSL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VLSL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VLSL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VLSL16:TyQ (N3VLSL16:OpNode (N3VLSL16:TyD DPR:$Vn), (N3VLSL16:TyD (NEONvduplane (N3VLSL16:TyD DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLSL16:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VLane16<bit N3VLane16:op24 = ?, bit N3VLane16:op23 = ?, bits<2> N3VLane16:op21_20 = { ?, ? }, bits<4> N3VLane16:op11_8 = { ?, ?, ?, ? }, bit N3VLane16:op6 = ?, bit N3VLane16:op4 = ?, dag N3VLane16:oops = ?, dag N3VLane16:iops = ?, Format N3VLane16:f = ?, InstrItinClass N3VLane16:itin = ?, string N3VLane16:opc = ?, string N3VLane16:dt = ?, string N3VLane16:asm = ?, string N3VLane16:cstr = ?, list<dag> N3VLane16:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLane16:op24, N3VLane16:op23, Vd{4}, N3VLane16:op21_20{1}, N3VLane16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLane16:op11_8{3}, N3VLane16:op11_8{2}, N3VLane16:op11_8{1}, N3VLane16:op11_8{0}, Vn{4}, N3VLane16:op6, lane{1}, N3VLane16:op4, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N3VLane16:oops;
  dag InOperandList = !con(N3VLane16:iops, (ins pred:$p));
  string AsmString = !strconcat(N3VLane16:opc, !strconcat("${p}", !strconcat(".", !strconcat(N3VLane16:dt, !strconcat("	", N3VLane16:asm)))));
  list<dag> Pattern = N3VLane16:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VLane16:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLane16:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N3VLane16:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VLane16:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VLane32<bit N3VLane32:op24 = ?, bit N3VLane32:op23 = ?, bits<2> N3VLane32:op21_20 = { ?, ? }, bits<4> N3VLane32:op11_8 = { ?, ?, ?, ? }, bit N3VLane32:op6 = ?, bit N3VLane32:op4 = ?, dag N3VLane32:oops = ?, dag N3VLane32:iops = ?, Format N3VLane32:f = ?, InstrItinClass N3VLane32:itin = ?, string N3VLane32:opc = ?, string N3VLane32:dt = ?, string N3VLane32:asm = ?, string N3VLane32:cstr = ?, list<dag> N3VLane32:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VLane32:op24, N3VLane32:op23, Vd{4}, N3VLane32:op21_20{1}, N3VLane32:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VLane32:op11_8{3}, N3VLane32:op11_8{2}, N3VLane32:op11_8{1}, N3VLane32:op11_8{0}, Vn{4}, N3VLane32:op6, lane, N3VLane32:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N3VLane32:oops;
  dag InOperandList = !con(N3VLane32:iops, (ins pred:$p));
  string AsmString = !strconcat(N3VLane32:opc, !strconcat("${p}", !strconcat(".", !strconcat(N3VLane32:dt, !strconcat("	", N3VLane32:asm)))));
  list<dag> Pattern = N3VLane32:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VLane32:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLane32:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N3VLane32:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VLane32:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VLaneCP8<bit N3VLaneCP8:op23 = ?, bits<2> N3VLaneCP8:op21_20 = { ?, ? }, bit N3VLaneCP8:op6 = ?, bit N3VLaneCP8:op4 = ?, dag N3VLaneCP8:oops = ?, dag N3VLaneCP8:iops = ?, InstrItinClass N3VLaneCP8:itin = ?, string N3VLaneCP8:opc = ?, string N3VLaneCP8:dt = ?, string N3VLaneCP8:asm = ?, string N3VLaneCP8:cstr = ?, list<dag> N3VLaneCP8:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, N3VLaneCP8:op23, Vd{4}, N3VLaneCP8:op21_20{1}, N3VLaneCP8:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, N3VLaneCP8:op6, ?, N3VLaneCP8:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N3VLaneCP8:oops;
  dag InOperandList = N3VLaneCP8:iops;
  string AsmString = !strconcat(N3VLaneCP8:opc, !strconcat(".", !strconcat(N3VLaneCP8:dt, !strconcat("	", N3VLaneCP8:asm))));
  list<dag> Pattern = N3VLaneCP8:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VLaneCP8:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N3VLaneCP8:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegCplxFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VNInt<bit N3VNInt:op24 = ?, bit N3VNInt:op23 = ?, bits<2> N3VNInt:op21_20 = { ?, ? }, bits<4> N3VNInt:op11_8 = { ?, ?, ?, ? }, bit N3VNInt:op4 = ?, string N3VNInt:OpcodeStr = ?, string N3VNInt:Dt = ?, ValueType N3VNInt:TyD = ?, ValueType N3VNInt:TyQ = ?, SDPatternOperator N3VNInt:IntOp = ?, bit N3VNInt:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VNInt:op24, N3VNInt:op23, Vd{4}, N3VNInt:op21_20{1}, N3VNInt:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VNInt:op11_8{3}, N3VNInt:op11_8{2}, N3VNInt:op11_8{1}, N3VNInt:op11_8{0}, Vn{4}, 0, Vm{4}, N3VNInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VNInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VNInt:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (N3VNInt:TyD (N3VNInt:IntOp (N3VNInt:TyQ QPR:$Vn), (N3VNInt:TyQ QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VNInt:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VQ<bit N3VQ:op24 = ?, bit N3VQ:op23 = ?, bits<2> N3VQ:op21_20 = { ?, ? }, bits<4> N3VQ:op11_8 = { ?, ?, ?, ? }, bit N3VQ:op4 = ?, InstrItinClass N3VQ:itin = ?, string N3VQ:OpcodeStr = ?, string N3VQ:Dt = ?, ValueType N3VQ:ResTy = ?, ValueType N3VQ:OpTy = ?, SDNode N3VQ:OpNode = ?, bit N3VQ:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VQ:op24, N3VQ:op23, Vd{4}, N3VQ:op21_20{1}, N3VQ:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQ:op11_8{3}, N3VQ:op11_8{2}, N3VQ:op11_8{1}, N3VQ:op11_8{0}, Vn{4}, 1, Vm{4}, N3VQ:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VQ:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQ:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VQ:ResTy (N3VQ:OpNode (N3VQ:OpTy QPR:$Vn), (N3VQ:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VQ:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQ:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VQInt<bit N3VQInt:op24 = ?, bit N3VQInt:op23 = ?, bits<2> N3VQInt:op21_20 = { ?, ? }, bits<4> N3VQInt:op11_8 = { ?, ?, ?, ? }, bit N3VQInt:op4 = ?, Format N3VQInt:f = ?, InstrItinClass N3VQInt:itin = ?, string N3VQInt:OpcodeStr = ?, string N3VQInt:Dt = ?, ValueType N3VQInt:ResTy = ?, ValueType N3VQInt:OpTy = ?, SDPatternOperator N3VQInt:IntOp = ?, bit N3VQInt:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VQInt:op24, N3VQInt:op23, Vd{4}, N3VQInt:op21_20{1}, N3VQInt:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQInt:op11_8{3}, N3VQInt:op11_8{2}, N3VQInt:op11_8{1}, N3VQInt:op11_8{0}, Vn{4}, 1, Vm{4}, N3VQInt:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VQInt:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQInt:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VQInt:ResTy (N3VQInt:IntOp (N3VQInt:OpTy QPR:$Vn), (N3VQInt:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VQInt:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VQInt:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQInt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VQInt:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VQInt3<bit N3VQInt3:op24 = ?, bit N3VQInt3:op23 = ?, bits<2> N3VQInt3:op21_20 = { ?, ? }, bits<4> N3VQInt3:op11_8 = { ?, ?, ?, ? }, bit N3VQInt3:op4 = ?, InstrItinClass N3VQInt3:itin = ?, string N3VQInt3:OpcodeStr = ?, string N3VQInt3:Dt = ?, ValueType N3VQInt3:ResTy = ?, ValueType N3VQInt3:OpTy = ?, SDPatternOperator N3VQInt3:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VQInt3:op24, N3VQInt3:op23, Vd{4}, N3VQInt3:op21_20{1}, N3VQInt3:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQInt3:op11_8{3}, N3VQInt3:op11_8{2}, N3VQInt3:op11_8{1}, N3VQInt3:op11_8{0}, Vn{4}, 1, Vm{4}, N3VQInt3:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VQInt3:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQInt3:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VQInt3:ResTy (N3VQInt3:IntOp (N3VQInt3:OpTy QPR:$src1), (N3VQInt3:OpTy QPR:$Vn), (N3VQInt3:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQInt3:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VQInt3np<bits<5> N3VQInt3np:op27_23 = { ?, ?, ?, ?, ? }, bits<2> N3VQInt3np:op21_20 = { ?, ? }, bits<4> N3VQInt3np:op11_8 = { ?, ?, ?, ? }, bit N3VQInt3np:op6 = ?, bit N3VQInt3np:op4 = ?, Format N3VQInt3np:f = ?, InstrItinClass N3VQInt3np:itin = ?, string N3VQInt3np:OpcodeStr = ?, string N3VQInt3np:Dt = ?, ValueType N3VQInt3np:ResTy = ?, ValueType N3VQInt3np:OpTy = ?, SDPatternOperator N3VQInt3np:IntOp = ?, bit N3VQInt3np:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp
  field bits<32> Inst = { 1, 1, 1, 1, N3VQInt3np:op27_23{4}, N3VQInt3np:op27_23{3}, N3VQInt3np:op27_23{2}, N3VQInt3np:op27_23{1}, N3VQInt3np:op27_23{0}, Vd{4}, N3VQInt3np:op21_20{1}, N3VQInt3np:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQInt3np:op11_8{3}, N3VQInt3np:op11_8{2}, N3VQInt3np:op11_8{1}, N3VQInt3np:op11_8{0}, Vn{4}, N3VQInt3np:op6, Vm{4}, N3VQInt3np:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vn, QPR:$Vm);
  string AsmString = !strconcat(N3VQInt3np:OpcodeStr, !strconcat(".", !strconcat(N3VQInt3np:Dt, "	$Vd, $Vn, $Vm")));
  list<dag> Pattern = [(set QPR:$Vd, (N3VQInt3np:ResTy (N3VQInt3np:IntOp (N3VQInt3np:OpTy QPR:$src), (N3VQInt3np:OpTy QPR:$Vn), (N3VQInt3np:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VQInt3np:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQInt3np:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VQInt3np:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VQIntOp<bit N3VQIntOp:op24 = ?, bit N3VQIntOp:op23 = ?, bits<2> N3VQIntOp:op21_20 = { ?, ? }, bits<4> N3VQIntOp:op11_8 = { ?, ?, ?, ? }, bit N3VQIntOp:op4 = ?, InstrItinClass N3VQIntOp:itin = ?, string N3VQIntOp:OpcodeStr = ?, string N3VQIntOp:Dt = ?, ValueType N3VQIntOp:Ty = ?, SDPatternOperator N3VQIntOp:IntOp = ?, SDNode N3VQIntOp:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VQIntOp:op24, N3VQIntOp:op23, Vd{4}, N3VQIntOp:op21_20{1}, N3VQIntOp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQIntOp:op11_8{3}, N3VQIntOp:op11_8{2}, N3VQIntOp:op11_8{1}, N3VQIntOp:op11_8{0}, Vn{4}, 1, Vm{4}, N3VQIntOp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VQIntOp:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQIntOp:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VQIntOp:Ty (N3VQIntOp:OpNode QPR:$src1, (N3VQIntOp:Ty (N3VQIntOp:IntOp (N3VQIntOp:Ty QPR:$Vn), (N3VQIntOp:Ty QPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQIntOp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VQIntSL<bits<2> N3VQIntSL:op21_20 = { ?, ? }, bits<4> N3VQIntSL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VQIntSL:itin = ?, string N3VQIntSL:OpcodeStr = ?, string N3VQIntSL:Dt = ?, ValueType N3VQIntSL:ResTy = ?, ValueType N3VQIntSL:OpTy = ?, SDPatternOperator N3VQIntSL:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, N3VQIntSL:op21_20{1}, N3VQIntSL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQIntSL:op11_8{3}, N3VQIntSL:op11_8{2}, N3VQIntSL:op11_8{1}, N3VQIntSL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VQIntSL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQIntSL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VQIntSL:ResTy QPR:$Vd), (N3VQIntSL:ResTy (N3VQIntSL:IntOp (N3VQIntSL:ResTy QPR:$Vn), (N3VQIntSL:ResTy (NEONvduplane (N3VQIntSL:OpTy DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQIntSL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VQIntSL16<bits<2> N3VQIntSL16:op21_20 = { ?, ? }, bits<4> N3VQIntSL16:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VQIntSL16:itin = ?, string N3VQIntSL16:OpcodeStr = ?, string N3VQIntSL16:Dt = ?, ValueType N3VQIntSL16:ResTy = ?, ValueType N3VQIntSL16:OpTy = ?, SDPatternOperator N3VQIntSL16:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, N3VQIntSL16:op21_20{1}, N3VQIntSL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQIntSL16:op11_8{3}, N3VQIntSL16:op11_8{2}, N3VQIntSL16:op11_8{1}, N3VQIntSL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VQIntSL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQIntSL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VQIntSL16:ResTy QPR:$Vd), (N3VQIntSL16:ResTy (N3VQIntSL16:IntOp (N3VQIntSL16:ResTy QPR:$Vn), (N3VQIntSL16:ResTy (NEONvduplane (N3VQIntSL16:OpTy DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQIntSL16:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VQIntSh<bit N3VQIntSh:op24 = ?, bit N3VQIntSh:op23 = ?, bits<2> N3VQIntSh:op21_20 = { ?, ? }, bits<4> N3VQIntSh:op11_8 = { ?, ?, ?, ? }, bit N3VQIntSh:op4 = ?, Format N3VQIntSh:f = ?, InstrItinClass N3VQIntSh:itin = ?, string N3VQIntSh:OpcodeStr = ?, string N3VQIntSh:Dt = ?, ValueType N3VQIntSh:ResTy = ?, ValueType N3VQIntSh:OpTy = ?, SDPatternOperator N3VQIntSh:IntOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VQIntSh:op24, N3VQIntSh:op23, Vd{4}, N3VQIntSh:op21_20{1}, N3VQIntSh:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQIntSh:op11_8{3}, N3VQIntSh:op11_8{2}, N3VQIntSh:op11_8{1}, N3VQIntSh:op11_8{0}, Vn{4}, 1, Vm{4}, N3VQIntSh:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = !strconcat(N3VQIntSh:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQIntSh:Dt, "	$Vd, $Vm, $Vn"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VQIntSh:ResTy (N3VQIntSh:IntOp (N3VQIntSh:OpTy QPR:$Vm), (N3VQIntSh:OpTy QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VQIntSh:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQIntSh:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VQIntSh:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VQIntnp<bits<5> N3VQIntnp:op27_23 = { ?, ?, ?, ?, ? }, bits<2> N3VQIntnp:op21_20 = { ?, ? }, bits<4> N3VQIntnp:op11_8 = { ?, ?, ?, ? }, bit N3VQIntnp:op6 = ?, bit N3VQIntnp:op4 = ?, Format N3VQIntnp:f = ?, InstrItinClass N3VQIntnp:itin = ?, string N3VQIntnp:OpcodeStr = ?, string N3VQIntnp:Dt = ?, ValueType N3VQIntnp:ResTy = ?, ValueType N3VQIntnp:OpTy = ?, SDPatternOperator N3VQIntnp:IntOp = ?, bit N3VQIntnp:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp
  field bits<32> Inst = { 1, 1, 1, 1, N3VQIntnp:op27_23{4}, N3VQIntnp:op27_23{3}, N3VQIntnp:op27_23{2}, N3VQIntnp:op27_23{1}, N3VQIntnp:op27_23{0}, Vd{4}, N3VQIntnp:op21_20{1}, N3VQIntnp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQIntnp:op11_8{3}, N3VQIntnp:op11_8{2}, N3VQIntnp:op11_8{1}, N3VQIntnp:op11_8{0}, Vn{4}, N3VQIntnp:op6, Vm{4}, N3VQIntnp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm);
  string AsmString = !strconcat(N3VQIntnp:OpcodeStr, !strconcat(".", !strconcat(N3VQIntnp:Dt, "	$Vd, $Vn, $Vm")));
  list<dag> Pattern = [(set QPR:$Vd, (N3VQIntnp:ResTy (N3VQIntnp:IntOp (N3VQIntnp:OpTy QPR:$Vn), (N3VQIntnp:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VQIntnp:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQIntnp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VQIntnp:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VQMulOp<bit N3VQMulOp:op24 = ?, bit N3VQMulOp:op23 = ?, bits<2> N3VQMulOp:op21_20 = { ?, ? }, bits<4> N3VQMulOp:op11_8 = { ?, ?, ?, ? }, bit N3VQMulOp:op4 = ?, InstrItinClass N3VQMulOp:itin = ?, string N3VQMulOp:OpcodeStr = ?, string N3VQMulOp:Dt = ?, ValueType N3VQMulOp:Ty = ?, SDPatternOperator N3VQMulOp:MulOp = ?, SDPatternOperator N3VQMulOp:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VQMulOp:op24, N3VQMulOp:op23, Vd{4}, N3VQMulOp:op21_20{1}, N3VQMulOp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQMulOp:op11_8{3}, N3VQMulOp:op11_8{2}, N3VQMulOp:op11_8{1}, N3VQMulOp:op11_8{0}, Vn{4}, 1, Vm{4}, N3VQMulOp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VQMulOp:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQMulOp:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VQMulOp:Ty (N3VQMulOp:OpNode QPR:$src1, (N3VQMulOp:Ty (N3VQMulOp:MulOp QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQMulOp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VQMulOpSL<bits<2> N3VQMulOpSL:op21_20 = { ?, ? }, bits<4> N3VQMulOpSL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VQMulOpSL:itin = ?, string N3VQMulOpSL:OpcodeStr = ?, string N3VQMulOpSL:Dt = ?, ValueType N3VQMulOpSL:ResTy = ?, ValueType N3VQMulOpSL:OpTy = ?, SDPatternOperator N3VQMulOpSL:MulOp = ?, SDPatternOperator N3VQMulOpSL:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, N3VQMulOpSL:op21_20{1}, N3VQMulOpSL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQMulOpSL:op11_8{3}, N3VQMulOpSL:op11_8{2}, N3VQMulOpSL:op11_8{1}, N3VQMulOpSL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VQMulOpSL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQMulOpSL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VQMulOpSL:ResTy QPR:$Vd), (N3VQMulOpSL:ResTy (N3VQMulOpSL:ShOp (N3VQMulOpSL:ResTy QPR:$src1), (N3VQMulOpSL:ResTy (N3VQMulOpSL:MulOp QPR:$Vn, (N3VQMulOpSL:ResTy (NEONvduplane (N3VQMulOpSL:OpTy DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQMulOpSL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VQMulOpSL16<bits<2> N3VQMulOpSL16:op21_20 = { ?, ? }, bits<4> N3VQMulOpSL16:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VQMulOpSL16:itin = ?, string N3VQMulOpSL16:OpcodeStr = ?, string N3VQMulOpSL16:Dt = ?, ValueType N3VQMulOpSL16:ResTy = ?, ValueType N3VQMulOpSL16:OpTy = ?, SDPatternOperator N3VQMulOpSL16:MulOp = ?, SDPatternOperator N3VQMulOpSL16:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, N3VQMulOpSL16:op21_20{1}, N3VQMulOpSL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQMulOpSL16:op11_8{3}, N3VQMulOpSL16:op11_8{2}, N3VQMulOpSL16:op11_8{1}, N3VQMulOpSL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VQMulOpSL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQMulOpSL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VQMulOpSL16:ResTy QPR:$Vd), (N3VQMulOpSL16:ResTy (N3VQMulOpSL16:ShOp (N3VQMulOpSL16:ResTy QPR:$src1), (N3VQMulOpSL16:ResTy (N3VQMulOpSL16:MulOp QPR:$Vn, (N3VQMulOpSL16:ResTy (NEONvduplane (N3VQMulOpSL16:OpTy DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQMulOpSL16:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VQSL<bits<2> N3VQSL:op21_20 = { ?, ? }, bits<4> N3VQSL:op11_8 = { ?, ?, ?, ? }, InstrItinClass N3VQSL:itin = ?, string N3VQSL:OpcodeStr = ?, string N3VQSL:Dt = ?, ValueType N3VQSL:ResTy = ?, ValueType N3VQSL:OpTy = ?, SDNode N3VQSL:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, N3VQSL:op21_20{1}, N3VQSL:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQSL:op11_8{3}, N3VQSL:op11_8{2}, N3VQSL:op11_8{1}, N3VQSL:op11_8{0}, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = !strconcat(N3VQSL:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQSL:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VQSL:ResTy QPR:$Vd), (N3VQSL:ResTy (N3VQSL:ShOp (N3VQSL:ResTy QPR:$Vn), (N3VQSL:ResTy (NEONvduplane (N3VQSL:OpTy DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQSL:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
class N3VQSL16<bits<2> N3VQSL16:op21_20 = { ?, ? }, bits<4> N3VQSL16:op11_8 = { ?, ?, ?, ? }, string N3VQSL16:OpcodeStr = ?, string N3VQSL16:Dt = ?, ValueType N3VQSL16:ResTy = ?, ValueType N3VQSL16:OpTy = ?, SDNode N3VQSL16:ShOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, N3VQSL16:op21_20{1}, N3VQSL16:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQSL16:op11_8{3}, N3VQSL16:op11_8{2}, N3VQSL16:op11_8{1}, N3VQSL16:op11_8{0}, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = !strconcat(N3VQSL16:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VQSL16:Dt, "	$Vd, $Vn, $Vm$lane"))));
  list<dag> Pattern = [(set (N3VQSL16:ResTy QPR:$Vd), (N3VQSL16:ResTy (N3VQSL16:ShOp (N3VQSL16:ResTy QPR:$Vn), (N3VQSL16:ResTy (NEONvduplane (N3VQSL16:OpTy DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVMulSLFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
class N3VQX<bit N3VQX:op24 = ?, bit N3VQX:op23 = ?, bits<2> N3VQX:op21_20 = { ?, ? }, bits<4> N3VQX:op11_8 = { ?, ?, ?, ? }, bit N3VQX:op4 = ?, InstrItinClass N3VQX:itin = ?, string N3VQX:OpcodeStr = ?, ValueType N3VQX:ResTy = ?, ValueType N3VQX:OpTy = ?, SDNode N3VQX:OpNode = ?, bit N3VQX:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VQX:op24, N3VQX:op23, Vd{4}, N3VQX:op21_20{1}, N3VQX:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VQX:op11_8{3}, N3VQX:op11_8{2}, N3VQX:op11_8{1}, N3VQX:op11_8{0}, Vn{4}, 1, Vm{4}, N3VQX:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VQX:OpcodeStr, "${p}	$Vd, $Vn, $Vm");
  list<dag> Pattern = [(set QPR:$Vd, (N3VQX:ResTy (N3VQX:OpNode (N3VQX:OpTy QPR:$Vn), (N3VQX:OpTy QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VQX:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VQX:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VSMulOpPat<SDNode N3VSMulOpPat:MulNode = ?, SDNode N3VSMulOpPat:OpNode = ?, NeonI N3VSMulOpPat:Inst = ?> {	// Pattern Pat NEONFPPat
  dag PatternToMatch = (f32 (N3VSMulOpPat:OpNode SPR:$acc, (f32 (N3VSMulOpPat:MulNode SPR:$a, SPR:$b))));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (N3VSMulOpPat:Inst (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$acc, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class N3VSPat<SDNode N3VSPat:OpNode = ?, NeonI N3VSPat:Inst = ?> {	// Pattern Pat NEONFPPat
  dag PatternToMatch = (f32 (N3VSPat:OpNode SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (N3VSPat:Inst (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class N3VSPatFP16<SDNode N3VSPatFP16:OpNode = ?, NeonI N3VSPatFP16:Inst = ?> {	// Pattern Pat NEONFPPat
  dag PatternToMatch = (f16 (N3VSPatFP16:OpNode HPR:$a, HPR:$b));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v4f16 (COPY_TO_REGCLASS (N3VSPatFP16:Inst (INSERT_SUBREG (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), HPR:$a, ssub_0), (INSERT_SUBREG (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), HPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class N3VW<bit N3VW:op24 = ?, bit N3VW:op23 = ?, bits<2> N3VW:op21_20 = { ?, ? }, bits<4> N3VW:op11_8 = { ?, ?, ?, ? }, bit N3VW:op4 = ?, string N3VW:OpcodeStr = ?, string N3VW:Dt = ?, ValueType N3VW:TyQ = ?, ValueType N3VW:TyD = ?, SDNode N3VW:OpNode = ?, SDNode N3VW:ExtOp = ?, bit N3VW:Commutable = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VW:op24, N3VW:op23, Vd{4}, N3VW:op21_20{1}, N3VW:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VW:op11_8{3}, N3VW:op11_8{2}, N3VW:op11_8{1}, N3VW:op11_8{0}, Vn{4}, 0, Vm{4}, N3VW:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = !strconcat(N3VW:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(N3VW:Dt, "	$Vd, $Vn, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (N3VW:OpNode (N3VW:TyQ QPR:$Vn), (N3VW:TyQ (N3VW:ExtOp (N3VW:TyD DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = N3VW:Commutable;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3VX<bit N3VX:op24 = ?, bit N3VX:op23 = ?, bits<2> N3VX:op21_20 = { ?, ? }, bits<4> N3VX:op11_8 = { ?, ?, ?, ? }, bit N3VX:op6 = ?, bit N3VX:op4 = ?, dag N3VX:oops = ?, dag N3VX:iops = ?, Format N3VX:f = ?, InstrItinClass N3VX:itin = ?, string N3VX:opc = ?, string N3VX:asm = ?, string N3VX:cstr = ?, list<dag> N3VX:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, N3VX:op24, N3VX:op23, Vd{4}, N3VX:op21_20{1}, N3VX:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3VX:op11_8{3}, N3VX:op11_8{2}, N3VX:op11_8{1}, N3VX:op11_8{0}, Vn{4}, N3VX:op6, Vm{4}, N3VX:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N3VX:oops;
  dag InOperandList = !con(N3VX:iops, (ins pred:$p));
  string AsmString = !strconcat(N3VX:opc, !strconcat("${p}", !strconcat("	", N3VX:asm)));
  list<dag> Pattern = N3VX:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3VX:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3VX:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = N3VX:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3VX:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class N3Vnp<bits<5> N3Vnp:op27_23 = { ?, ?, ?, ?, ? }, bits<2> N3Vnp:op21_20 = { ?, ? }, bits<4> N3Vnp:op11_8 = { ?, ?, ?, ? }, bit N3Vnp:op6 = ?, bit N3Vnp:op4 = ?, dag N3Vnp:oops = ?, dag N3Vnp:iops = ?, Format N3Vnp:f = ?, InstrItinClass N3Vnp:itin = ?, string N3Vnp:OpcodeStr = ?, string N3Vnp:Dt = ?, list<dag> N3Vnp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp
  field bits<32> Inst = { 1, 1, 1, 1, N3Vnp:op27_23{4}, N3Vnp:op27_23{3}, N3Vnp:op27_23{2}, N3Vnp:op27_23{1}, N3Vnp:op27_23{0}, Vd{4}, N3Vnp:op21_20{1}, N3Vnp:op21_20{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, N3Vnp:op11_8{3}, N3Vnp:op11_8{2}, N3Vnp:op11_8{1}, N3Vnp:op11_8{0}, Vn{4}, N3Vnp:op6, Vm{4}, N3Vnp:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = N3Vnp:oops;
  dag InOperandList = N3Vnp:iops;
  string AsmString = !strconcat(N3Vnp:OpcodeStr, !strconcat(".", !strconcat(N3Vnp:Dt, "	$Vd, $Vn, $Vm")));
  list<dag> Pattern = N3Vnp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(N3Vnp:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = N3Vnp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3Vnp:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class NDataI<dag NDataI:oops = ?, dag NDataI:iops = ?, Format NDataI:f = ?, InstrItinClass NDataI:itin = ?, string NDataI:opc = ?, string NDataI:dt = ?, string NDataI:asm = ?, string NDataI:cstr = ?, list<dag> NDataI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NDataI:oops;
  dag InOperandList = !con(NDataI:iops, (ins pred:$p));
  string AsmString = !strconcat(NDataI:opc, !strconcat("${p}", !strconcat(".", !strconcat(NDataI:dt, !strconcat("	", NDataI:asm)))));
  list<dag> Pattern = NDataI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(NDataI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NDataI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = NDataI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NDataI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class NDataXI<dag NDataXI:oops = ?, dag NDataXI:iops = ?, Format NDataXI:f = ?, InstrItinClass NDataXI:itin = ?, string NDataXI:opc = ?, string NDataXI:asm = ?, string NDataXI:cstr = ?, list<dag> NDataXI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonXI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NDataXI:oops;
  dag InOperandList = !con(NDataXI:iops, (ins pred:$p));
  string AsmString = !strconcat(NDataXI:opc, !strconcat("${p}", !strconcat("	", NDataXI:asm)));
  list<dag> Pattern = NDataXI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(NDataXI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NDataXI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = NDataXI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NDataXI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class NEONAsmPseudo<string NEONAsmPseudo:asm = ?, dag NEONAsmPseudo:iops = ?, dag NEONAsmPseudo:oops = (outs)> {	// Instruction InstTemplate AsmPseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = NEONAsmPseudo:oops;
  dag InOperandList = NEONAsmPseudo:iops;
  string AsmString = NEONAsmPseudo:asm;
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class NEONDataTypeAsmPseudoInst<string NEONDataTypeAsmPseudoInst:opc = ?, string NEONDataTypeAsmPseudoInst:dt = ?, string NEONDataTypeAsmPseudoInst:asm = ?, dag NEONDataTypeAsmPseudoInst:iops = ?> {	// Instruction InstTemplate AsmPseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = NEONDataTypeAsmPseudoInst:iops;
  string AsmString = !strconcat(NEONDataTypeAsmPseudoInst:opc, !strconcat(NEONDataTypeAsmPseudoInst:dt, !strconcat("	", NEONDataTypeAsmPseudoInst:asm)));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class NEONFPPat<dag NEONFPPat:pattern = ?, dag NEONFPPat:result = ?> {	// Pattern Pat
  dag PatternToMatch = NEONFPPat:pattern;
  list<dag> ResultInstrs = [NEONFPPat:result];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class NEONInstAlias<string NEONInstAlias:Asm = ?, dag NEONInstAlias:Result = ?, bit NEONInstAlias:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = NEONInstAlias:Asm;
  dag ResultInst = NEONInstAlias:Result;
  int EmitPriority = !cast<int>(NEONInstAlias:EmitPriority);
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class NEONMnemonicAlias<string NEONMnemonicAlias:src = ?, string NEONMnemonicAlias:dst = ?> {	// MnemonicAlias Requires
  string FromMnemonic = NEONMnemonicAlias:src;
  string ToMnemonic = NEONMnemonicAlias:dst;
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
class NLdSt<bit NLdSt:op23 = ?, bits<2> NLdSt:op21_20 = { ?, ? }, bits<4> NLdSt:op11_8 = { ?, ?, ?, ? }, bits<4> NLdSt:op7_4 = { ?, ?, ?, ? }, dag NLdSt:oops = ?, dag NLdSt:iops = ?, InstrItinClass NLdSt:itin = ?, string NLdSt:opc = ?, string NLdSt:dt = ?, string NLdSt:asm = ?, string NLdSt:cstr = ?, list<dag> NLdSt:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, NLdSt:op23, Vd{4}, NLdSt:op21_20{1}, NLdSt:op21_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, NLdSt:op11_8{3}, NLdSt:op11_8{2}, NLdSt:op11_8{1}, NLdSt:op11_8{0}, NLdSt:op7_4{3}, NLdSt:op7_4{2}, NLdSt:op7_4{1}, NLdSt:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NLdSt:oops;
  dag InOperandList = !con(NLdSt:iops, (ins pred:$p));
  string AsmString = !strconcat(NLdSt:opc, !strconcat("${p}", !strconcat(".", !strconcat(NLdSt:dt, !strconcat("	", NLdSt:asm)))));
  list<dag> Pattern = NLdSt:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NLdSt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = NLdSt:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class NLdStLn<bit NLdStLn:op23 = ?, bits<2> NLdStLn:op21_20 = { ?, ? }, bits<4> NLdStLn:op11_8 = { ?, ?, ?, ? }, bits<4> NLdStLn:op7_4 = { ?, ?, ?, ? }, dag NLdStLn:oops = ?, dag NLdStLn:iops = ?, InstrItinClass NLdStLn:itin = ?, string NLdStLn:opc = ?, string NLdStLn:dt = ?, string NLdStLn:asm = ?, string NLdStLn:cstr = ?, list<dag> NLdStLn:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, NLdStLn:op23, Vd{4}, NLdStLn:op21_20{1}, NLdStLn:op21_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, NLdStLn:op11_8{3}, NLdStLn:op11_8{2}, NLdStLn:op11_8{1}, NLdStLn:op11_8{0}, NLdStLn:op7_4{3}, NLdStLn:op7_4{2}, NLdStLn:op7_4{1}, NLdStLn:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NLdStLn:oops;
  dag InOperandList = !con(NLdStLn:iops, (ins pred:$p));
  string AsmString = !strconcat(NLdStLn:opc, !strconcat("${p}", !strconcat(".", !strconcat(NLdStLn:dt, !strconcat("	", NLdStLn:asm)))));
  list<dag> Pattern = NLdStLn:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NLdStLn:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = NLdStLn:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class NVCVTFIPat<SDNode NVCVTFIPat:OpNode = ?, NeonI NVCVTFIPat:Inst = ?> {	// Pattern Pat NEONFPPat
  dag PatternToMatch = (i32 (NVCVTFIPat:OpNode SPR:$a));
  list<dag> ResultInstrs = [(i32 (EXTRACT_SUBREG (v2f32 (NVCVTFIPat:Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, ssub_0))), ssub_0))];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class NVCVTIFPat<SDNode NVCVTIFPat:OpNode = ?, NeonI NVCVTIFPat:Inst = ?> {	// Pattern Pat NEONFPPat
  dag PatternToMatch = (f32 (NVCVTIFPat:OpNode GPR:$a));
  list<dag> ResultInstrs = [(f32 (EXTRACT_SUBREG (v2f32 (NVCVTIFPat:Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (i32 (COPY_TO_REGCLASS GPR:$a, SPR)), ssub_0))), ssub_0))];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class NVDup<bits<8> NVDup:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> NVDup:opcod2 = { ?, ?, ?, ? }, bits<2> NVDup:opcod3 = { ?, ? }, dag NVDup:oops = ?, dag NVDup:iops = ?, InstrItinClass NVDup:itin = ?, string NVDup:opc = ?, string NVDup:dt = ?, string NVDup:asm = ?, list<dag> NVDup:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NVLaneOp
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, NVDup:opcod1{7}, NVDup:opcod1{6}, NVDup:opcod1{5}, NVDup:opcod1{4}, NVDup:opcod1{3}, NVDup:opcod1{2}, NVDup:opcod1{1}, NVDup:opcod1{0}, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, NVDup:opcod2{3}, NVDup:opcod2{2}, NVDup:opcod2{1}, NVDup:opcod2{0}, V{4}, NVDup:opcod3{1}, NVDup:opcod3{0}, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NVDup:oops;
  dag InOperandList = !con(NVDup:iops, (ins pred:$p));
  string AsmString = !strconcat(NVDup:opc, !strconcat("${p}", !strconcat(".", !strconcat(NVDup:dt, !strconcat("	", NVDup:asm)))));
  list<dag> Pattern = NVDup:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NVDup:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NDupFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
class NVDupLane<bits<4> NVDupLane:op19_16 = { ?, ?, ?, ? }, bit NVDupLane:op6 = ?, dag NVDupLane:oops = ?, dag NVDupLane:iops = ?, InstrItinClass NVDupLane:itin = ?, string NVDupLane:opc = ?, string NVDupLane:dt = ?, string NVDupLane:asm = ?, list<dag> NVDupLane:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, NVDupLane:op19_16{3}, NVDupLane:op19_16{2}, NVDupLane:op19_16{1}, NVDupLane:op19_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, NVDupLane:op6, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NVDupLane:oops;
  dag InOperandList = !con(NVDupLane:iops, (ins pred:$p));
  string AsmString = !strconcat(NVDupLane:opc, !strconcat("${p}", !strconcat(".", !strconcat(NVDupLane:dt, !strconcat("	", NVDupLane:asm)))));
  list<dag> Pattern = NVDupLane:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NVDupLane:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVDupLnFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class NVGetLane<bits<8> NVGetLane:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> NVGetLane:opcod2 = { ?, ?, ?, ? }, bits<2> NVGetLane:opcod3 = { ?, ? }, dag NVGetLane:oops = ?, dag NVGetLane:iops = ?, InstrItinClass NVGetLane:itin = ?, string NVGetLane:opc = ?, string NVGetLane:dt = ?, string NVGetLane:asm = ?, list<dag> NVGetLane:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NVLaneOp
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, NVGetLane:opcod1{7}, NVGetLane:opcod1{6}, NVGetLane:opcod1{5}, NVGetLane:opcod1{4}, NVGetLane:opcod1{3}, NVGetLane:opcod1{2}, NVGetLane:opcod1{1}, NVGetLane:opcod1{0}, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, NVGetLane:opcod2{3}, NVGetLane:opcod2{2}, NVGetLane:opcod2{1}, NVGetLane:opcod2{0}, V{4}, NVGetLane:opcod3{1}, NVGetLane:opcod3{0}, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NVGetLane:oops;
  dag InOperandList = !con(NVGetLane:iops, (ins pred:$p));
  string AsmString = !strconcat(NVGetLane:opc, !strconcat("${p}", !strconcat(".", !strconcat(NVGetLane:dt, !strconcat("	", NVGetLane:asm)))));
  list<dag> Pattern = NVGetLane:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NVGetLane:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NGetLnFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
class NVLaneOp<bits<8> NVLaneOp:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> NVLaneOp:opcod2 = { ?, ?, ?, ? }, bits<2> NVLaneOp:opcod3 = { ?, ? }, dag NVLaneOp:oops = ?, dag NVLaneOp:iops = ?, Format NVLaneOp:f = ?, InstrItinClass NVLaneOp:itin = ?, string NVLaneOp:opc = ?, string NVLaneOp:dt = ?, string NVLaneOp:asm = ?, list<dag> NVLaneOp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, NVLaneOp:opcod1{7}, NVLaneOp:opcod1{6}, NVLaneOp:opcod1{5}, NVLaneOp:opcod1{4}, NVLaneOp:opcod1{3}, NVLaneOp:opcod1{2}, NVLaneOp:opcod1{1}, NVLaneOp:opcod1{0}, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, NVLaneOp:opcod2{3}, NVLaneOp:opcod2{2}, NVLaneOp:opcod2{1}, NVLaneOp:opcod2{0}, V{4}, NVLaneOp:opcod3{1}, NVLaneOp:opcod3{0}, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NVLaneOp:oops;
  dag InOperandList = !con(NVLaneOp:iops, (ins pred:$p));
  string AsmString = !strconcat(NVLaneOp:opc, !strconcat("${p}", !strconcat(".", !strconcat(NVLaneOp:dt, !strconcat("	", NVLaneOp:asm)))));
  list<dag> Pattern = NVLaneOp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(NVLaneOp:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NVLaneOp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVLaneOp:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
class NVSetLane<bits<8> NVSetLane:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<4> NVSetLane:opcod2 = { ?, ?, ?, ? }, bits<2> NVSetLane:opcod3 = { ?, ? }, dag NVSetLane:oops = ?, dag NVSetLane:iops = ?, InstrItinClass NVSetLane:itin = ?, string NVSetLane:opc = ?, string NVSetLane:dt = ?, string NVSetLane:asm = ?, list<dag> NVSetLane:pattern = ?> {	// Instruction InstTemplate Encoding InstARM NVLaneOp
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, NVSetLane:opcod1{7}, NVSetLane:opcod1{6}, NVSetLane:opcod1{5}, NVSetLane:opcod1{4}, NVSetLane:opcod1{3}, NVSetLane:opcod1{2}, NVSetLane:opcod1{1}, NVSetLane:opcod1{0}, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, NVSetLane:opcod2{3}, NVSetLane:opcod2{2}, NVSetLane:opcod2{1}, NVSetLane:opcod2{0}, V{4}, NVSetLane:opcod3{1}, NVSetLane:opcod3{0}, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NVSetLane:oops;
  dag InOperandList = !con(NVSetLane:iops, (ins pred:$p));
  string AsmString = !strconcat(NVSetLane:opc, !strconcat("${p}", !strconcat(".", !strconcat(NVSetLane:dt, !strconcat("	", NVSetLane:asm)))));
  list<dag> Pattern = NVSetLane:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NVSetLane:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NSetLnFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
class NVVM_WMMA_LD_GALSTS<string NVVM_WMMA_LD_GALSTS:Geometry = ?, string NVVM_WMMA_LD_GALSTS:Abc = ?, string NVVM_WMMA_LD_GALSTS:Layout = ?, string NVVM_WMMA_LD_GALSTS:Type = ?, LLVMType NVVM_WMMA_LD_GALSTS:regty = ?, int NVVM_WMMA_LD_GALSTS:WithStride = ?> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = !strconcat("llvm.nvvm.wmma.", !strconcat(NVVM_WMMA_LD_GALSTS:Geometry, !strconcat(".load", !strconcat(".", !strconcat(NVVM_WMMA_LD_GALSTS:Abc, !strconcat(".", !strconcat(NVVM_WMMA_LD_GALSTS:Layout, !strconcat(!if(NVVM_WMMA_LD_GALSTS:WithStride, ".stride", ""), !strconcat(".", NVVM_WMMA_LD_GALSTS:Type)))))))));
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = !if(!eq(!strconcat(NVVM_WMMA_LD_GALSTS:Abc, NVVM_WMMA_LD_GALSTS:Type), "cf16"), [NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty], [NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty, NVVM_WMMA_LD_GALSTS:regty]);
  list<LLVMType> ParamTypes = !if(NVVM_WMMA_LD_GALSTS:WithStride, [llvm_anyptr_ty, llvm_i32_ty], [llvm_anyptr_ty]);
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
class NVVM_WMMA_MMA_GABDCS<string NVVM_WMMA_MMA_GABDCS:Geometry = ?, string NVVM_WMMA_MMA_GABDCS:ALayout = ?, string NVVM_WMMA_MMA_GABDCS:BLayout = ?, string NVVM_WMMA_MMA_GABDCS:DType = ?, LLVMType NVVM_WMMA_MMA_GABDCS:d_regty = ?, string NVVM_WMMA_MMA_GABDCS:CType = ?, LLVMType NVVM_WMMA_MMA_GABDCS:c_regty = ?, string NVVM_WMMA_MMA_GABDCS:Satfinite = ""> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = !strconcat("llvm.nvvm.wmma.", !strconcat(NVVM_WMMA_MMA_GABDCS:Geometry, !strconcat(".mma", !strconcat(".", !strconcat(NVVM_WMMA_MMA_GABDCS:ALayout, !strconcat(".", !strconcat(NVVM_WMMA_MMA_GABDCS:BLayout, !strconcat(".", !strconcat(NVVM_WMMA_MMA_GABDCS:DType, !strconcat(".", !strconcat(NVVM_WMMA_MMA_GABDCS:CType, NVVM_WMMA_MMA_GABDCS:Satfinite)))))))))));
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = !if(!eq(NVVM_WMMA_MMA_GABDCS:DType, "f16"), [NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty], [NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty, NVVM_WMMA_MMA_GABDCS:d_regty]);
  list<LLVMType> ParamTypes = !listconcat([llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty], !if(!eq(NVVM_WMMA_MMA_GABDCS:CType, "f16"), [NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty], [NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty, NVVM_WMMA_MMA_GABDCS:c_regty]));
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class NVVM_WMMA_STD_GLSTS<string NVVM_WMMA_STD_GLSTS:Geometry = ?, string NVVM_WMMA_STD_GLSTS:Layout = ?, string NVVM_WMMA_STD_GLSTS:Type = ?, LLVMType NVVM_WMMA_STD_GLSTS:regty = ?, int NVVM_WMMA_STD_GLSTS:WithStride = ?, list<LLVMType> NVVM_WMMA_STD_GLSTS:Empty = []> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = !strconcat("llvm.nvvm.wmma.", !strconcat(NVVM_WMMA_STD_GLSTS:Geometry, !strconcat(".store.d", !strconcat(".", !strconcat(NVVM_WMMA_STD_GLSTS:Layout, !strconcat(!if(NVVM_WMMA_STD_GLSTS:WithStride, ".stride", ""), !strconcat(".", NVVM_WMMA_STD_GLSTS:Type)))))));
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = !listconcat([llvm_anyptr_ty], !listconcat(!if(!eq(NVVM_WMMA_STD_GLSTS:Type, "f16"), [NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty], [NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty, NVVM_WMMA_STD_GLSTS:regty]), !if(NVVM_WMMA_STD_GLSTS:WithStride, [llvm_i32_ty], NVVM_WMMA_STD_GLSTS:Empty)));
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
class NeonI<dag NeonI:oops = ?, dag NeonI:iops = ?, AddrMode NeonI:am = ?, IndexMode NeonI:im = ?, Format NeonI:f = ?, InstrItinClass NeonI:itin = ?, string NeonI:opc = ?, string NeonI:dt = ?, string NeonI:asm = ?, string NeonI:cstr = ?, list<dag> NeonI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NeonI:oops;
  dag InOperandList = !con(NeonI:iops, (ins pred:$p));
  string AsmString = !strconcat(NeonI:opc, !strconcat("${p}", !strconcat(".", !strconcat(NeonI:dt, !strconcat("	", NeonI:asm)))));
  list<dag> Pattern = NeonI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(NeonI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NeonI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = NeonI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = NeonI:am;
  IndexMode IM = NeonI:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NeonI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class NeonInp<dag NeonInp:oops = ?, dag NeonInp:iops = ?, AddrMode NeonInp:am = ?, IndexMode NeonInp:im = ?, Format NeonInp:f = ?, InstrItinClass NeonInp:itin = ?, string NeonInp:opc = ?, string NeonInp:dt = ?, string NeonInp:asm = ?, string NeonInp:cstr = ?, list<dag> NeonInp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { 1, 1, 1, 1, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NeonInp:oops;
  dag InOperandList = NeonInp:iops;
  string AsmString = !strconcat(NeonInp:opc, !strconcat(".", !strconcat(NeonInp:dt, !strconcat("	", NeonInp:asm))));
  list<dag> Pattern = NeonInp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(NeonInp:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NeonInp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = NeonInp:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = NeonInp:am;
  IndexMode IM = NeonInp:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NeonInp:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class NeonXI<dag NeonXI:oops = ?, dag NeonXI:iops = ?, AddrMode NeonXI:am = ?, IndexMode NeonXI:im = ?, Format NeonXI:f = ?, InstrItinClass NeonXI:itin = ?, string NeonXI:opc = ?, string NeonXI:asm = ?, string NeonXI:cstr = ?, list<dag> NeonXI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = NeonXI:oops;
  dag InOperandList = !con(NeonXI:iops, (ins pred:$p));
  string AsmString = !strconcat(NeonXI:opc, !strconcat("${p}", !strconcat("	", NeonXI:asm)));
  list<dag> Pattern = NeonXI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(NeonXI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NeonXI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = NeonXI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = NeonXI:am;
  IndexMode IM = NeonXI:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NeonXI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class Neon_1Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_1Arg_Narrow_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_1FloatArg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_2Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_2Arg_Long_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_2Arg_Narrow_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_3Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_3Arg_Long_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_Compare_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_CvtFPToFx_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_CvtFPtoInt_1Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_CvtFxToFP_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_Dot_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_Tbl2Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_Tbl3Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_Tbl4Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_Tbl5Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Neon_Tbl6Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class NoCapture<int NoCapture:argNo = ?> {	// IntrinsicProperty
  int ArgNo = NoCapture:argNo;
  string NAME = ?;
}
class Operand<ValueType Operand:ty = ?> {	// DAGOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = Operand:ty;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
class OperandUnsignedOffset_b8s2 {	// AsmOperandClass
  string Name = "UnsignedOffset_b8s2";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isUnsignedOffset<8, 2>";
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
class OperandWithDefaultOps<ValueType OperandWithDefaultOps:ty = ?, dag OperandWithDefaultOps:defaultops = ?> {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = OperandWithDefaultOps:ty;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  dag DefaultOps = OperandWithDefaultOps:defaultops;
  string NAME = ?;
}
class OptionalDefOperand<ValueType OptionalDefOperand:ty = ?, dag OptionalDefOperand:OpTypes = ?, dag OptionalDefOperand:defaultops = ?> {	// DAGOperand Operand OperandWithDefaultOps
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = OptionalDefOperand:ty;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = OptionalDefOperand:OpTypes;
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  dag DefaultOps = OptionalDefOperand:defaultops;
  string NAME = ?;
}
class OutPatFrag<dag OutPatFrag:ops = ?, dag OutPatFrag:frag = ?> {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = OutPatFrag:ops;
  dag Fragment = OutPatFrag:frag;
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
class PTXReadSRegIntrinsic_r32<string PTXReadSRegIntrinsic_r32:name = ?> {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = !strconcat("__nvvm_read_ptx_sreg_", PTXReadSRegIntrinsic_r32:name);
  string NAME = ?;
}
class PTXReadSRegIntrinsic_r64<string PTXReadSRegIntrinsic_r64:name = ?> {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = !strconcat("__nvvm_read_ptx_sreg_", PTXReadSRegIntrinsic_r64:name);
  string NAME = ?;
}
class Pat<dag Pat:pattern = ?, dag Pat:result = ?> {	// Pattern
  dag PatternToMatch = Pat:pattern;
  list<dag> ResultInstrs = [Pat:result];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
class PatFrag<dag PatFrag:ops = ?, dag PatFrag:frag = ?, code PatFrag:pred = [{}], SDNodeXForm PatFrag:xform = NOOP_SDNodeXForm> {	// SDPatternOperator
  list<SDNodeProperty> Properties = [];
  dag Operands = PatFrag:ops;
  dag Fragment = PatFrag:frag;
  code PredicateCode = PatFrag:pred;
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = PatFrag:xform;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
class PatLeaf<dag PatLeaf:frag = ?, code PatLeaf:pred = [{}], SDNodeXForm PatLeaf:xform = NOOP_SDNodeXForm> {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = PatLeaf:frag;
  code PredicateCode = PatLeaf:pred;
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = PatLeaf:xform;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
class PatPred {
  string NAME = ?;
}
class Pattern<dag Pattern:patternToMatch = ?, list<dag> Pattern:resultInstrs = ?> {
  dag PatternToMatch = Pattern:patternToMatch;
  list<dag> ResultInstrs = Pattern:resultInstrs;
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
class PfmCounter {
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class PfmCycleCounter<string PfmCycleCounter:counter = ?> {	// PfmCounter
  SchedMachineModel SchedModel = ?;
  string Counter = PfmCycleCounter:counter;
  string NAME = ?;
}
class PfmIssueCounter<ProcResourceUnits PfmIssueCounter:resource = ?, list<string> PfmIssueCounter:counters = ?> {	// PfmCounter
  SchedMachineModel SchedModel = ?;
  ProcResourceUnits Resource = PfmIssueCounter:resource;
  list<string> Counters = PfmIssueCounter:counters;
  string NAME = ?;
}
class PointerLikeRegClass<int PointerLikeRegClass:Kind = ?> {
  int RegClassKind = PointerLikeRegClass:Kind;
  string NAME = ?;
}
class PowerPC_QPX_FFFF_Intrinsic<string PowerPC_QPX_FFFF_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_qpx_", PowerPC_QPX_FFFF_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_QPX_FFF_Intrinsic<string PowerPC_QPX_FFF_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_qpx_", PowerPC_QPX_FFF_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_QPX_FF_Intrinsic<string PowerPC_QPX_FF_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_qpx_", PowerPC_QPX_FF_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_QPX_Intrinsic<string PowerPC_QPX_Intrinsic:GCCIntSuffix = ?, list<LLVMType> PowerPC_QPX_Intrinsic:ret_types = ?, list<LLVMType> PowerPC_QPX_Intrinsic:param_types = ?, list<IntrinsicProperty> PowerPC_QPX_Intrinsic:properties = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_qpx_", PowerPC_QPX_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = PowerPC_QPX_Intrinsic:ret_types;
  list<LLVMType> ParamTypes = PowerPC_QPX_Intrinsic:param_types;
  list<IntrinsicProperty> IntrProperties = PowerPC_QPX_Intrinsic:properties;
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_QPX_LoadPerm_Intrinsic<string PowerPC_QPX_LoadPerm_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_qpx_", PowerPC_QPX_LoadPerm_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_QPX_Load_Intrinsic<string PowerPC_QPX_Load_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_qpx_", PowerPC_QPX_Load_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_QPX_Store_Intrinsic<string PowerPC_QPX_Store_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_qpx_", PowerPC_QPX_Store_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_VSX_Intrinsic<string PowerPC_VSX_Intrinsic:GCCIntSuffix = ?, list<LLVMType> PowerPC_VSX_Intrinsic:ret_types = ?, list<LLVMType> PowerPC_VSX_Intrinsic:param_types = ?, list<IntrinsicProperty> PowerPC_VSX_Intrinsic:properties = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_vsx_", PowerPC_VSX_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = PowerPC_VSX_Intrinsic:ret_types;
  list<LLVMType> ParamTypes = PowerPC_VSX_Intrinsic:param_types;
  list<IntrinsicProperty> IntrProperties = PowerPC_VSX_Intrinsic:properties;
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_VSX_Sca_DDD_Intrinsic<string PowerPC_VSX_Sca_DDD_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_vsx_", PowerPC_VSX_Sca_DDD_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_VSX_Vec_DDD_Intrinsic<string PowerPC_VSX_Vec_DDD_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_vsx_", PowerPC_VSX_Vec_DDD_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_VSX_Vec_FFF_Intrinsic<string PowerPC_VSX_Vec_FFF_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_vsx_", PowerPC_VSX_Vec_FFF_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_Vec_BBB_Intrinsic<string PowerPC_Vec_BBB_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_altivec_", PowerPC_Vec_BBB_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_Vec_DDD_Intrinsic<string PowerPC_Vec_DDD_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_altivec_", PowerPC_Vec_DDD_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_Vec_FFF_Intrinsic<string PowerPC_Vec_FFF_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_altivec_", PowerPC_Vec_FFF_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_Vec_FF_Intrinsic<string PowerPC_Vec_FF_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_altivec_", PowerPC_Vec_FF_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_Vec_HHH_Intrinsic<string PowerPC_Vec_HHH_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_altivec_", PowerPC_Vec_HHH_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_Vec_Intrinsic<string PowerPC_Vec_Intrinsic:GCCIntSuffix = ?, list<LLVMType> PowerPC_Vec_Intrinsic:ret_types = ?, list<LLVMType> PowerPC_Vec_Intrinsic:param_types = ?, list<IntrinsicProperty> PowerPC_Vec_Intrinsic:properties = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_altivec_", PowerPC_Vec_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = PowerPC_Vec_Intrinsic:ret_types;
  list<LLVMType> ParamTypes = PowerPC_Vec_Intrinsic:param_types;
  list<IntrinsicProperty> IntrProperties = PowerPC_Vec_Intrinsic:properties;
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_Vec_QQQ_Intrinsic<string PowerPC_Vec_QQQ_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_altivec_", PowerPC_Vec_QQQ_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v1i128_ty];
  list<LLVMType> ParamTypes = [llvm_v1i128_ty, llvm_v1i128_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class PowerPC_Vec_WWW_Intrinsic<string PowerPC_Vec_WWW_Intrinsic:GCCIntSuffix = ?> {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_altivec_", PowerPC_Vec_WWW_Intrinsic:GCCIntSuffix);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class Predicate<string Predicate:cond = ?> {
  string CondString = Predicate:cond;
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
class PredicateOp {
  string NAME = ?;
}
class PredicateOperand<ValueType PredicateOperand:ty = ?, dag PredicateOperand:OpTypes = ?, dag PredicateOperand:AlwaysVal = ?> {	// DAGOperand Operand OperandWithDefaultOps PredicateOp
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = PredicateOperand:ty;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = PredicateOperand:OpTypes;
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  dag DefaultOps = PredicateOperand:AlwaysVal;
  string NAME = ?;
}
class PredicateProlog<code PredicateProlog:c = ?> {
  code Code = PredicateProlog:c;
  string NAME = ?;
}
class ProcNoItin<string ProcNoItin:Name = ?, list<SubtargetFeature> ProcNoItin:Features = ?> {	// Processor
  string Name = ProcNoItin:Name;
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = ProcNoItin:Features;
  string NAME = ?;
}
class ProcReadAdvance<int ProcReadAdvance:cycles = ?, list<SchedWrite> ProcReadAdvance:writes = []> {
  int Cycles = ProcReadAdvance:cycles;
  list<SchedWrite> ValidWrites = ProcReadAdvance:writes;
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class ProcResGroup<list<ProcResource> ProcResGroup:resources = ?> {	// ProcResourceKind
  list<ProcResource> Resources = ProcResGroup:resources;
  SchedMachineModel SchedModel = ?;
  int BufferSize = -1;
  string NAME = ?;
}
class ProcResource<int ProcResource:num = ?, list<string> ProcResource:pfmCounters = []> {	// ProcResourceKind ProcResourceUnits
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = ProcResource:num;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class ProcResourceKind {
  string NAME = ?;
}
class ProcResourceUnits<ProcResourceKind ProcResourceUnits:kind = ?, int ProcResourceUnits:num = ?, list<string> ProcResourceUnits:pfmCounters = ?> {
  ProcResourceKind Kind = ProcResourceUnits:kind;
  int NumUnits = ProcResourceUnits:num;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class ProcWriteResources<list<ProcResourceKind> ProcWriteResources:resources = ?> {
  list<ProcResourceKind> ProcResources = ProcWriteResources:resources;
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class Processor<string Processor:n = ?, ProcessorItineraries Processor:pi = ?, list<SubtargetFeature> Processor:f = ?> {
  string Name = Processor:n;
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = Processor:pi;
  list<SubtargetFeature> Features = Processor:f;
  string NAME = ?;
}
class ProcessorItineraries<list<FuncUnit> ProcessorItineraries:fu = ?, list<Bypass> ProcessorItineraries:bp = ?, list<InstrItinData> ProcessorItineraries:iid = ?> {
  list<FuncUnit> FU = ProcessorItineraries:fu;
  list<Bypass> BP = ProcessorItineraries:bp;
  list<InstrItinData> IID = ProcessorItineraries:iid;
  string NAME = ?;
}
class ProcessorModel<string ProcessorModel:n = ?, SchedMachineModel ProcessorModel:m = ?, list<SubtargetFeature> ProcessorModel:f = ?> {	// Processor
  string Name = ProcessorModel:n;
  SchedMachineModel SchedModel = ProcessorModel:m;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = ProcessorModel:f;
  string NAME = ?;
}
class PseudoInst<dag PseudoInst:oops = ?, dag PseudoInst:iops = ?, InstrItinClass PseudoInst:itin = ?, list<dag> PseudoInst:pattern = ?> {	// Instruction InstTemplate
  string Namespace = "ARM";
  dag OutOperandList = PseudoInst:oops;
  dag InOperandList = PseudoInst:iops;
  string AsmString = "";
  list<dag> Pattern = PseudoInst:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = PseudoInst:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class PseudoInstExpansion<dag PseudoInstExpansion:Result = ?> {
  dag ResultInst = PseudoInstExpansion:Result;
  bit isPseudo = 1;
  string NAME = ?;
}
class PseudoNLdSt<dag PseudoNLdSt:oops = ?, dag PseudoNLdSt:iops = ?, InstrItinClass PseudoNLdSt:itin = ?, string PseudoNLdSt:cstr = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = PseudoNLdSt:oops;
  dag InOperandList = !con(PseudoNLdSt:iops, (ins pred:$p));
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = PseudoNLdSt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = PseudoNLdSt:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class PseudoNeonI<dag PseudoNeonI:oops = ?, dag PseudoNeonI:iops = ?, InstrItinClass PseudoNeonI:itin = ?, string PseudoNeonI:cstr = ?, list<dag> PseudoNeonI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = PseudoNeonI:oops;
  dag InOperandList = !con(PseudoNeonI:iops, (ins pred:$p));
  string AsmString = "";
  list<dag> Pattern = PseudoNeonI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = PseudoNeonI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = PseudoNeonI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class PseudoVFPLdStM<dag PseudoVFPLdStM:oops = ?, dag PseudoVFPLdStM:iops = ?, InstrItinClass PseudoVFPLdStM:itin = ?, string PseudoVFPLdStM:cstr = ?, list<dag> PseudoVFPLdStM:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = PseudoVFPLdStM:oops;
  dag InOperandList = !con(PseudoVFPLdStM:iops, (ins pred:$p));
  string AsmString = "";
  list<dag> Pattern = PseudoVFPLdStM:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = PseudoVFPLdStM:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = PseudoVFPLdStM:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class RFEI<bit RFEI:wb = ?, string RFEI:asm = ?> {	// Instruction InstTemplate Encoding InstARM XI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, ?, ?, 0, RFEI:wb, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn);
  string AsmString = RFEI:asm;
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
class ReadAdvance<SchedRead ReadAdvance:read = ?, int ReadAdvance:cycles = ?, list<SchedWrite> ReadAdvance:writes = []> {	// ProcReadAdvance
  int Cycles = ReadAdvance:cycles;
  list<SchedWrite> ValidWrites = ReadAdvance:writes;
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  SchedRead ReadType = ReadAdvance:read;
  string NAME = ?;
}
class ReadNone<int ReadNone:argNo = ?> {	// IntrinsicProperty
  int ArgNo = ReadNone:argNo;
  string NAME = ?;
}
class ReadOnly<int ReadOnly:argNo = ?> {	// IntrinsicProperty
  int ArgNo = ReadOnly:argNo;
  string NAME = ?;
}
class RegAltNameIndex {
  string Namespace = "";
  string NAME = ?;
}
class RegConstraint<string RegConstraint:C = ?> {
  string Constraints = RegConstraint:C;
  string NAME = ?;
}
class RegInfo<int RegInfo:RS = ?, int RegInfo:SS = ?, int RegInfo:SA = ?> {
  int RegSize = RegInfo:RS;
  int SpillSize = RegInfo:SS;
  int SpillAlignment = RegInfo:SA;
  string NAME = ?;
}
class RegInfoByHwMode<list<HwMode> RegInfoByHwMode:Ms = [], list<RegInfo> RegInfoByHwMode:Ts = []> {	// HwModeSelect
  list<HwMode> Modes = RegInfoByHwMode:Ms;
  list<RegInfo> Objects = RegInfoByHwMode:Ts;
  string NAME = ?;
}
class Register<string Register:n = ?, list<string> Register:altNames = []> {
  string Namespace = "";
  string AsmName = Register:n;
  list<string> AltNames = Register:altNames;
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
class RegisterBank<string RegisterBank:name = ?, list<RegisterClass> RegisterBank:classes = ?> {
  string Name = RegisterBank:name;
  list<RegisterClass> RegisterClasses = RegisterBank:classes;
  string NAME = ?;
}
class RegisterClass<string RegisterClass:namespace = ?, list<ValueType> RegisterClass:regTypes = ?, int RegisterClass:alignment = ?, dag RegisterClass:regList = ?, RegAltNameIndex RegisterClass:idx = NoRegAltName> {	// DAGOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = RegisterClass:namespace;
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = RegisterClass:regTypes;
  int Size = 0;
  int Alignment = RegisterClass:alignment;
  int CopyCost = 1;
  dag MemberList = RegisterClass:regList;
  RegAltNameIndex altNameIndex = RegisterClass:idx;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
class RegisterFile<int RegisterFile:numPhysRegs = ?, list<RegisterClass> RegisterFile:Classes = [], list<int> RegisterFile:Costs = []> {
  list<RegisterClass> RegClasses = RegisterFile:Classes;
  list<int> RegCosts = RegisterFile:Costs;
  int NumPhysRegs = RegisterFile:numPhysRegs;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class RegisterOperand<RegisterClass RegisterOperand:regclass = ?, string RegisterOperand:pm = "printOperand"> {	// DAGOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = RegisterOperand:regclass;
  string PrintMethod = RegisterOperand:pm;
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = ?;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
class RegisterTuples<list<SubRegIndex> RegisterTuples:Indices = ?, list<dag> RegisterTuples:Regs = ?> {
  list<dag> SubRegs = RegisterTuples:Regs;
  list<SubRegIndex> SubRegIndices = RegisterTuples:Indices;
  string NAME = ?;
}
class RegisterWithSubRegs<string RegisterWithSubRegs:n = ?, list<Register> RegisterWithSubRegs:subregs = ?> {	// Register
  string Namespace = "";
  string AsmName = RegisterWithSubRegs:n;
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = RegisterWithSubRegs:subregs;
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
class Requires<list<Predicate> Requires:preds = ?> {
  list<Predicate> Predicates = Requires:preds;
  string NAME = ?;
}
class ReservationKind<bits<1> ReservationKind:val = { ? }> {
  int Value = !cast<int>(ReservationKind:val);
  string NAME = ?;
}
class RetireControlUnit<int RetireControlUnit:bufferSize = ?, int RetireControlUnit:retirePerCycle = ?> {
  int ReorderBufferSize = RetireControlUnit:bufferSize;
  int MaxRetirePerCycle = RetireControlUnit:retirePerCycle;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class Returned<int Returned:argNo = ?> {	// IntrinsicProperty
  int ArgNo = Returned:argNo;
  string NAME = ?;
}
class SCOPED_ATOMIC2_impl<LLVMType SCOPED_ATOMIC2_impl:elty = ?> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [SCOPED_ATOMIC2_impl:elty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
class SCOPED_ATOMIC3_impl<LLVMType SCOPED_ATOMIC3_impl:elty = ?> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [SCOPED_ATOMIC3_impl:elty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
class SDCallSeqEnd<list<SDTypeConstraint> SDCallSeqEnd:constraints = ?> {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = SDCallSeqEnd:constraints;
  string NAME = ?;
}
class SDCallSeqStart<list<SDTypeConstraint> SDCallSeqStart:constraints = ?> {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = SDCallSeqStart:constraints;
  string NAME = ?;
}
class SDNode<string SDNode:opcode = ?, SDTypeProfile SDNode:typeprof = ?, list<SDNodeProperty> SDNode:props = [], string SDNode:sdclass = "SDNode"> {	// SDPatternOperator
  list<SDNodeProperty> Properties = SDNode:props;
  string Opcode = SDNode:opcode;
  string SDClass = SDNode:sdclass;
  SDTypeProfile TypeProfile = SDNode:typeprof;
  string NAME = ?;
}
class SDNodeProperty {
  string NAME = ?;
}
class SDNodeXForm<SDNode SDNodeXForm:opc = ?, code SDNodeXForm:xformFunction = ?> {
  SDNode Opcode = SDNodeXForm:opc;
  code XFormFunction = SDNodeXForm:xformFunction;
  string NAME = ?;
}
class SDPatternOperator {
  list<SDNodeProperty> Properties = [];
  string NAME = ?;
}
class SDTCVecEltisVT<int SDTCVecEltisVT:OpNum = ?, ValueType SDTCVecEltisVT:vt = ?> {	// SDTypeConstraint
  int OperandNum = SDTCVecEltisVT:OpNum;
  ValueType VT = SDTCVecEltisVT:vt;
  string NAME = ?;
}
class SDTCisEltOfVec<int SDTCisEltOfVec:ThisOp = ?, int SDTCisEltOfVec:OtherOp = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisEltOfVec:ThisOp;
  int OtherOpNum = SDTCisEltOfVec:OtherOp;
  string NAME = ?;
}
class SDTCisFP<int SDTCisFP:OpNum = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisFP:OpNum;
  string NAME = ?;
}
class SDTCisInt<int SDTCisInt:OpNum = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisInt:OpNum;
  string NAME = ?;
}
class SDTCisOpSmallerThanOp<int SDTCisOpSmallerThanOp:SmallOp = ?, int SDTCisOpSmallerThanOp:BigOp = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisOpSmallerThanOp:SmallOp;
  int BigOperandNum = SDTCisOpSmallerThanOp:BigOp;
  string NAME = ?;
}
class SDTCisPtrTy<int SDTCisPtrTy:OpNum = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisPtrTy:OpNum;
  string NAME = ?;
}
class SDTCisSameAs<int SDTCisSameAs:OpNum = ?, int SDTCisSameAs:OtherOp = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisSameAs:OpNum;
  int OtherOperandNum = SDTCisSameAs:OtherOp;
  string NAME = ?;
}
class SDTCisSameNumEltsAs<int SDTCisSameNumEltsAs:OpNum = ?, int SDTCisSameNumEltsAs:OtherOp = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisSameNumEltsAs:OpNum;
  int OtherOperandNum = SDTCisSameNumEltsAs:OtherOp;
  string NAME = ?;
}
class SDTCisSameSizeAs<int SDTCisSameSizeAs:OpNum = ?, int SDTCisSameSizeAs:OtherOp = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisSameSizeAs:OpNum;
  int OtherOperandNum = SDTCisSameSizeAs:OtherOp;
  string NAME = ?;
}
class SDTCisSubVecOfVec<int SDTCisSubVecOfVec:ThisOp = ?, int SDTCisSubVecOfVec:OtherOp = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisSubVecOfVec:ThisOp;
  int OtherOpNum = SDTCisSubVecOfVec:OtherOp;
  string NAME = ?;
}
class SDTCisVT<int SDTCisVT:OpNum = ?, ValueType SDTCisVT:vt = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisVT:OpNum;
  ValueType VT = SDTCisVT:vt;
  string NAME = ?;
}
class SDTCisVTSmallerThanOp<int SDTCisVTSmallerThanOp:OpNum = ?, int SDTCisVTSmallerThanOp:OtherOp = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisVTSmallerThanOp:OpNum;
  int OtherOperandNum = SDTCisVTSmallerThanOp:OtherOp;
  string NAME = ?;
}
class SDTCisVec<int SDTCisVec:OpNum = ?> {	// SDTypeConstraint
  int OperandNum = SDTCisVec:OpNum;
  string NAME = ?;
}
class SDTypeConstraint<int SDTypeConstraint:opnum = ?> {
  int OperandNum = SDTypeConstraint:opnum;
  string NAME = ?;
}
class SDTypeProfile<int SDTypeProfile:numresults = ?, int SDTypeProfile:numoperands = ?, list<SDTypeConstraint> SDTypeProfile:constraints = ?> {
  int NumResults = SDTypeProfile:numresults;
  int NumOperands = SDTypeProfile:numoperands;
  list<SDTypeConstraint> Constraints = SDTypeProfile:constraints;
  string NAME = ?;
}
class SHA_1Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SHA_2Arg_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SHA_3Arg_i32_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SHA_3Arg_v4i32_Intrinsic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SMLAL<bits<2> SMLAL:opc1 = { ?, ? }, string SMLAL:asm = ?> {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI64 RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, SMLAL:opc1{1}, SMLAL:opc1{0}, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$RdLo, GPRnopc:$RdHi);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi, pred:$p);
  string AsmString = !strconcat(SMLAL:asm, "${p}	$RdLo, $RdHi, $Rn, $Rm");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = MulFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
class SRSI<bit SRSI:wb = ?, string SRSI:asm = ?> {	// Instruction InstTemplate Encoding InstARM XI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, ?, ?, 1, SRSI:wb, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = SRSI:asm;
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = BrFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class Sched<list<SchedReadWrite> Sched:schedrw = ?> {
  list<SchedReadWrite> SchedRW = Sched:schedrw;
  string NAME = ?;
}
class SchedAlias<SchedReadWrite SchedAlias:match = ?, SchedReadWrite SchedAlias:alias = ?> {
  SchedReadWrite MatchRW = SchedAlias:match;
  SchedReadWrite AliasRW = SchedAlias:alias;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class SchedMachineModel {
  int IssueWidth = -1;
  int MicroOpBufferSize = -1;
  int LoopMicroOpBufferSize = -1;
  int LoadLatency = -1;
  int HighLatency = -1;
  int MispredictPenalty = -1;
  ProcessorItineraries Itineraries = NoItineraries;
  bit PostRAScheduler = 0;
  bit CompleteModel = 1;
  bit FullInstRWOverlapCheck = 1;
  list<Predicate> UnsupportedFeatures = [];
  bit NoModel = 0;
  string NAME = ?;
}
class SchedPredicate<code SchedPredicate:pred = ?> {
  SchedMachineModel SchedModel = ?;
  code Predicate = SchedPredicate:pred;
  string NAME = ?;
}
class SchedRead {	// SchedReadWrite
  string NAME = ?;
}
class SchedReadAdvance<int SchedReadAdvance:cycles = ?, list<SchedWrite> SchedReadAdvance:writes = []> {	// SchedReadWrite SchedRead ProcReadAdvance
  int Cycles = SchedReadAdvance:cycles;
  list<SchedWrite> ValidWrites = SchedReadAdvance:writes;
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class SchedReadVariant<list<SchedVar> SchedReadVariant:variants = ?> {	// SchedReadWrite SchedRead SchedVariant
  list<SchedVar> Variants = SchedReadVariant:variants;
  bit Variadic = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class SchedReadWrite {
  string NAME = ?;
}
class SchedVar<SchedPredicate SchedVar:pred = ?, list<SchedReadWrite> SchedVar:selected = ?> {
  SchedPredicate Predicate = SchedVar:pred;
  list<SchedReadWrite> Selected = SchedVar:selected;
  string NAME = ?;
}
class SchedVariant<list<SchedVar> SchedVariant:variants = ?> {
  list<SchedVar> Variants = SchedVariant:variants;
  bit Variadic = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class SchedWrite {	// SchedReadWrite
  string NAME = ?;
}
class SchedWriteRes<list<ProcResourceKind> SchedWriteRes:resources = ?> {	// SchedReadWrite SchedWrite ProcWriteResources
  list<ProcResourceKind> ProcResources = SchedWriteRes:resources;
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class SchedWriteVariant<list<SchedVar> SchedWriteVariant:variants = ?> {	// SchedReadWrite SchedWrite SchedVariant
  list<SchedVar> Variants = SchedWriteVariant:variants;
  bit Variadic = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class SearchableTable {
  list<string> SearchableFields = ?;
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string NAME = ?;
}
class StandardPseudoInstruction {	// Instruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = ?;
  dag InOperandList = ?;
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
class SubRegIndex<int SubRegIndex:size = ?, int SubRegIndex:offset = 0> {
  string Namespace = "";
  int Size = SubRegIndex:size;
  int Offset = SubRegIndex:offset;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
class SubtargetFeature<string SubtargetFeature:n = ?, string SubtargetFeature:a = ?, string SubtargetFeature:v = ?, string SubtargetFeature:d = ?, list<SubtargetFeature> SubtargetFeature:i = []> {
  string Name = SubtargetFeature:n;
  string Attribute = SubtargetFeature:a;
  string Value = SubtargetFeature:v;
  string Desc = SubtargetFeature:d;
  list<SubtargetFeature> Implies = SubtargetFeature:i;
  string NAME = ?;
}
class SystemZBinary<string SystemZBinary:name = ?, LLVMType SystemZBinary:type = ?> {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = !strconcat("__builtin_s390_", SystemZBinary:name);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZBinary:type];
  list<LLVMType> ParamTypes = [SystemZBinary:type, SystemZBinary:type];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZBinaryCC<LLVMType SystemZBinaryCC:type = ?> {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZBinaryCC:type, llvm_i32_ty];
  list<LLVMType> ParamTypes = [SystemZBinaryCC:type, SystemZBinaryCC:type];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZBinaryConv<string SystemZBinaryConv:name = ?, LLVMType SystemZBinaryConv:result = ?, LLVMType SystemZBinaryConv:arg = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_s390_", SystemZBinaryConv:name);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZBinaryConv:result];
  list<LLVMType> ParamTypes = [SystemZBinaryConv:arg, SystemZBinaryConv:arg];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZBinaryConvCC<LLVMType SystemZBinaryConvCC:result = ?, LLVMType SystemZBinaryConvCC:arg = ?> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZBinaryConvCC:result, llvm_i32_ty];
  list<LLVMType> ParamTypes = [SystemZBinaryConvCC:arg, SystemZBinaryConvCC:arg];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZBinaryConvIntCC<LLVMType SystemZBinaryConvIntCC:result = ?, LLVMType SystemZBinaryConvIntCC:arg = ?> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZBinaryConvIntCC:result, llvm_i32_ty];
  list<LLVMType> ParamTypes = [SystemZBinaryConvIntCC:arg, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZBinaryInt<string SystemZBinaryInt:name = ?, LLVMType SystemZBinaryInt:type = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_s390_", SystemZBinaryInt:name);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZBinaryInt:type];
  list<LLVMType> ParamTypes = [SystemZBinaryInt:type, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZQuaternaryInt<string SystemZQuaternaryInt:name = ?, LLVMType SystemZQuaternaryInt:type = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_s390_", SystemZQuaternaryInt:name);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZQuaternaryInt:type];
  list<LLVMType> ParamTypes = [SystemZQuaternaryInt:type, SystemZQuaternaryInt:type, SystemZQuaternaryInt:type, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZQuaternaryIntCC<LLVMType SystemZQuaternaryIntCC:type = ?> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZQuaternaryIntCC:type, llvm_i32_ty];
  list<LLVMType> ParamTypes = [SystemZQuaternaryIntCC:type, SystemZQuaternaryIntCC:type, SystemZQuaternaryIntCC:type, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZTernary<string SystemZTernary:name = ?, LLVMType SystemZTernary:type = ?> {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = !strconcat("__builtin_s390_", SystemZTernary:name);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZTernary:type];
  list<LLVMType> ParamTypes = [SystemZTernary:type, SystemZTernary:type, SystemZTernary:type];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZTernaryConv<string SystemZTernaryConv:name = ?, LLVMType SystemZTernaryConv:result = ?, LLVMType SystemZTernaryConv:arg = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_s390_", SystemZTernaryConv:name);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZTernaryConv:result];
  list<LLVMType> ParamTypes = [SystemZTernaryConv:arg, SystemZTernaryConv:arg, SystemZTernaryConv:result];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZTernaryInt<string SystemZTernaryInt:name = ?, LLVMType SystemZTernaryInt:type = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_s390_", SystemZTernaryInt:name);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZTernaryInt:type];
  list<LLVMType> ParamTypes = [SystemZTernaryInt:type, SystemZTernaryInt:type, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZTernaryIntCC<LLVMType SystemZTernaryIntCC:type = ?> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZTernaryIntCC:type, llvm_i32_ty];
  list<LLVMType> ParamTypes = [SystemZTernaryIntCC:type, SystemZTernaryIntCC:type, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZUnary<string SystemZUnary:name = ?, LLVMType SystemZUnary:type = ?> {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = !strconcat("__builtin_s390_", SystemZUnary:name);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZUnary:type];
  list<LLVMType> ParamTypes = [SystemZUnary:type];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZUnaryCC<LLVMType SystemZUnaryCC:type = ?> {	// SDPatternOperator Intrinsic SystemZUnaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZUnaryCC:type, llvm_i32_ty];
  list<LLVMType> ParamTypes = [SystemZUnaryCC:type];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZUnaryConv<string SystemZUnaryConv:name = ?, LLVMType SystemZUnaryConv:result = ?, LLVMType SystemZUnaryConv:arg = ?> {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = !strconcat("__builtin_s390_", SystemZUnaryConv:name);
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZUnaryConv:result];
  list<LLVMType> ParamTypes = [SystemZUnaryConv:arg];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class SystemZUnaryConvCC<LLVMType SystemZUnaryConvCC:result = ?, LLVMType SystemZUnaryConvCC:arg = ?> {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [SystemZUnaryConvCC:result, llvm_i32_ty];
  list<LLVMType> ParamTypes = [SystemZUnaryConvCC:arg];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
class T1BranchCond<bits<4> T1BranchCond:opcode = { ?, ?, ?, ? }> {	// Encoding Encoding16
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T1BranchCond:opcode{3}, T1BranchCond:opcode{2}, T1BranchCond:opcode{1}, T1BranchCond:opcode{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class T1DataProcessing<bits<4> T1DataProcessing:opcode = { ?, ?, ?, ? }> {	// Encoding Encoding16
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, T1DataProcessing:opcode{3}, T1DataProcessing:opcode{2}, T1DataProcessing:opcode{1}, T1DataProcessing:opcode{0}, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class T1Encoding<bits<6> T1Encoding:opcode = { ?, ?, ?, ?, ?, ? }> {	// Encoding Encoding16
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T1Encoding:opcode{5}, T1Encoding:opcode{4}, T1Encoding:opcode{3}, T1Encoding:opcode{2}, T1Encoding:opcode{1}, T1Encoding:opcode{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class T1General<bits<5> T1General:opcode = { ?, ?, ?, ?, ? }> {	// Encoding Encoding16
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T1General:opcode{4}, T1General:opcode{3}, T1General:opcode{2}, T1General:opcode{1}, T1General:opcode{0}, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class T1I<dag T1I:oops = ?, dag T1I:iops = ?, InstrItinClass T1I:itin = ?, string T1I:asm = ?, list<dag> T1I:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1I
  string Namespace = "ARM";
  dag OutOperandList = T1I:oops;
  dag InOperandList = T1I:iops;
  string AsmString = T1I:asm;
  list<dag> Pattern = T1I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T1It<dag T1It:oops = ?, dag T1It:iops = ?, InstrItinClass T1It:itin = ?, string T1It:asm = ?, string T1It:cstr = ?, list<dag> T1It:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1I
  string Namespace = "ARM";
  dag OutOperandList = T1It:oops;
  dag InOperandList = T1It:iops;
  string AsmString = T1It:asm;
  list<dag> Pattern = T1It:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1It:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = T1It:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T1Ix2<dag T1Ix2:oops = ?, dag T1Ix2:iops = ?, InstrItinClass T1Ix2:itin = ?, string T1Ix2:asm = ?, list<dag> T1Ix2:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1I
  string Namespace = "ARM";
  dag OutOperandList = T1Ix2:oops;
  dag InOperandList = T1Ix2:iops;
  string AsmString = T1Ix2:asm;
  list<dag> Pattern = T1Ix2:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 4;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1Ix2:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T1LdStSP<bits<3> T1LdStSP:opB = { ?, ?, ? }> {	// Encoding Encoding16 T1LoadStore
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, T1LdStSP:opB{2}, T1LdStSP:opB{1}, T1LdStSP:opB{0}, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class T1LoadStore<bits<4> T1LoadStore:opA = { ?, ?, ?, ? }, bits<3> T1LoadStore:opB = { ?, ?, ? }> {	// Encoding Encoding16
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T1LoadStore:opA{3}, T1LoadStore:opA{2}, T1LoadStore:opA{1}, T1LoadStore:opA{0}, T1LoadStore:opB{2}, T1LoadStore:opB{1}, T1LoadStore:opB{0}, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class T1Misc<bits<7> T1Misc:opcode = { ?, ?, ?, ?, ?, ?, ? }> {	// Encoding Encoding16
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, T1Misc:opcode{6}, T1Misc:opcode{5}, T1Misc:opcode{4}, T1Misc:opcode{3}, T1Misc:opcode{2}, T1Misc:opcode{1}, T1Misc:opcode{0}, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class T1Pat<dag T1Pat:pattern = ?, dag T1Pat:result = ?> {	// Pattern Pat
  dag PatternToMatch = T1Pat:pattern;
  list<dag> ResultInstrs = [T1Pat:result];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
class T1Special<bits<4> T1Special:opcode = { ?, ?, ?, ? }> {	// Encoding Encoding16
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, T1Special:opcode{3}, T1Special:opcode{2}, T1Special:opcode{1}, T1Special:opcode{0}, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class T1SystemEncoding<bits<8> T1SystemEncoding:opc = { ?, ?, ?, ?, ?, ?, ?, ? }> {	// Encoding Encoding16 T1Encoding
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, T1SystemEncoding:opc{7}, T1SystemEncoding:opc{6}, T1SystemEncoding:opc{5}, T1SystemEncoding:opc{4}, T1SystemEncoding:opc{3}, T1SystemEncoding:opc{2}, T1SystemEncoding:opc{1}, T1SystemEncoding:opc{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string NAME = ?;
}
class T1pI<dag T1pI:oops = ?, dag T1pI:iops = ?, InstrItinClass T1pI:itin = ?, string T1pI:opc = ?, string T1pI:asm = ?, list<dag> T1pI:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1pI
  string Namespace = "ARM";
  dag OutOperandList = T1pI:oops;
  dag InOperandList = !con(T1pI:iops, (ins pred:$p));
  string AsmString = !strconcat(T1pI:opc, !strconcat("${p}", T1pI:asm));
  list<dag> Pattern = T1pI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1pI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T1pIDPEncode<bits<4> T1pIDPEncode:opA = { ?, ?, ?, ? }, dag T1pIDPEncode:oops = ?, dag T1pIDPEncode:iops = ?, InstrItinClass T1pIDPEncode:itin = ?, string T1pIDPEncode:opc = ?, string T1pIDPEncode:asm = ?, list<dag> T1pIDPEncode:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1DataProcessing
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, T1pIDPEncode:opA{3}, T1pIDPEncode:opA{2}, T1pIDPEncode:opA{1}, T1pIDPEncode:opA{0}, Rm{2}, Rm{1}, Rm{0}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T1pIDPEncode:oops;
  dag InOperandList = !con(T1pIDPEncode:iops, (ins pred:$p));
  string AsmString = !strconcat(T1pIDPEncode:opc, !strconcat("${p}", T1pIDPEncode:asm));
  list<dag> Pattern = T1pIDPEncode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1pIDPEncode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
class T1pILdStEncode<bits<3> T1pILdStEncode:opcode = { ?, ?, ? }, dag T1pILdStEncode:oops = ?, dag T1pILdStEncode:iops = ?, AddrMode T1pILdStEncode:am = ?, InstrItinClass T1pILdStEncode:itin = ?, string T1pILdStEncode:opc = ?, string T1pILdStEncode:asm = ?, list<dag> T1pILdStEncode:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, T1pILdStEncode:opcode{2}, T1pILdStEncode:opcode{1}, T1pILdStEncode:opcode{0}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T1pILdStEncode:oops;
  dag InOperandList = !con(T1pILdStEncode:iops, (ins pred:$p));
  string AsmString = !strconcat(T1pILdStEncode:opc, !strconcat("${p}", T1pILdStEncode:asm));
  list<dag> Pattern = T1pILdStEncode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1pILdStEncode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = T1pILdStEncode:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T1pILdStEncodeImm<bits<4> T1pILdStEncodeImm:opA = { ?, ?, ?, ? }, bit T1pILdStEncodeImm:opB = ?, dag T1pILdStEncodeImm:oops = ?, dag T1pILdStEncodeImm:iops = ?, AddrMode T1pILdStEncodeImm:am = ?, InstrItinClass T1pILdStEncodeImm:itin = ?, string T1pILdStEncodeImm:opc = ?, string T1pILdStEncodeImm:asm = ?, list<dag> T1pILdStEncodeImm:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T1pILdStEncodeImm:opA{3}, T1pILdStEncodeImm:opA{2}, T1pILdStEncodeImm:opA{1}, T1pILdStEncodeImm:opA{0}, T1pILdStEncodeImm:opB, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T1pILdStEncodeImm:oops;
  dag InOperandList = !con(T1pILdStEncodeImm:iops, (ins pred:$p));
  string AsmString = !strconcat(T1pILdStEncodeImm:opc, !strconcat("${p}", T1pILdStEncodeImm:asm));
  list<dag> Pattern = T1pILdStEncodeImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1pILdStEncodeImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = T1pILdStEncodeImm:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T1pIMiscEncode<bits<7> T1pIMiscEncode:opA = { ?, ?, ?, ?, ?, ?, ? }, dag T1pIMiscEncode:oops = ?, dag T1pIMiscEncode:iops = ?, InstrItinClass T1pIMiscEncode:itin = ?, string T1pIMiscEncode:opc = ?, string T1pIMiscEncode:asm = ?, list<dag> T1pIMiscEncode:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Misc
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, T1pIMiscEncode:opA{6}, T1pIMiscEncode:opA{5}, T1pIMiscEncode:opA{4}, T1pIMiscEncode:opA{3}, T1pIMiscEncode:opA{2}, T1pIMiscEncode:opA{1}, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T1pIMiscEncode:oops;
  dag InOperandList = !con(T1pIMiscEncode:iops, (ins pred:$p));
  string AsmString = !strconcat(T1pIMiscEncode:opc, !strconcat("${p}", T1pIMiscEncode:asm));
  list<dag> Pattern = T1pIMiscEncode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1pIMiscEncode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
class T1pIs<dag T1pIs:oops = ?, dag T1pIs:iops = ?, InstrItinClass T1pIs:itin = ?, string T1pIs:opc = ?, string T1pIs:asm = ?, list<dag> T1pIs:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1pI
  string Namespace = "ARM";
  dag OutOperandList = T1pIs:oops;
  dag InOperandList = !con(T1pIs:iops, (ins pred:$p));
  string AsmString = !strconcat(T1pIs:opc, !strconcat("${p}", T1pIs:asm));
  list<dag> Pattern = T1pIs:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1pIs:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_s;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T1pIt<dag T1pIt:oops = ?, dag T1pIt:iops = ?, InstrItinClass T1pIt:itin = ?, string T1pIt:opc = ?, string T1pIt:asm = ?, list<dag> T1pIt:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1pI
  string Namespace = "ARM";
  dag OutOperandList = T1pIt:oops;
  dag InOperandList = !con(T1pIt:iops, (ins pred:$p));
  string AsmString = !strconcat(T1pIt:opc, !strconcat("${p}", T1pIt:asm));
  list<dag> Pattern = T1pIt:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1pIt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T1sI<dag T1sI:oops = ?, dag T1sI:iops = ?, InstrItinClass T1sI:itin = ?, string T1sI:opc = ?, string T1sI:asm = ?, list<dag> T1sI:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1sI
  string Namespace = "ARM";
  dag OutOperandList = !con(T1sI:oops, (outs s_cc_out:$s));
  dag InOperandList = !con(T1sI:iops, (ins pred:$p));
  string AsmString = !strconcat(T1sI:opc, !strconcat("${s}${p}", T1sI:asm));
  list<dag> Pattern = T1sI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1sI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  string NAME = ?;
}
class T1sIDPEncode<bits<4> T1sIDPEncode:opA = { ?, ?, ?, ? }, dag T1sIDPEncode:oops = ?, dag T1sIDPEncode:iops = ?, InstrItinClass T1sIDPEncode:itin = ?, string T1sIDPEncode:opc = ?, string T1sIDPEncode:asm = ?, list<dag> T1sIDPEncode:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1DataProcessing
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, T1sIDPEncode:opA{3}, T1sIDPEncode:opA{2}, T1sIDPEncode:opA{1}, T1sIDPEncode:opA{0}, Rn{2}, Rn{1}, Rn{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = !con(T1sIDPEncode:oops, (outs s_cc_out:$s));
  dag InOperandList = !con(T1sIDPEncode:iops, (ins pred:$p));
  string AsmString = !strconcat(T1sIDPEncode:opc, !strconcat("${s}${p}", T1sIDPEncode:asm));
  list<dag> Pattern = T1sIDPEncode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1sIDPEncode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
class T1sIGenEncode<bits<5> T1sIGenEncode:opA = { ?, ?, ?, ?, ? }, dag T1sIGenEncode:oops = ?, dag T1sIGenEncode:iops = ?, InstrItinClass T1sIGenEncode:itin = ?, string T1sIGenEncode:opc = ?, string T1sIGenEncode:asm = ?, list<dag> T1sIGenEncode:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T1sIGenEncode:opA{4}, T1sIGenEncode:opA{3}, T1sIGenEncode:opA{2}, T1sIGenEncode:opA{1}, T1sIGenEncode:opA{0}, Rm{2}, Rm{1}, Rm{0}, Rn{2}, Rn{1}, Rn{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = !con(T1sIGenEncode:oops, (outs s_cc_out:$s));
  dag InOperandList = !con(T1sIGenEncode:iops, (ins pred:$p));
  string AsmString = !strconcat(T1sIGenEncode:opc, !strconcat("${s}${p}", T1sIGenEncode:asm));
  list<dag> Pattern = T1sIGenEncode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1sIGenEncode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
class T1sIGenEncodeImm<bits<5> T1sIGenEncodeImm:opA = { ?, ?, ?, ?, ? }, dag T1sIGenEncodeImm:oops = ?, dag T1sIGenEncodeImm:iops = ?, InstrItinClass T1sIGenEncodeImm:itin = ?, string T1sIGenEncodeImm:opc = ?, string T1sIGenEncodeImm:asm = ?, list<dag> T1sIGenEncodeImm:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T1sIGenEncodeImm:opA{4}, T1sIGenEncodeImm:opA{3}, T1sIGenEncodeImm:opA{2}, T1sIGenEncodeImm:opA{1}, T1sIGenEncodeImm:opA{0}, ?, ?, ?, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = !con(T1sIGenEncodeImm:oops, (outs s_cc_out:$s));
  dag InOperandList = !con(T1sIGenEncodeImm:iops, (ins pred:$p));
  string AsmString = !strconcat(T1sIGenEncodeImm:opc, !strconcat("${s}${p}", T1sIGenEncodeImm:asm));
  list<dag> Pattern = T1sIGenEncodeImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1sIGenEncodeImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
class T1sIt<dag T1sIt:oops = ?, dag T1sIt:iops = ?, InstrItinClass T1sIt:itin = ?, string T1sIt:opc = ?, string T1sIt:asm = ?, list<dag> T1sIt:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1sI
  string Namespace = "ARM";
  dag OutOperandList = !con(T1sIt:oops, (outs s_cc_out:$s));
  dag InOperandList = !con(T1sIt:iops, (ins pred:$p));
  string AsmString = !strconcat(T1sIt:opc, !strconcat("${s}${p}", T1sIt:asm));
  list<dag> Pattern = T1sIt:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1sIt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  string NAME = ?;
}
class T1sItDPEncode<bits<4> T1sItDPEncode:opA = { ?, ?, ?, ? }, dag T1sItDPEncode:oops = ?, dag T1sItDPEncode:iops = ?, InstrItinClass T1sItDPEncode:itin = ?, string T1sItDPEncode:opc = ?, string T1sItDPEncode:asm = ?, list<dag> T1sItDPEncode:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, T1sItDPEncode:opA{3}, T1sItDPEncode:opA{2}, T1sItDPEncode:opA{1}, T1sItDPEncode:opA{0}, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = !con(T1sItDPEncode:oops, (outs s_cc_out:$s));
  dag InOperandList = !con(T1sItDPEncode:iops, (ins pred:$p));
  string AsmString = !strconcat(T1sItDPEncode:opc, !strconcat("${s}${p}", T1sItDPEncode:asm));
  list<dag> Pattern = T1sItDPEncode:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1sItDPEncode:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
class T1sItGenEncodeImm<bits<5> T1sItGenEncodeImm:opA = { ?, ?, ?, ?, ? }, dag T1sItGenEncodeImm:oops = ?, dag T1sItGenEncodeImm:iops = ?, InstrItinClass T1sItGenEncodeImm:itin = ?, string T1sItGenEncodeImm:opc = ?, string T1sItGenEncodeImm:asm = ?, list<dag> T1sItGenEncodeImm:pattern = ?> {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1General
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T1sItGenEncodeImm:opA{4}, T1sItGenEncodeImm:opA{3}, T1sItGenEncodeImm:opA{2}, Rdn{2}, Rdn{1}, Rdn{0}, imm8{7}, imm8{6}, imm8{5}, imm8{4}, imm8{3}, imm8{2}, imm8{1}, imm8{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = !con(T1sItGenEncodeImm:oops, (outs s_cc_out:$s));
  dag InOperandList = !con(T1sItGenEncodeImm:iops, (ins pred:$p));
  string AsmString = !strconcat(T1sItGenEncodeImm:opc, !strconcat("${s}${p}", T1sItGenEncodeImm:asm));
  list<dag> Pattern = T1sItGenEncodeImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T1sItGenEncodeImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<8> imm8 = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2AddrMode_Imm8 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm8";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getT2AddrModeImm8OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm8OffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectT2AddrModeImm8";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
class T2AddrMode_Imm8s4 {	// DAGOperand Operand MemOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm8s4";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getT2AddrModeImm8s4OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm8s4OffsetAsmOperand;
  string NAME = ?;
}
class T2BitFI<dag T2BitFI:oops = ?, dag T2BitFI:iops = ?, InstrItinClass T2BitFI:itin = ?, string T2BitFI:opc = ?, string T2BitFI:asm = ?, list<dag> T2BitFI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, lsb{4}, lsb{3}, lsb{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, lsb{1}, lsb{0}, ?, msb{4}, msb{3}, msb{2}, msb{1}, msb{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2BitFI:oops;
  dag InOperandList = !con(T2BitFI:iops, (ins pred:$p));
  string AsmString = !strconcat(T2BitFI:opc, !strconcat("${p}", T2BitFI:asm));
  list<dag> Pattern = T2BitFI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2BitFI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<5> msb = { ?, ?, ?, ?, ? };
  bits<5> lsb = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2CI<bits<4> T2CI:op31_28 = { ?, ?, ?, ? }, dag T2CI:oops = ?, dag T2CI:iops = ?, string T2CI:opc = ?, string T2CI:asm = ?, list<dag> T2CI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { T2CI:op31_28{3}, T2CI:op31_28{2}, T2CI:op31_28{1}, T2CI:op31_28{0}, 1, 1, 0, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2CI:oops;
  dag InOperandList = !con(T2CI:iops, (ins pred:$p));
  string AsmString = !strconcat(T2CI:opc, !strconcat("${p}", T2CI:asm));
  list<dag> Pattern = T2CI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2Cop<bits<4> T2Cop:opc = { ?, ?, ?, ? }, dag T2Cop:oops = ?, dag T2Cop:iops = ?, string T2Cop:opcstr = ?, string T2Cop:asm = ?, list<dag> T2Cop:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { T2Cop:opc{3}, T2Cop:opc{2}, T2Cop:opc{1}, T2Cop:opc{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Cop:oops;
  dag InOperandList = !con(T2Cop:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Cop:opcstr, !strconcat("${p}", T2Cop:asm));
  list<dag> Pattern = T2Cop:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2DCPS<bits<2> T2DCPS:opt = { ?, ? }, string T2DCPS:opc = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T2DCPS:opt{1}, T2DCPS:opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = !strconcat(T2DCPS:opc, "${p}");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2DualHalfMul<bits<3> T2DualHalfMul:op22_20 = { ?, ?, ? }, bits<4> T2DualHalfMul:op7_4 = { ?, ?, ?, ? }, string T2DualHalfMul:opc = ?, Intrinsic T2DualHalfMul:intrinsic = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2ThreeReg_mac Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, T2DualHalfMul:op22_20{2}, T2DualHalfMul:op22_20{1}, T2DualHalfMul:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2DualHalfMul:op7_4{3}, T2DualHalfMul:op7_4{2}, T2DualHalfMul:op7_4{1}, T2DualHalfMul:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = !strconcat(T2DualHalfMul:opc, "${p}	$Rd, $Rn, $Rm");
  list<dag> Pattern = [(set rGPR:$Rd, (T2DualHalfMul:intrinsic rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2DualHalfMulAdd<bits<3> T2DualHalfMulAdd:op22_20 = { ?, ?, ? }, bits<4> T2DualHalfMulAdd:op7_4 = { ?, ?, ?, ? }, string T2DualHalfMulAdd:opc = ?, Intrinsic T2DualHalfMulAdd:intrinsic = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, T2DualHalfMulAdd:op22_20{2}, T2DualHalfMulAdd:op22_20{1}, T2DualHalfMulAdd:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2DualHalfMulAdd:op7_4{3}, T2DualHalfMulAdd:op7_4{2}, T2DualHalfMulAdd:op7_4{1}, T2DualHalfMulAdd:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = !strconcat(T2DualHalfMulAdd:opc, "${p}	$Rd, $Rn, $Rm, $Ra");
  list<dag> Pattern = [(set rGPR:$Rd, (T2DualHalfMulAdd:intrinsic rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2DualHalfMulAddLong<bits<3> T2DualHalfMulAddLong:op22_20 = { ?, ?, ? }, bits<4> T2DualHalfMulAddLong:op7_4 = { ?, ?, ?, ? }, string T2DualHalfMulAddLong:opc = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac RegConstraint Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, T2DualHalfMulAddLong:op22_20{2}, T2DualHalfMulAddLong:op22_20{1}, T2DualHalfMulAddLong:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2DualHalfMulAddLong:op7_4{3}, T2DualHalfMulAddLong:op7_4{2}, T2DualHalfMulAddLong:op7_4{1}, T2DualHalfMulAddLong:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Ra, rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = !strconcat(T2DualHalfMulAddLong:opc, "${p}	$Ra, $Rd, $Rn, $Rm");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$Ra = $RLo, $Rd = $RHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2FourReg<dag T2FourReg:oops = ?, dag T2FourReg:iops = ?, InstrItinClass T2FourReg:itin = ?, string T2FourReg:opc = ?, string T2FourReg:asm = ?, list<dag> T2FourReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2FourReg:oops;
  dag InOperandList = !con(T2FourReg:iops, (ins pred:$p));
  string AsmString = !strconcat(T2FourReg:opc, !strconcat("${p}", T2FourReg:asm));
  list<dag> Pattern = T2FourReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2FourReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2FourRegMLA<bits<4> T2FourRegMLA:op7_4 = { ?, ?, ?, ? }, string T2FourRegMLA:opc = ?, list<dag> T2FourRegMLA:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2FourRegMLA:op7_4{3}, T2FourRegMLA:op7_4{2}, T2FourRegMLA:op7_4{1}, T2FourRegMLA:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = !strconcat(T2FourRegMLA:opc, "${p}	$Rd, $Rn, $Rm, $Ra");
  list<dag> Pattern = T2FourRegMLA:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2FourRegSMLA<bits<3> T2FourRegSMLA:op22_20 = { ?, ?, ? }, bits<2> T2FourRegSMLA:op5_4 = { ?, ? }, string T2FourRegSMLA:opc = ?, list<dag> T2FourRegSMLA:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, T2FourRegSMLA:op22_20{2}, T2FourRegSMLA:op22_20{1}, T2FourRegSMLA:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, T2FourRegSMLA:op5_4{1}, T2FourRegSMLA:op5_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = !strconcat(T2FourRegSMLA:opc, "${p}	$Rd, $Rn, $Rm, $Ra");
  list<dag> Pattern = T2FourRegSMLA:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2FourRegSMMLA<bits<3> T2FourRegSMMLA:op22_20 = { ?, ?, ? }, bits<4> T2FourRegSMMLA:op7_4 = { ?, ?, ?, ? }, string T2FourRegSMMLA:opc = ?, list<dag> T2FourRegSMMLA:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, T2FourRegSMMLA:op22_20{2}, T2FourRegSMMLA:op22_20{1}, T2FourRegSMMLA:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2FourRegSMMLA:op7_4{3}, T2FourRegSMMLA:op7_4{2}, T2FourRegSMMLA:op7_4{1}, T2FourRegSMMLA:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = !strconcat(T2FourRegSMMLA:opc, "${p}	$Rd, $Rn, $Rm, $Ra");
  list<dag> Pattern = T2FourRegSMMLA:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2FourReg_mac<bit T2FourReg_mac:long = ?, bits<3> T2FourReg_mac:op22_20 = { ?, ?, ? }, bits<4> T2FourReg_mac:op7_4 = { ?, ?, ?, ? }, dag T2FourReg_mac:oops = ?, dag T2FourReg_mac:iops = ?, InstrItinClass T2FourReg_mac:itin = ?, string T2FourReg_mac:opc = ?, string T2FourReg_mac:asm = ?, list<dag> T2FourReg_mac:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, T2FourReg_mac:long, T2FourReg_mac:op22_20{2}, T2FourReg_mac:op22_20{1}, T2FourReg_mac:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2FourReg_mac:op7_4{3}, T2FourReg_mac:op7_4{2}, T2FourReg_mac:op7_4{1}, T2FourReg_mac:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2FourReg_mac:oops;
  dag InOperandList = !con(T2FourReg_mac:iops, (ins pred:$p));
  string AsmString = !strconcat(T2FourReg_mac:opc, !strconcat("${p}", T2FourReg_mac:asm));
  list<dag> Pattern = T2FourReg_mac:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2FourReg_mac:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2I<dag T2I:oops = ?, dag T2I:iops = ?, InstrItinClass T2I:itin = ?, string T2I:opc = ?, string T2I:asm = ?, list<dag> T2I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2I:oops;
  dag InOperandList = !con(T2I:iops, (ins pred:$p));
  string AsmString = !strconcat(T2I:opc, !strconcat("${p}", T2I:asm));
  list<dag> Pattern = T2I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2I_crc32<bit T2I_crc32:C = ?, bits<2> T2I_crc32:sz = { ?, ? }, string T2I_crc32:suffix = ?, SDPatternOperator T2I_crc32:builtin = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI T2ThreeRegNoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, T2I_crc32:C, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, T2I_crc32:sz{1}, T2I_crc32:sz{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm);
  string AsmString = !strconcat("crc32", !strconcat(T2I_crc32:suffix, "	$Rd, $Rn, $Rm"));
  list<dag> Pattern = [(set rGPR:$Rd, (T2I_crc32:builtin rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2I_ext_rrot<bits<3> T2I_ext_rrot:opcod = { ?, ?, ? }, string T2I_ext_rrot:opc = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoReg T2I_ext_rrot_base Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, T2I_ext_rrot:opcod{2}, T2I_ext_rrot:opcod{1}, T2I_ext_rrot:opcod{0}, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = !strconcat(T2I_ext_rrot:opc, "${p}.w	$Rd, $Rm$rot");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
class T2I_ext_rrot_base<bits<3> T2I_ext_rrot_base:opcod = { ?, ?, ? }, dag T2I_ext_rrot_base:iops = ?, dag T2I_ext_rrot_base:oops = ?, string T2I_ext_rrot_base:opc = ?, string T2I_ext_rrot_base:oprs = ?, list<dag> T2I_ext_rrot_base:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoReg
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, T2I_ext_rrot_base:opcod{2}, T2I_ext_rrot_base:opcod{1}, T2I_ext_rrot_base:opcod{0}, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2I_ext_rrot_base:iops;
  dag InOperandList = !con(T2I_ext_rrot_base:oops, (ins pred:$p));
  string AsmString = !strconcat(T2I_ext_rrot_base:opc, !strconcat("${p}", T2I_ext_rrot_base:oprs));
  list<dag> Pattern = T2I_ext_rrot_base:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
class T2I_ext_rrot_xtb16<bits<3> T2I_ext_rrot_xtb16:opcod = { ?, ?, ? }, string T2I_ext_rrot_xtb16:opc = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoReg T2I_ext_rrot_base Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, T2I_ext_rrot_xtb16:opcod{2}, T2I_ext_rrot_xtb16:opcod{1}, T2I_ext_rrot_xtb16:opcod{0}, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = !strconcat(T2I_ext_rrot_xtb16:opc, "${p}	$Rd, $Rm$rot");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
class T2I_exta_rrot<bits<3> T2I_exta_rrot:opcod = { ?, ?, ? }, string T2I_exta_rrot:opc = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, T2I_exta_rrot:opcod{2}, T2I_exta_rrot:opcod{1}, T2I_exta_rrot:opcod{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = !strconcat(T2I_exta_rrot:opc, "${p}	$Rd, $Rn, $Rm$rot");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAsr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
class T2I_ldrex<bits<4> T2I_ldrex:opcod = { ?, ?, ?, ? }, dag T2I_ldrex:oops = ?, dag T2I_ldrex:iops = ?, AddrMode T2I_ldrex:am = ?, int T2I_ldrex:sz = ?, InstrItinClass T2I_ldrex:itin = ?, string T2I_ldrex:opc = ?, string T2I_ldrex:asm = ?, string T2I_ldrex:cstr = ?, list<dag> T2I_ldrex:pattern = ?, bits<4> T2I_ldrex:rt2 = { 1, 1, 1, 1 }> {	// Instruction InstTemplate Encoding InstARM Thumb2I
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, T2I_ldrex:rt2{3}, T2I_ldrex:rt2{2}, T2I_ldrex:rt2{1}, T2I_ldrex:rt2{0}, T2I_ldrex:opcod{3}, T2I_ldrex:opcod{2}, T2I_ldrex:opcod{1}, T2I_ldrex:opcod{0}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2I_ldrex:oops;
  dag InOperandList = !con(T2I_ldrex:iops, (ins pred:$p));
  string AsmString = !strconcat(T2I_ldrex:opc, !strconcat("${p}", T2I_ldrex:asm));
  list<dag> Pattern = T2I_ldrex:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = T2I_ldrex:sz;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2I_ldrex:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = T2I_ldrex:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = T2I_ldrex:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2I_misc<bits<2> T2I_misc:op1 = { ?, ? }, bits<2> T2I_misc:op2 = { ?, ? }, dag T2I_misc:oops = ?, dag T2I_misc:iops = ?, InstrItinClass T2I_misc:itin = ?, string T2I_misc:opc = ?, string T2I_misc:asm = ?, list<dag> T2I_misc:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, T2I_misc:op1{1}, T2I_misc:op1{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, T2I_misc:op2{1}, T2I_misc:op2{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2I_misc:oops;
  dag InOperandList = !con(T2I_misc:iops, (ins pred:$p));
  string AsmString = !strconcat(T2I_misc:opc, !strconcat("${p}", T2I_misc:asm));
  list<dag> Pattern = T2I_misc:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2I_misc:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2I_pam<bits<3> T2I_pam:op22_20 = { ?, ?, ? }, bits<4> T2I_pam:op7_4 = { ?, ?, ?, ? }, string T2I_pam:opc = ?, list<dag> T2I_pam:pat = ?, dag T2I_pam:iops = ?, string T2I_pam:asm = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, T2I_pam:op22_20{2}, T2I_pam:op22_20{1}, T2I_pam:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2I_pam:op7_4{3}, T2I_pam:op7_4{2}, T2I_pam:op7_4{1}, T2I_pam:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = !con(T2I_pam:iops, (ins pred:$p));
  string AsmString = !strconcat(T2I_pam:opc, !strconcat("${p}", T2I_pam:asm));
  list<dag> Pattern = T2I_pam:pat;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2I_pam_intrinsics<bits<3> T2I_pam_intrinsics:op22_20 = { ?, ?, ? }, bits<4> T2I_pam_intrinsics:op7_4 = { ?, ?, ?, ? }, string T2I_pam_intrinsics:opc = ?, Intrinsic T2I_pam_intrinsics:intrinsic = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, T2I_pam_intrinsics:op22_20{2}, T2I_pam_intrinsics:op22_20{1}, T2I_pam_intrinsics:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2I_pam_intrinsics:op7_4{3}, T2I_pam_intrinsics:op7_4{2}, T2I_pam_intrinsics:op7_4{1}, T2I_pam_intrinsics:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = !strconcat(T2I_pam_intrinsics:opc, "${p}	$Rd, $Rn, $Rm");
  list<dag> Pattern = [(set rGPR:$Rd, (T2I_pam_intrinsics:intrinsic rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2I_pam_intrinsics_rev<bits<3> T2I_pam_intrinsics_rev:op22_20 = { ?, ?, ? }, bits<4> T2I_pam_intrinsics_rev:op7_4 = { ?, ?, ?, ? }, string T2I_pam_intrinsics_rev:opc = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, T2I_pam_intrinsics_rev:op22_20{2}, T2I_pam_intrinsics_rev:op22_20{1}, T2I_pam_intrinsics_rev:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2I_pam_intrinsics_rev:op7_4{3}, T2I_pam_intrinsics_rev:op7_4{2}, T2I_pam_intrinsics_rev:op7_4{1}, T2I_pam_intrinsics_rev:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rGPR:$Rn, pred:$p);
  string AsmString = !strconcat(T2I_pam_intrinsics_rev:opc, "${p}	$Rd, $Rm, $Rn");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2I_strex<bits<4> T2I_strex:opcod = { ?, ?, ?, ? }, dag T2I_strex:oops = ?, dag T2I_strex:iops = ?, AddrMode T2I_strex:am = ?, int T2I_strex:sz = ?, InstrItinClass T2I_strex:itin = ?, string T2I_strex:opc = ?, string T2I_strex:asm = ?, string T2I_strex:cstr = ?, list<dag> T2I_strex:pattern = ?, bits<4> T2I_strex:rt2 = { 1, 1, 1, 1 }> {	// Instruction InstTemplate Encoding InstARM Thumb2I
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, T2I_strex:rt2{3}, T2I_strex:rt2{2}, T2I_strex:rt2{1}, T2I_strex:rt2{0}, T2I_strex:opcod{3}, T2I_strex:opcod{2}, T2I_strex:opcod{1}, T2I_strex:opcod{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2I_strex:oops;
  dag InOperandList = !con(T2I_strex:iops, (ins pred:$p));
  string AsmString = !strconcat(T2I_strex:opc, !strconcat("${p}", T2I_strex:asm));
  list<dag> Pattern = T2I_strex:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = T2I_strex:sz;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2I_strex:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = T2I_strex:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = T2I_strex:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2Ii12<dag T2Ii12:oops = ?, dag T2Ii12:iops = ?, InstrItinClass T2Ii12:itin = ?, string T2Ii12:opc = ?, string T2Ii12:asm = ?, list<dag> T2Ii12:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Ii12:oops;
  dag InOperandList = !con(T2Ii12:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Ii12:opc, !strconcat("${p}", T2Ii12:asm));
  list<dag> Pattern = T2Ii12:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2Ii12:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2Ii8<dag T2Ii8:oops = ?, dag T2Ii8:iops = ?, InstrItinClass T2Ii8:itin = ?, string T2Ii8:opc = ?, string T2Ii8:asm = ?, list<dag> T2Ii8:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Ii8:oops;
  dag InOperandList = !con(T2Ii8:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Ii8:opc, !strconcat("${p}", T2Ii8:asm));
  list<dag> Pattern = T2Ii8:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2Ii8:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2Ii8s4<bit T2Ii8s4:P = ?, bit T2Ii8s4:W = ?, bit T2Ii8s4:isLoad = ?, dag T2Ii8s4:oops = ?, dag T2Ii8s4:iops = ?, InstrItinClass T2Ii8s4:itin = ?, string T2Ii8s4:opc = ?, string T2Ii8s4:asm = ?, string T2Ii8s4:cstr = ?, list<dag> T2Ii8s4:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, T2Ii8s4:P, addr{8}, 1, T2Ii8s4:W, T2Ii8s4:isLoad, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Ii8s4:oops;
  dag InOperandList = !con(T2Ii8s4:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Ii8s4:opc, !strconcat("${p}", T2Ii8s4:asm));
  list<dag> Pattern = T2Ii8s4:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2Ii8s4:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = T2Ii8s4:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8s4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2Ii8s4post<bit T2Ii8s4post:P = ?, bit T2Ii8s4post:W = ?, bit T2Ii8s4post:isLoad = ?, dag T2Ii8s4post:oops = ?, dag T2Ii8s4post:iops = ?, InstrItinClass T2Ii8s4post:itin = ?, string T2Ii8s4post:opc = ?, string T2Ii8s4post:asm = ?, string T2Ii8s4post:cstr = ?, list<dag> T2Ii8s4post:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, T2Ii8s4post:P, imm{8}, 1, T2Ii8s4post:W, T2Ii8s4post:isLoad, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Ii8s4post:oops;
  dag InOperandList = !con(T2Ii8s4post:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Ii8s4post:opc, !strconcat("${p}", T2Ii8s4post:asm));
  list<dag> Pattern = T2Ii8s4post:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2Ii8s4post:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = T2Ii8s4post:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8s4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<9> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2IldT<bit T2IldT:signed = ?, bits<2> T2IldT:type = { ?, ? }, string T2IldT:opc = ?, InstrItinClass T2IldT:ii = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, T2IldT:signed, 0, T2IldT:type{1}, T2IldT:type{0}, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_posimm8:$addr, pred:$p);
  string AsmString = !strconcat(T2IldT:opc, "${p}	$Rt, $addr");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2IldT:ii;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadT";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2Ildacq<bits<4> T2Ildacq:bits23_20 = { ?, ?, ?, ? }, bits<2> T2Ildacq:bit54 = { ?, ? }, dag T2Ildacq:oops = ?, dag T2Ildacq:iops = ?, string T2Ildacq:opc = ?, string T2Ildacq:asm = ?, list<dag> T2Ildacq:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, T2Ildacq:bits23_20{3}, T2Ildacq:bits23_20{2}, T2Ildacq:bits23_20{1}, T2Ildacq:bits23_20{0}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, T2Ildacq:bit54{1}, T2Ildacq:bit54{0}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Ildacq:oops;
  dag InOperandList = !con(T2Ildacq:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Ildacq:opc, !strconcat("${p}", T2Ildacq:asm));
  list<dag> Pattern = T2Ildacq:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2Ipc<dag T2Ipc:oops = ?, dag T2Ipc:iops = ?, InstrItinClass T2Ipc:itin = ?, string T2Ipc:opc = ?, string T2Ipc:asm = ?, list<dag> T2Ipc:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Ipc:oops;
  dag InOperandList = !con(T2Ipc:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Ipc:opc, !strconcat("${p}", T2Ipc:asm));
  list<dag> Pattern = T2Ipc:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2Ipc:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_pc;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2Iplpci<bits<1> T2Iplpci:inst = { ? }, string T2Iplpci:opc = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, T2Iplpci:inst{0}, addr{12}, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2ldrlabel:$addr, pred:$p);
  string AsmString = !strconcat(T2Iplpci:opc, "${p}	$addr");
  list<dag> Pattern = [(ARMPreload (ARMWrapper tconstpool:$addr), (i32 0), (i32 T2Iplpci:inst))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadLabel";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2Ipostldst<bit T2Ipostldst:signed = ?, bits<2> T2Ipostldst:opcod = { ?, ? }, bit T2Ipostldst:load = ?, bit T2Ipostldst:pre = ?, dag T2Ipostldst:oops = ?, dag T2Ipostldst:iops = ?, AddrMode T2Ipostldst:am = ?, IndexMode T2Ipostldst:im = ?, InstrItinClass T2Ipostldst:itin = ?, string T2Ipostldst:opc = ?, string T2Ipostldst:asm = ?, string T2Ipostldst:cstr = ?, list<dag> T2Ipostldst:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, T2Ipostldst:signed, 0, T2Ipostldst:opcod{1}, T2Ipostldst:opcod{0}, T2Ipostldst:load, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, T2Ipostldst:pre, offset{8}, 1, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Ipostldst:oops;
  dag InOperandList = !con(T2Ipostldst:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Ipostldst:opc, !strconcat("${p}", T2Ipostldst:asm));
  list<dag> Pattern = T2Ipostldst:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2Ipostldst:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = T2Ipostldst:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = T2Ipostldst:am;
  IndexMode IM = T2Ipostldst:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2Ipreldst<bit T2Ipreldst:signed = ?, bits<2> T2Ipreldst:opcod = { ?, ? }, bit T2Ipreldst:load = ?, bit T2Ipreldst:pre = ?, dag T2Ipreldst:oops = ?, dag T2Ipreldst:iops = ?, AddrMode T2Ipreldst:am = ?, IndexMode T2Ipreldst:im = ?, InstrItinClass T2Ipreldst:itin = ?, string T2Ipreldst:opc = ?, string T2Ipreldst:asm = ?, string T2Ipreldst:cstr = ?, list<dag> T2Ipreldst:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, T2Ipreldst:signed, 0, T2Ipreldst:opcod{1}, T2Ipreldst:opcod{0}, T2Ipreldst:load, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, T2Ipreldst:pre, addr{8}, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Ipreldst:oops;
  dag InOperandList = !con(T2Ipreldst:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Ipreldst:opc, !strconcat("${p}", T2Ipreldst:asm));
  list<dag> Pattern = T2Ipreldst:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2Ipreldst:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = T2Ipreldst:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = T2Ipreldst:am;
  IndexMode IM = T2Ipreldst:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2Iso<dag T2Iso:oops = ?, dag T2Iso:iops = ?, InstrItinClass T2Iso:itin = ?, string T2Iso:opc = ?, string T2Iso:asm = ?, list<dag> T2Iso:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Iso:oops;
  dag InOperandList = !con(T2Iso:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Iso:opc, !strconcat("${p}", T2Iso:asm));
  list<dag> Pattern = T2Iso:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2Iso:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2IstT<bits<2> T2IstT:type = { ?, ? }, string T2IstT:opc = ?, InstrItinClass T2IstT:ii = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, T2IstT:type{1}, T2IstT:type{0}, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_imm8:$addr, pred:$p);
  string AsmString = !strconcat(T2IstT:opc, "${p}	$Rt, $addr");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2IstT:ii;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2Istrrel<bits<2> T2Istrrel:bit54 = { ?, ? }, dag T2Istrrel:oops = ?, dag T2Istrrel:iops = ?, string T2Istrrel:opc = ?, string T2Istrrel:asm = ?, list<dag> T2Istrrel:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, T2Istrrel:bit54{1}, T2Istrrel:bit54{0}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2Istrrel:oops;
  dag InOperandList = !con(T2Istrrel:iops, (ins pred:$p));
  string AsmString = !strconcat(T2Istrrel:opc, !strconcat("${p}", T2Istrrel:asm));
  list<dag> Pattern = T2Istrrel:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2JTI<dag T2JTI:oops = ?, dag T2JTI:iops = ?, InstrItinClass T2JTI:itin = ?, string T2JTI:asm = ?, list<dag> T2JTI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2XI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2JTI:oops;
  dag InOperandList = T2JTI:iops;
  string AsmString = T2JTI:asm;
  list<dag> Pattern = T2JTI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2JTI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2MlaLong<bits<3> T2MlaLong:opc22_20 = { ?, ?, ? }, bits<4> T2MlaLong:opc7_4 = { ?, ?, ?, ? }, string T2MlaLong:opc = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I RegConstraint Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, T2MlaLong:opc22_20{2}, T2MlaLong:opc22_20{1}, T2MlaLong:opc22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, T2MlaLong:opc7_4{3}, T2MlaLong:opc7_4{2}, T2MlaLong:opc7_4{1}, T2MlaLong:opc7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = !strconcat(T2MlaLong:opc, "${p}	$RdLo, $RdHi, $Rn, $Rm");
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2MulLong<bits<3> T2MulLong:opc22_20 = { ?, ?, ? }, bits<4> T2MulLong:opc7_4 = { ?, ?, ?, ? }, string T2MulLong:opc = ?, list<dag> T2MulLong:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, T2MulLong:opc22_20{2}, T2MulLong:opc22_20{1}, T2MulLong:opc22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, T2MulLong:opc7_4{3}, T2MulLong:opc7_4{2}, T2MulLong:opc7_4{1}, T2MulLong:opc7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = !strconcat(T2MulLong:opc, "${p}	$RdLo, $RdHi, $Rn, $Rm");
  list<dag> Pattern = T2MulLong:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL64;
  list<SchedReadWrite> SchedRW = [WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2OneRegCmpImm<dag T2OneRegCmpImm:oops = ?, dag T2OneRegCmpImm:iops = ?, InstrItinClass T2OneRegCmpImm:itin = ?, string T2OneRegCmpImm:opc = ?, string T2OneRegCmpImm:asm = ?, list<dag> T2OneRegCmpImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, imm{11}, ?, ?, ?, ?, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, imm{10}, imm{9}, imm{8}, ?, ?, ?, ?, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2OneRegCmpImm:oops;
  dag InOperandList = !con(T2OneRegCmpImm:iops, (ins pred:$p));
  string AsmString = !strconcat(T2OneRegCmpImm:opc, !strconcat("${p}", T2OneRegCmpImm:asm));
  list<dag> Pattern = T2OneRegCmpImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2OneRegCmpImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2OneRegCmpShiftedReg<dag T2OneRegCmpShiftedReg:oops = ?, dag T2OneRegCmpShiftedReg:iops = ?, InstrItinClass T2OneRegCmpShiftedReg:itin = ?, string T2OneRegCmpShiftedReg:opc = ?, string T2OneRegCmpShiftedReg:asm = ?, list<dag> T2OneRegCmpShiftedReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, ?, ?, ?, ?, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2OneRegCmpShiftedReg:oops;
  dag InOperandList = !con(T2OneRegCmpShiftedReg:iops, (ins pred:$p));
  string AsmString = !strconcat(T2OneRegCmpShiftedReg:opc, !strconcat("${p}", T2OneRegCmpShiftedReg:asm));
  list<dag> Pattern = T2OneRegCmpShiftedReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2OneRegCmpShiftedReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2OneRegImm<dag T2OneRegImm:oops = ?, dag T2OneRegImm:iops = ?, InstrItinClass T2OneRegImm:itin = ?, string T2OneRegImm:opc = ?, string T2OneRegImm:asm = ?, list<dag> T2OneRegImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, imm{11}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2OneRegImm:oops;
  dag InOperandList = !con(T2OneRegImm:iops, (ins pred:$p));
  string AsmString = !strconcat(T2OneRegImm:opc, !strconcat("${p}", T2OneRegImm:asm));
  list<dag> Pattern = T2OneRegImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2OneRegImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2OneRegShiftedReg<dag T2OneRegShiftedReg:oops = ?, dag T2OneRegShiftedReg:iops = ?, InstrItinClass T2OneRegShiftedReg:itin = ?, string T2OneRegShiftedReg:opc = ?, string T2OneRegShiftedReg:asm = ?, list<dag> T2OneRegShiftedReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2OneRegShiftedReg:oops;
  dag InOperandList = !con(T2OneRegShiftedReg:iops, (ins pred:$p));
  string AsmString = !strconcat(T2OneRegShiftedReg:opc, !strconcat("${p}", T2OneRegShiftedReg:asm));
  list<dag> Pattern = T2OneRegShiftedReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2OneRegShiftedReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2PCOneRegImm<dag T2PCOneRegImm:oops = ?, dag T2PCOneRegImm:iops = ?, InstrItinClass T2PCOneRegImm:itin = ?, string T2PCOneRegImm:asm = ?, list<dag> T2PCOneRegImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI
  field bits<32> Inst = { ?, ?, ?, ?, ?, label{11}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, label{10}, label{9}, label{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, label{7}, label{6}, label{5}, label{4}, label{3}, label{2}, label{1}, label{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2PCOneRegImm:oops;
  dag InOperandList = T2PCOneRegImm:iops;
  string AsmString = T2PCOneRegImm:asm;
  list<dag> Pattern = T2PCOneRegImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2PCOneRegImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> label = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2Pat<dag T2Pat:pattern = ?, dag T2Pat:result = ?> {	// Pattern Pat
  dag PatternToMatch = T2Pat:pattern;
  list<dag> ResultInstrs = [T2Pat:result];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
class T2RFE<bits<12> T2RFE:op31_20 = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? }, dag T2RFE:oops = ?, dag T2RFE:iops = ?, InstrItinClass T2RFE:itin = ?, string T2RFE:opc = ?, string T2RFE:asm = ?, list<dag> T2RFE:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { T2RFE:op31_20{11}, T2RFE:op31_20{10}, T2RFE:op31_20{9}, T2RFE:op31_20{8}, T2RFE:op31_20{7}, T2RFE:op31_20{6}, T2RFE:op31_20{5}, T2RFE:op31_20{4}, T2RFE:op31_20{3}, T2RFE:op31_20{2}, T2RFE:op31_20{1}, T2RFE:op31_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2RFE:oops;
  dag InOperandList = !con(T2RFE:iops, (ins pred:$p));
  string AsmString = !strconcat(T2RFE:opc, !strconcat("${p}", T2RFE:asm));
  list<dag> Pattern = T2RFE:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [PC];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2RFE:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2SMMUL<bits<4> T2SMMUL:op7_4 = { ?, ?, ?, ? }, string T2SMMUL:opc = ?, list<dag> T2SMMUL:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2SMMUL:op7_4{3}, T2SMMUL:op7_4{2}, T2SMMUL:op7_4{1}, T2SMMUL:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = !strconcat(T2SMMUL:opc, "${p}	$Rd, $Rn, $Rm");
  list<dag> Pattern = T2SMMUL:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL32;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2SRS<bits<2> T2SRS:Op = { ?, ? }, bit T2SRS:W = ?, dag T2SRS:oops = ?, dag T2SRS:iops = ?, InstrItinClass T2SRS:itin = ?, string T2SRS:opc = ?, string T2SRS:asm = ?, list<dag> T2SRS:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, T2SRS:Op{1}, T2SRS:Op{0}, 0, T2SRS:W, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2SRS:oops;
  dag InOperandList = !con(T2SRS:iops, (ins pred:$p));
  string AsmString = !strconcat(T2SRS:opc, !strconcat("${p}", T2SRS:asm));
  list<dag> Pattern = T2SRS:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2SRS:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2SatI<dag T2SatI:iops = ?, string T2SatI:opc = ?, string T2SatI:asm = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, ?, ?, sh{5}, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, sh{4}, sh{3}, sh{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{1}, sh{0}, 0, sat_imm{4}, sat_imm{3}, sat_imm{2}, sat_imm{1}, sat_imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = !con(T2SatI:iops, (ins pred:$p));
  string AsmString = !strconcat(T2SatI:opc, !strconcat("${p}", T2SatI:asm));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<5> sat_imm = { ?, ?, ?, ?, ? };
  bits<6> sh = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2TT<bits<2> T2TT:at = { ?, ? }, string T2TT:asm = ?, list<dag> T2TT:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, T2TT:at{1}, T2TT:at{0}, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins GPRnopc:$Rn, pred:$p);
  string AsmString = !strconcat(T2TT:asm, "${p}	$Rt, $Rn");
  list<dag> Pattern = T2TT:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2ThreeReg<dag T2ThreeReg:oops = ?, dag T2ThreeReg:iops = ?, InstrItinClass T2ThreeReg:itin = ?, string T2ThreeReg:opc = ?, string T2ThreeReg:asm = ?, list<dag> T2ThreeReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ?, ?, ?, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2ThreeReg:oops;
  dag InOperandList = !con(T2ThreeReg:iops, (ins pred:$p));
  string AsmString = !strconcat(T2ThreeReg:opc, !strconcat("${p}", T2ThreeReg:asm));
  list<dag> Pattern = T2ThreeReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2ThreeReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2ThreeRegNoP<dag T2ThreeRegNoP:oops = ?, dag T2ThreeRegNoP:iops = ?, InstrItinClass T2ThreeRegNoP:itin = ?, string T2ThreeRegNoP:asm = ?, list<dag> T2ThreeRegNoP:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ?, ?, ?, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2ThreeRegNoP:oops;
  dag InOperandList = T2ThreeRegNoP:iops;
  string AsmString = T2ThreeRegNoP:asm;
  list<dag> Pattern = T2ThreeRegNoP:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2ThreeRegNoP:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2ThreeRegSMUL<bits<3> T2ThreeRegSMUL:op22_20 = { ?, ?, ? }, bits<2> T2ThreeRegSMUL:op5_4 = { ?, ? }, string T2ThreeRegSMUL:opc = ?, list<dag> T2ThreeRegSMUL:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, T2ThreeRegSMUL:op22_20{2}, T2ThreeRegSMUL:op22_20{1}, T2ThreeRegSMUL:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, T2ThreeRegSMUL:op5_4{1}, T2ThreeRegSMUL:op5_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = !strconcat(T2ThreeRegSMUL:opc, "${p}	$Rd, $Rn, $Rm");
  list<dag> Pattern = T2ThreeRegSMUL:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2ThreeReg_mac<bit T2ThreeReg_mac:long = ?, bits<3> T2ThreeReg_mac:op22_20 = { ?, ?, ? }, bits<4> T2ThreeReg_mac:op7_4 = { ?, ?, ?, ? }, dag T2ThreeReg_mac:oops = ?, dag T2ThreeReg_mac:iops = ?, InstrItinClass T2ThreeReg_mac:itin = ?, string T2ThreeReg_mac:opc = ?, string T2ThreeReg_mac:asm = ?, list<dag> T2ThreeReg_mac:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, T2ThreeReg_mac:long, T2ThreeReg_mac:op22_20{2}, T2ThreeReg_mac:op22_20{1}, T2ThreeReg_mac:op22_20{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ?, ?, ?, Rd{3}, Rd{2}, Rd{1}, Rd{0}, T2ThreeReg_mac:op7_4{3}, T2ThreeReg_mac:op7_4{2}, T2ThreeReg_mac:op7_4{1}, T2ThreeReg_mac:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2ThreeReg_mac:oops;
  dag InOperandList = !con(T2ThreeReg_mac:iops, (ins pred:$p));
  string AsmString = !strconcat(T2ThreeReg_mac:opc, !strconcat("${p}", T2ThreeReg_mac:asm));
  list<dag> Pattern = T2ThreeReg_mac:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2ThreeReg_mac:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2TwoReg<dag T2TwoReg:oops = ?, dag T2TwoReg:iops = ?, InstrItinClass T2TwoReg:itin = ?, string T2TwoReg:opc = ?, string T2TwoReg:asm = ?, list<dag> T2TwoReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2TwoReg:oops;
  dag InOperandList = !con(T2TwoReg:iops, (ins pred:$p));
  string AsmString = !strconcat(T2TwoReg:opc, !strconcat("${p}", T2TwoReg:asm));
  list<dag> Pattern = T2TwoReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2TwoReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2TwoRegBitFI<dag T2TwoRegBitFI:oops = ?, dag T2TwoRegBitFI:iops = ?, InstrItinClass T2TwoRegBitFI:itin = ?, string T2TwoRegBitFI:opc = ?, string T2TwoRegBitFI:asm = ?, list<dag> T2TwoRegBitFI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2BitFI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, lsb{4}, lsb{3}, lsb{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, lsb{1}, lsb{0}, ?, msb{4}, msb{3}, msb{2}, msb{1}, msb{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2TwoRegBitFI:oops;
  dag InOperandList = !con(T2TwoRegBitFI:iops, (ins pred:$p));
  string AsmString = !strconcat(T2TwoRegBitFI:opc, !strconcat("${p}", T2TwoRegBitFI:asm));
  list<dag> Pattern = T2TwoRegBitFI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2TwoRegBitFI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<5> msb = { ?, ?, ?, ?, ? };
  bits<5> lsb = { ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2TwoRegCmp<dag T2TwoRegCmp:oops = ?, dag T2TwoRegCmp:iops = ?, InstrItinClass T2TwoRegCmp:itin = ?, string T2TwoRegCmp:opc = ?, string T2TwoRegCmp:asm = ?, list<dag> T2TwoRegCmp:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2TwoRegCmp:oops;
  dag InOperandList = !con(T2TwoRegCmp:iops, (ins pred:$p));
  string AsmString = !strconcat(T2TwoRegCmp:opc, !strconcat("${p}", T2TwoRegCmp:asm));
  list<dag> Pattern = T2TwoRegCmp:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2TwoRegCmp:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2TwoRegImm<dag T2TwoRegImm:oops = ?, dag T2TwoRegImm:iops = ?, InstrItinClass T2TwoRegImm:itin = ?, string T2TwoRegImm:opc = ?, string T2TwoRegImm:asm = ?, list<dag> T2TwoRegImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, imm{11}, ?, ?, ?, ?, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2TwoRegImm:oops;
  dag InOperandList = !con(T2TwoRegImm:iops, (ins pred:$p));
  string AsmString = !strconcat(T2TwoRegImm:opc, !strconcat("${p}", T2TwoRegImm:asm));
  list<dag> Pattern = T2TwoRegImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2TwoRegImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2TwoRegShiftImm<dag T2TwoRegShiftImm:oops = ?, dag T2TwoRegShiftImm:iops = ?, InstrItinClass T2TwoRegShiftImm:itin = ?, string T2TwoRegShiftImm:opc = ?, string T2TwoRegShiftImm:asm = ?, list<dag> T2TwoRegShiftImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, imm{4}, imm{3}, imm{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{1}, imm{0}, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2TwoRegShiftImm:oops;
  dag InOperandList = !con(T2TwoRegShiftImm:iops, (ins pred:$p));
  string AsmString = !strconcat(T2TwoRegShiftImm:opc, !strconcat("${p}", T2TwoRegShiftImm:asm));
  list<dag> Pattern = T2TwoRegShiftImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2TwoRegShiftImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> imm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2TwoRegShiftedReg<dag T2TwoRegShiftedReg:oops = ?, dag T2TwoRegShiftedReg:iops = ?, InstrItinClass T2TwoRegShiftedReg:itin = ?, string T2TwoRegShiftedReg:opc = ?, string T2TwoRegShiftedReg:asm = ?, list<dag> T2TwoRegShiftedReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2TwoRegShiftedReg:oops;
  dag InOperandList = !con(T2TwoRegShiftedReg:iops, (ins pred:$p));
  string AsmString = !strconcat(T2TwoRegShiftedReg:opc, !strconcat("${p}", T2TwoRegShiftedReg:asm));
  list<dag> Pattern = T2TwoRegShiftedReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2TwoRegShiftedReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2XI<dag T2XI:oops = ?, dag T2XI:iops = ?, InstrItinClass T2XI:itin = ?, string T2XI:asm = ?, list<dag> T2XI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2XI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2XI:oops;
  dag InOperandList = T2XI:iops;
  string AsmString = T2XI:asm;
  list<dag> Pattern = T2XI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2XI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2XIt<dag T2XIt:oops = ?, dag T2XIt:iops = ?, InstrItinClass T2XIt:itin = ?, string T2XIt:asm = ?, string T2XIt:cstr = ?, list<dag> T2XIt:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2XI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2XIt:oops;
  dag InOperandList = T2XIt:iops;
  string AsmString = T2XIt:asm;
  list<dag> Pattern = T2XIt:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2XIt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = T2XIt:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class T2sI<dag T2sI:oops = ?, dag T2sI:iops = ?, InstrItinClass T2sI:itin = ?, string T2sI:opc = ?, string T2sI:asm = ?, list<dag> T2sI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2sI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, s{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2sI:oops;
  dag InOperandList = !con(T2sI:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(T2sI:opc, !strconcat("${s}${p}", T2sI:asm));
  list<dag> Pattern = T2sI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2sI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  string NAME = ?;
}
class T2sOneRegImm<dag T2sOneRegImm:oops = ?, dag T2sOneRegImm:iops = ?, InstrItinClass T2sOneRegImm:itin = ?, string T2sOneRegImm:opc = ?, string T2sOneRegImm:asm = ?, list<dag> T2sOneRegImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI
  field bits<32> Inst = { ?, ?, ?, ?, ?, imm{11}, ?, ?, ?, ?, ?, s{0}, ?, ?, ?, ?, ?, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2sOneRegImm:oops;
  dag InOperandList = !con(T2sOneRegImm:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(T2sOneRegImm:opc, !strconcat("${s}${p}", T2sOneRegImm:asm));
  list<dag> Pattern = T2sOneRegImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2sOneRegImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2sOneRegShiftedReg<dag T2sOneRegShiftedReg:oops = ?, dag T2sOneRegShiftedReg:iops = ?, InstrItinClass T2sOneRegShiftedReg:itin = ?, string T2sOneRegShiftedReg:opc = ?, string T2sOneRegShiftedReg:asm = ?, list<dag> T2sOneRegShiftedReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, s{0}, ?, ?, ?, ?, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2sOneRegShiftedReg:oops;
  dag InOperandList = !con(T2sOneRegShiftedReg:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(T2sOneRegShiftedReg:opc, !strconcat("${s}${p}", T2sOneRegShiftedReg:asm));
  list<dag> Pattern = T2sOneRegShiftedReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2sOneRegShiftedReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2sThreeReg<dag T2sThreeReg:oops = ?, dag T2sThreeReg:iops = ?, InstrItinClass T2sThreeReg:itin = ?, string T2sThreeReg:opc = ?, string T2sThreeReg:asm = ?, list<dag> T2sThreeReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ?, ?, ?, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2sThreeReg:oops;
  dag InOperandList = !con(T2sThreeReg:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(T2sThreeReg:opc, !strconcat("${s}${p}", T2sThreeReg:asm));
  list<dag> Pattern = T2sThreeReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2sThreeReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2sTwoReg<dag T2sTwoReg:oops = ?, dag T2sTwoReg:iops = ?, InstrItinClass T2sTwoReg:itin = ?, string T2sTwoReg:opc = ?, string T2sTwoReg:asm = ?, list<dag> T2sTwoReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, s{0}, ?, ?, ?, ?, ?, ?, ?, ?, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2sTwoReg:oops;
  dag InOperandList = !con(T2sTwoReg:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(T2sTwoReg:opc, !strconcat("${s}${p}", T2sTwoReg:asm));
  list<dag> Pattern = T2sTwoReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2sTwoReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class T2sTwoRegImm<dag T2sTwoRegImm:oops = ?, dag T2sTwoRegImm:iops = ?, InstrItinClass T2sTwoRegImm:itin = ?, string T2sTwoRegImm:opc = ?, string T2sTwoRegImm:asm = ?, list<dag> T2sTwoRegImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI
  field bits<32> Inst = { ?, ?, ?, ?, ?, imm{11}, ?, ?, ?, ?, ?, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2sTwoRegImm:oops;
  dag InOperandList = !con(T2sTwoRegImm:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(T2sTwoRegImm:opc, !strconcat("${s}${p}", T2sTwoRegImm:asm));
  list<dag> Pattern = T2sTwoRegImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2sTwoRegImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2sTwoRegShiftImm<dag T2sTwoRegShiftImm:oops = ?, dag T2sTwoRegShiftImm:iops = ?, InstrItinClass T2sTwoRegShiftImm:itin = ?, string T2sTwoRegShiftImm:opc = ?, string T2sTwoRegShiftImm:asm = ?, list<dag> T2sTwoRegShiftImm:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, s{0}, ?, ?, ?, ?, ?, imm{4}, imm{3}, imm{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{1}, imm{0}, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2sTwoRegShiftImm:oops;
  dag InOperandList = !con(T2sTwoRegShiftImm:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(T2sTwoRegShiftImm:opc, !strconcat("${s}${p}", T2sTwoRegShiftImm:asm));
  list<dag> Pattern = T2sTwoRegShiftImm:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2sTwoRegShiftImm:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> imm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2sTwoRegShiftedReg<dag T2sTwoRegShiftedReg:oops = ?, dag T2sTwoRegShiftedReg:iops = ?, InstrItinClass T2sTwoRegShiftedReg:itin = ?, string T2sTwoRegShiftedReg:opc = ?, string T2sTwoRegShiftedReg:asm = ?, list<dag> T2sTwoRegShiftedReg:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = T2sTwoRegShiftedReg:oops;
  dag InOperandList = !con(T2sTwoRegShiftedReg:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(T2sTwoRegShiftedReg:opc, !strconcat("${s}${p}", T2sTwoRegShiftedReg:asm));
  list<dag> Pattern = T2sTwoRegShiftedReg:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = T2sTwoRegShiftedReg:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
class T2v6Pat<dag T2v6Pat:pattern = ?, dag T2v6Pat:result = ?> {	// Pattern Pat
  dag PatternToMatch = T2v6Pat:pattern;
  list<dag> ResultInstrs = [T2v6Pat:result];
  list<Predicate> Predicates = [IsThumb2, HasV6T2];
  int AddedComplexity = 0;
  string NAME = ?;
}
class TI<dag TI:oops = ?, dag TI:iops = ?, InstrItinClass TI:itin = ?, string TI:asm = ?, list<dag> TI:pattern = ?> {	// Instruction InstTemplate InstThumb ThumbI
  string Namespace = "ARM";
  dag OutOperandList = TI:oops;
  dag InOperandList = TI:iops;
  string AsmString = TI:asm;
  list<dag> Pattern = TI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = TI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class TIt<dag TIt:oops = ?, dag TIt:iops = ?, InstrItinClass TIt:itin = ?, string TIt:asm = ?, list<dag> TIt:pattern = ?> {	// Instruction InstTemplate InstThumb ThumbI
  string Namespace = "ARM";
  dag OutOperandList = TIt:oops;
  dag InOperandList = TIt:iops;
  string AsmString = TIt:asm;
  list<dag> Pattern = TIt:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = TIt:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$lhs = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class TIx2<bits<5> TIx2:opcod1 = { ?, ?, ?, ?, ? }, bits<2> TIx2:opcod2 = { ?, ? }, bit TIx2:opcod3 = ?, dag TIx2:oops = ?, dag TIx2:iops = ?, InstrItinClass TIx2:itin = ?, string TIx2:asm = ?, list<dag> TIx2:pattern = ?> {	// Instruction InstTemplate InstThumb ThumbI Encoding
  field bits<32> Inst = { TIx2:opcod1{4}, TIx2:opcod1{3}, TIx2:opcod1{2}, TIx2:opcod1{1}, TIx2:opcod1{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, TIx2:opcod2{1}, TIx2:opcod2{0}, ?, TIx2:opcod3, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = TIx2:oops;
  dag InOperandList = TIx2:iops;
  string AsmString = TIx2:asm;
  list<dag> Pattern = TIx2:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 4;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = TIx2:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class TJTI<dag TJTI:oops = ?, dag TJTI:iops = ?, InstrItinClass TJTI:itin = ?, string TJTI:asm = ?, list<dag> TJTI:pattern = ?> {	// Instruction InstTemplate InstThumb ThumbI
  string Namespace = "ARM";
  dag OutOperandList = TJTI:oops;
  dag InOperandList = TJTI:iops;
  string AsmString = TJTI:asm;
  list<dag> Pattern = TJTI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 0;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = TJTI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class Target {
  InstrInfo InstructionSet = ?;
  list<AsmParser> AssemblyParsers = [DefaultAsmParser];
  list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
  list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
  int AllowRegisterRenaming = 0;
  string NAME = ?;
}
class Thumb1I<dag Thumb1I:oops = ?, dag Thumb1I:iops = ?, AddrMode Thumb1I:am = ?, int Thumb1I:sz = ?, InstrItinClass Thumb1I:itin = ?, string Thumb1I:asm = ?, string Thumb1I:cstr = ?, list<dag> Thumb1I:pattern = ?> {	// Instruction InstTemplate InstThumb
  string Namespace = "ARM";
  dag OutOperandList = Thumb1I:oops;
  dag InOperandList = Thumb1I:iops;
  string AsmString = Thumb1I:asm;
  list<dag> Pattern = Thumb1I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = Thumb1I:sz;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = Thumb1I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = Thumb1I:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = Thumb1I:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class Thumb1pI<dag Thumb1pI:oops = ?, dag Thumb1pI:iops = ?, AddrMode Thumb1pI:am = ?, int Thumb1pI:sz = ?, InstrItinClass Thumb1pI:itin = ?, string Thumb1pI:opc = ?, string Thumb1pI:asm = ?, string Thumb1pI:cstr = ?, list<dag> Thumb1pI:pattern = ?> {	// Instruction InstTemplate InstThumb
  string Namespace = "ARM";
  dag OutOperandList = Thumb1pI:oops;
  dag InOperandList = !con(Thumb1pI:iops, (ins pred:$p));
  string AsmString = !strconcat(Thumb1pI:opc, !strconcat("${p}", Thumb1pI:asm));
  list<dag> Pattern = Thumb1pI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = Thumb1pI:sz;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = Thumb1pI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = Thumb1pI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = Thumb1pI:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class Thumb1sI<dag Thumb1sI:oops = ?, dag Thumb1sI:iops = ?, AddrMode Thumb1sI:am = ?, int Thumb1sI:sz = ?, InstrItinClass Thumb1sI:itin = ?, string Thumb1sI:opc = ?, string Thumb1sI:asm = ?, string Thumb1sI:cstr = ?, list<dag> Thumb1sI:pattern = ?> {	// Instruction InstTemplate InstThumb
  string Namespace = "ARM";
  dag OutOperandList = !con(Thumb1sI:oops, (outs s_cc_out:$s));
  dag InOperandList = !con(Thumb1sI:iops, (ins pred:$p));
  string AsmString = !strconcat(Thumb1sI:opc, !strconcat("${s}${p}", Thumb1sI:asm));
  list<dag> Pattern = Thumb1sI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = Thumb1sI:sz;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = Thumb1sI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = Thumb1sI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = Thumb1sI:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  string NAME = ?;
}
class Thumb2DSPMulPat<dag Thumb2DSPMulPat:pattern = ?, dag Thumb2DSPMulPat:result = ?> {	// Pattern Pat
  dag PatternToMatch = Thumb2DSPMulPat:pattern;
  list<dag> ResultInstrs = [Thumb2DSPMulPat:result];
  list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class Thumb2DSPPat<dag Thumb2DSPPat:pattern = ?, dag Thumb2DSPPat:result = ?> {	// Pattern Pat
  dag PatternToMatch = Thumb2DSPPat:pattern;
  list<dag> ResultInstrs = [Thumb2DSPPat:result];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class Thumb2I<dag Thumb2I:oops = ?, dag Thumb2I:iops = ?, AddrMode Thumb2I:am = ?, int Thumb2I:sz = ?, InstrItinClass Thumb2I:itin = ?, string Thumb2I:opc = ?, string Thumb2I:asm = ?, string Thumb2I:cstr = ?, list<dag> Thumb2I:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = Thumb2I:oops;
  dag InOperandList = !con(Thumb2I:iops, (ins pred:$p));
  string AsmString = !strconcat(Thumb2I:opc, !strconcat("${p}", Thumb2I:asm));
  list<dag> Pattern = Thumb2I:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = Thumb2I:sz;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = Thumb2I:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = Thumb2I:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = Thumb2I:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class Thumb2XI<dag Thumb2XI:oops = ?, dag Thumb2XI:iops = ?, AddrMode Thumb2XI:am = ?, int Thumb2XI:sz = ?, InstrItinClass Thumb2XI:itin = ?, string Thumb2XI:asm = ?, string Thumb2XI:cstr = ?, list<dag> Thumb2XI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = Thumb2XI:oops;
  dag InOperandList = Thumb2XI:iops;
  string AsmString = Thumb2XI:asm;
  list<dag> Pattern = Thumb2XI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = Thumb2XI:sz;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = Thumb2XI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = Thumb2XI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = Thumb2XI:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class Thumb2sI<dag Thumb2sI:oops = ?, dag Thumb2sI:iops = ?, AddrMode Thumb2sI:am = ?, int Thumb2sI:sz = ?, InstrItinClass Thumb2sI:itin = ?, string Thumb2sI:opc = ?, string Thumb2sI:asm = ?, string Thumb2sI:cstr = ?, list<dag> Thumb2sI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, s{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = Thumb2sI:oops;
  dag InOperandList = !con(Thumb2sI:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(Thumb2sI:opc, !strconcat("${s}${p}", Thumb2sI:asm));
  list<dag> Pattern = Thumb2sI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = Thumb2sI:sz;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = Thumb2sI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = Thumb2sI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = Thumb2sI:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  string NAME = ?;
}
class ThumbI<dag ThumbI:oops = ?, dag ThumbI:iops = ?, AddrMode ThumbI:am = ?, int ThumbI:sz = ?, InstrItinClass ThumbI:itin = ?, string ThumbI:asm = ?, string ThumbI:cstr = ?, list<dag> ThumbI:pattern = ?> {	// Instruction InstTemplate InstThumb
  string Namespace = "ARM";
  dag OutOperandList = ThumbI:oops;
  dag InOperandList = ThumbI:iops;
  string AsmString = ThumbI:asm;
  list<dag> Pattern = ThumbI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = ThumbI:sz;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ThumbI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = ThumbI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = ThumbI:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class ThumbXI<dag ThumbXI:oops = ?, dag ThumbXI:iops = ?, AddrMode ThumbXI:am = ?, int ThumbXI:sz = ?, InstrItinClass ThumbXI:itin = ?, string ThumbXI:asm = ?, string ThumbXI:cstr = ?, list<dag> ThumbXI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = ThumbXI:oops;
  dag InOperandList = ThumbXI:iops;
  string AsmString = ThumbXI:asm;
  list<dag> Pattern = ThumbXI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = ThumbXI:sz;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = ThumbXI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = ThumbXI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = ThumbXI:am;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class TokenAlias<string TokenAlias:From = ?, string TokenAlias:To = ?> {
  string FromToken = TokenAlias:From;
  string ToToken = TokenAlias:To;
  string NAME = ?;
}
class TypedOperand<string TypedOperand:Ty = ?> {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = TypedOperand:Ty;
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 0;
  string NAME = ?;
}
class UnOpFrag<dag UnOpFrag:res = ?> {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$Src);
  dag Fragment = UnOpFrag:res;
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
class UnaryDP {
  bit isUnaryDataProc = 1;
  string NAME = ?;
}
class VDOT<bit VDOT:op6 = ?, bit VDOT:op4 = ?, RegisterClass VDOT:RegTy = ?, string VDOT:Asm = ?, string VDOT:AsmTy = ?, ValueType VDOT:AccumTy = ?, ValueType VDOT:InputTy = ?, SDPatternOperator VDOT:OpNode = ?> {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, VDOT:op6, Vm{4}, VDOT:op4, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs VDOT:RegTy:$dst);
  dag InOperandList = (ins VDOT:RegTy:$Vd, VDOT:RegTy:$Vn, VDOT:RegTy:$Vm);
  string AsmString = !strconcat(VDOT:Asm, !strconcat(".", !strconcat(VDOT:AsmTy, "	$Vd, $Vn, $Vm")));
  list<dag> Pattern = [(set (VDOT:AccumTy VDOT:RegTy:$dst), (VDOT:OpNode (VDOT:AccumTy VDOT:RegTy:$Vd), (VDOT:InputTy VDOT:RegTy:$Vn), (VDOT:InputTy VDOT:RegTy:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDotProd];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VDOTPROD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$dst = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N3RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VDUPD<bits<8> VDUPD:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<2> VDUPD:opcod3 = { ?, ? }, string VDUPD:Dt = ?, ValueType VDUPD:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVDup
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, VDUPD:opcod1{7}, VDUPD:opcod1{6}, VDUPD:opcod1{5}, VDUPD:opcod1{4}, VDUPD:opcod1{3}, VDUPD:opcod1{2}, VDUPD:opcod1{1}, VDUPD:opcod1{0}, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, VDUPD:opcod3{1}, VDUPD:opcod3{0}, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$V);
  dag InOperandList = (ins GPR:$R, pred:$p);
  string AsmString = !strconcat("vdup", !strconcat("${p}", !strconcat(".", !strconcat(VDUPD:Dt, "	$V, $R"))));
  list<dag> Pattern = [(set DPR:$V, (VDUPD:Ty (NEONvdup (i32 GPR:$R))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVIS;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NDupFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
class VDUPLND<bits<4> VDUPLND:op19_16 = { ?, ?, ?, ? }, string VDUPLND:OpcodeStr = ?, string VDUPLND:Dt = ?, ValueType VDUPLND:Ty = ?, Operand VDUPLND:IdxTy = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI NVDupLane
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VDUPLND:op19_16{3}, VDUPLND:op19_16{2}, VDUPLND:op19_16{1}, VDUPLND:op19_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, VDUPLND:IdxTy:$lane, pred:$p);
  string AsmString = !strconcat(VDUPLND:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VDUPLND:Dt, "	$Vd, $Vm$lane"))));
  list<dag> Pattern = [(set DPR:$Vd, (VDUPLND:Ty (NEONvduplane (VDUPLND:Ty DPR:$Vm), imm:$lane)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVDupLnFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VDUPLNQ<bits<4> VDUPLNQ:op19_16 = { ?, ?, ?, ? }, string VDUPLNQ:OpcodeStr = ?, string VDUPLNQ:Dt = ?, ValueType VDUPLNQ:ResTy = ?, ValueType VDUPLNQ:OpTy = ?, Operand VDUPLNQ:IdxTy = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI NVDupLane
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VDUPLNQ:op19_16{3}, VDUPLNQ:op19_16{2}, VDUPLNQ:op19_16{1}, VDUPLNQ:op19_16{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, VDUPLNQ:IdxTy:$lane, pred:$p);
  string AsmString = !strconcat(VDUPLNQ:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VDUPLNQ:Dt, "	$Vd, $Vm$lane"))));
  list<dag> Pattern = [(set QPR:$Vd, (VDUPLNQ:ResTy (NEONvduplane (VDUPLNQ:OpTy DPR:$Vm), VectorIndex32:$lane)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVDupLnFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VDUPQ<bits<8> VDUPQ:opcod1 = { ?, ?, ?, ?, ?, ?, ?, ? }, bits<2> VDUPQ:opcod3 = { ?, ? }, string VDUPQ:Dt = ?, ValueType VDUPQ:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVDup
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, VDUPQ:opcod1{7}, VDUPQ:opcod1{6}, VDUPQ:opcod1{5}, VDUPQ:opcod1{4}, VDUPQ:opcod1{3}, VDUPQ:opcod1{2}, VDUPQ:opcod1{1}, VDUPQ:opcod1{0}, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, VDUPQ:opcod3{1}, VDUPQ:opcod3{0}, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$V);
  dag InOperandList = (ins GPR:$R, pred:$p);
  string AsmString = !strconcat("vdup", !strconcat("${p}", !strconcat(".", !strconcat(VDUPQ:Dt, "	$V, $R"))));
  list<dag> Pattern = [(set QPR:$V, (VDUPQ:Ty (NEONvdup (i32 GPR:$R))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVIS;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NDupFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
class VEXTd<string VEXTd:OpcodeStr = ?, string VEXTd:Dt = ?, ValueType VEXTd:Ty = ?, Operand VEXTd:immTy = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, index{2}, index{1}, index{0}, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, VEXTd:immTy:$index, pred:$p);
  string AsmString = !strconcat(VEXTd:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VEXTd:Dt, "	$Vd, $Vn, $Vm, $index"))));
  list<dag> Pattern = [(set DPR:$Vd, (VEXTd:Ty (NEONvext (VEXTd:Ty DPR:$Vn), (VEXTd:Ty DPR:$Vm), imm:$index)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VEXTD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVExtFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<3> index = { ?, ?, ? };
  string NAME = ?;
}
class VEXTq<string VEXTq:OpcodeStr = ?, string VEXTq:Dt = ?, ValueType VEXTq:Ty = ?, Operand VEXTq:immTy = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, index{3}, index{2}, index{1}, index{0}, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, imm0_15:$index, pred:$p);
  string AsmString = !strconcat(VEXTq:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VEXTq:Dt, "	$Vd, $Vn, $Vm, $index"))));
  list<dag> Pattern = [(set QPR:$Vd, (VEXTq:Ty (NEONvext (VEXTq:Ty QPR:$Vn), (VEXTq:Ty QPR:$Vm), imm:$index)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VEXTQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NVExtFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<4> index = { ?, ?, ?, ? };
  string NAME = ?;
}
class VFP2AsmPseudo<string VFP2AsmPseudo:asm = ?, dag VFP2AsmPseudo:iops = ?, dag VFP2AsmPseudo:oops = (outs)> {	// Instruction InstTemplate AsmPseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = VFP2AsmPseudo:oops;
  dag InOperandList = VFP2AsmPseudo:iops;
  string AsmString = VFP2AsmPseudo:asm;
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VFP2DPInstAlias<string VFP2DPInstAlias:Asm = ?, dag VFP2DPInstAlias:Result = ?, bit VFP2DPInstAlias:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = VFP2DPInstAlias:Asm;
  dag ResultInst = VFP2DPInstAlias:Result;
  int EmitPriority = !cast<int>(VFP2DPInstAlias:EmitPriority);
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class VFP2InstAlias<string VFP2InstAlias:Asm = ?, dag VFP2InstAlias:Result = ?, bit VFP2InstAlias:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = VFP2InstAlias:Asm;
  dag ResultInst = VFP2InstAlias:Result;
  int EmitPriority = !cast<int>(VFP2InstAlias:EmitPriority);
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class VFP2MnemonicAlias<string VFP2MnemonicAlias:src = ?, string VFP2MnemonicAlias:dst = ?> {	// MnemonicAlias Requires
  string FromMnemonic = VFP2MnemonicAlias:src;
  string ToMnemonic = VFP2MnemonicAlias:dst;
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
class VFP3InstAlias<string VFP3InstAlias:Asm = ?, dag VFP3InstAlias:Result = ?, bit VFP3InstAlias:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = VFP3InstAlias:Asm;
  dag ResultInst = VFP3InstAlias:Result;
  int EmitPriority = !cast<int>(VFP3InstAlias:EmitPriority);
  list<Predicate> Predicates = [HasVFP3];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class VFPAI<dag VFPAI:oops = ?, dag VFPAI:iops = ?, Format VFPAI:f = ?, InstrItinClass VFPAI:itin = ?, string VFPAI:opc = ?, string VFPAI:asm = ?, list<dag> VFPAI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM VFPI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = VFPAI:oops;
  dag InOperandList = !con(VFPAI:iops, (ins pred:$p));
  string AsmString = !strconcat(VFPAI:opc, !strconcat("${p}", VFPAI:asm));
  list<dag> Pattern = VFPAI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(VFPAI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VFPAI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPAI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class VFPDataTypeInstAlias<string VFPDataTypeInstAlias:opc = ?, string VFPDataTypeInstAlias:dt = ?, string VFPDataTypeInstAlias:asm = ?, dag VFPDataTypeInstAlias:Result = ?, bit VFPDataTypeInstAlias:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = !strconcat(VFPDataTypeInstAlias:opc, !strconcat(VFPDataTypeInstAlias:dt, !strconcat("	", VFPDataTypeInstAlias:asm)));
  dag ResultInst = VFPDataTypeInstAlias:Result;
  int EmitPriority = !cast<int>(VFPDataTypeInstAlias:EmitPriority);
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class VFPI<dag VFPI:oops = ?, dag VFPI:iops = ?, AddrMode VFPI:am = ?, int VFPI:sz = ?, IndexMode VFPI:im = ?, Format VFPI:f = ?, InstrItinClass VFPI:itin = ?, string VFPI:opc = ?, string VFPI:asm = ?, string VFPI:cstr = ?, list<dag> VFPI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = VFPI:oops;
  dag InOperandList = !con(VFPI:iops, (ins pred:$p));
  string AsmString = !strconcat(VFPI:opc, !strconcat("${p}", VFPI:asm));
  list<dag> Pattern = VFPI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = VFPI:sz;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(VFPI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VFPI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = VFPI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = VFPI:am;
  IndexMode IM = VFPI:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class VFPNoNEONPat<dag VFPNoNEONPat:pattern = ?, dag VFPNoNEONPat:result = ?> {	// Pattern Pat
  dag PatternToMatch = VFPNoNEONPat:pattern;
  list<dag> ResultInstrs = [VFPNoNEONPat:result];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
class VFPPat<dag VFPPat:pattern = ?, dag VFPPat:result = ?> {	// Pattern Pat
  dag PatternToMatch = VFPPat:pattern;
  list<dag> ResultInstrs = [VFPPat:result];
  list<Predicate> Predicates = [HasVFP2];
  int AddedComplexity = 0;
  string NAME = ?;
}
class VFPXI<dag VFPXI:oops = ?, dag VFPXI:iops = ?, AddrMode VFPXI:am = ?, int VFPXI:sz = ?, IndexMode VFPXI:im = ?, Format VFPXI:f = ?, InstrItinClass VFPXI:itin = ?, string VFPXI:asm = ?, string VFPXI:cstr = ?, list<dag> VFPXI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = VFPXI:oops;
  dag InOperandList = VFPXI:iops;
  string AsmString = VFPXI:asm;
  list<dag> Pattern = VFPXI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = VFPXI:sz;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(VFPXI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VFPXI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = VFPXI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = VFPXI:am;
  IndexMode IM = VFPXI:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = VFPXI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
class VLD1D<bits<4> VLD1D:op7_4 = { ?, ?, ?, ? }, string VLD1D:Dt = ?, Operand VLD1D:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, VLD1D:op7_4{3}, VLD1D:op7_4{2}, VLD1D:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd);
  dag InOperandList = (ins VLD1D:AddrMode:$Rn, pred:$p);
  string AsmString = !strconcat("vld1", !strconcat("${p}", !strconcat(".", !strconcat(VLD1D:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD1D3<bits<4> VLD1D3:op7_4 = { ?, ?, ?, ? }, string VLD1D3:Dt = ?, Operand VLD1D3:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, VLD1D3:op7_4{3}, VLD1D3:op7_4{2}, VLD1D3:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd);
  dag InOperandList = (ins VLD1D3:AddrMode:$Rn, pred:$p);
  string AsmString = !strconcat("vld1", !strconcat("${p}", !strconcat(".", !strconcat(VLD1D3:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD1D4<bits<4> VLD1D4:op7_4 = { ?, ?, ?, ? }, string VLD1D4:Dt = ?, Operand VLD1D4:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, VLD1D4:op7_4{3}, VLD1D4:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd);
  dag InOperandList = (ins VLD1D4:AddrMode:$Rn, pred:$p);
  string AsmString = !strconcat("vld1", !strconcat("${p}", !strconcat(".", !strconcat(VLD1D4:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD1DUP<bits<4> VLD1DUP:op7_4 = { ?, ?, ?, ? }, string VLD1DUP:Dt = ?, ValueType VLD1DUP:Ty = ?, PatFrag VLD1DUP:LoadOp = ?, Operand VLD1DUP:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, VLD1DUP:op7_4{3}, VLD1DUP:op7_4{2}, VLD1DUP:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd);
  dag InOperandList = (ins VLD1DUP:AddrMode:$Rn, pred:$p);
  string AsmString = !strconcat("vld1", !strconcat("${p}", !strconcat(".", !strconcat(VLD1DUP:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [(set VecListOneDAllLanes:$Vd, (VLD1DUP:Ty (NEONvdup (i32 (VLD1DUP:LoadOp VLD1DUP:AddrMode:$Rn)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD1LN<bits<4> VLD1LN:op11_8 = { ?, ?, ?, ? }, bits<4> VLD1LN:op7_4 = { ?, ?, ?, ? }, string VLD1LN:Dt = ?, ValueType VLD1LN:Ty = ?, PatFrag VLD1LN:LoadOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD1LN:op11_8{3}, VLD1LN:op11_8{2}, VLD1LN:op11_8{1}, VLD1LN:op11_8{0}, VLD1LN:op7_4{3}, VLD1LN:op7_4{2}, VLD1LN:op7_4{1}, VLD1LN:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vld1", !strconcat("${p}", !strconcat(".", !strconcat(VLD1LN:Dt, "	\{$Vd[$lane]\}, $Rn"))));
  list<dag> Pattern = [(set DPR:$Vd, (vector_insert (VLD1LN:Ty DPR:$src), (i32 (VLD1LN:LoadOp addrmode6:$Rn)), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1ln;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VLD1LN32<bits<4> VLD1LN32:op11_8 = { ?, ?, ?, ? }, bits<4> VLD1LN32:op7_4 = { ?, ?, ?, ? }, string VLD1LN32:Dt = ?, ValueType VLD1LN32:Ty = ?, PatFrag VLD1LN32:LoadOp = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD1LN32:op11_8{3}, VLD1LN32:op11_8{2}, VLD1LN32:op11_8{1}, VLD1LN32:op11_8{0}, VLD1LN32:op7_4{3}, VLD1LN32:op7_4{2}, VLD1LN32:op7_4{1}, VLD1LN32:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vld1", !strconcat("${p}", !strconcat(".", !strconcat(VLD1LN32:Dt, "	\{$Vd[$lane]\}, $Rn"))));
  list<dag> Pattern = [(set DPR:$Vd, (vector_insert (VLD1LN32:Ty DPR:$src), (i32 (VLD1LN32:LoadOp addrmode6oneL32:$Rn)), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VLD1LNWB<bits<4> VLD1LNWB:op11_8 = { ?, ?, ?, ? }, bits<4> VLD1LNWB:op7_4 = { ?, ?, ?, ? }, string VLD1LNWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD1LNWB:op11_8{3}, VLD1LNWB:op11_8{2}, VLD1LNWB:op11_8{1}, VLD1LNWB:op11_8{0}, VLD1LNWB:op7_4{3}, VLD1LNWB:op7_4{2}, VLD1LNWB:op7_4{1}, VLD1LNWB:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vld1", !strconcat("${p}", !strconcat(".", !strconcat(VLD1LNWB:Dt, "	\{$Vd[$lane]\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $Vd, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VLD1Q<bits<4> VLD1Q:op7_4 = { ?, ?, ?, ? }, string VLD1Q:Dt = ?, Operand VLD1Q:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, VLD1Q:op7_4{3}, VLD1Q:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd);
  dag InOperandList = (ins VLD1Q:AddrMode:$Rn, pred:$p);
  string AsmString = !strconcat("vld1", !strconcat("${p}", !strconcat(".", !strconcat(VLD1Q:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD1QDUP<bits<4> VLD1QDUP:op7_4 = { ?, ?, ?, ? }, string VLD1QDUP:Dt = ?, ValueType VLD1QDUP:Ty = ?, PatFrag VLD1QDUP:LoadOp = ?, Operand VLD1QDUP:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, VLD1QDUP:op7_4{3}, VLD1QDUP:op7_4{2}, VLD1QDUP:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd);
  dag InOperandList = (ins VLD1QDUP:AddrMode:$Rn, pred:$p);
  string AsmString = !strconcat("vld1", !strconcat("${p}", !strconcat(".", !strconcat(VLD1QDUP:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [(set VecListDPairAllLanes:$Vd, (VLD1QDUP:Ty (NEONvdup (i32 (VLD1QDUP:LoadOp VLD1QDUP:AddrMode:$Rn)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD1QLNPseudo<ValueType VLD1QLNPseudo:Ty = ?, PatFrag VLD1QLNPseudo:LoadOp = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set QPR:$dst, (vector_insert (VLD1QLNPseudo:Ty QPR:$src), (i32 (VLD1QLNPseudo:LoadOp addrmode6:$addr)), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLD2<bits<4> VLD2:op11_8 = { ?, ?, ?, ? }, bits<4> VLD2:op7_4 = { ?, ?, ?, ? }, string VLD2:Dt = ?, RegisterOperand VLD2:VdTy = ?, InstrItinClass VLD2:itin = ?, Operand VLD2:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD2:op11_8{3}, VLD2:op11_8{2}, VLD2:op11_8{1}, VLD2:op11_8{0}, VLD2:op7_4{3}, VLD2:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs VLD2:VdTy:$Vd);
  dag InOperandList = (ins VLD2:AddrMode:$Rn, pred:$p);
  string AsmString = !strconcat("vld2", !strconcat("${p}", !strconcat(".", !strconcat(VLD2:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLD2:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD2DUP<bits<4> VLD2DUP:op7_4 = { ?, ?, ?, ? }, string VLD2DUP:Dt = ?, RegisterOperand VLD2DUP:VdTy = ?, Operand VLD2DUP:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, VLD2DUP:op7_4{3}, VLD2DUP:op7_4{2}, VLD2DUP:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs VLD2DUP:VdTy:$Vd);
  dag InOperandList = (ins VLD2DUP:AddrMode:$Rn, pred:$p);
  string AsmString = !strconcat("vld2", !strconcat("${p}", !strconcat(".", !strconcat(VLD2DUP:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD2LN<bits<4> VLD2LN:op11_8 = { ?, ?, ?, ? }, bits<4> VLD2LN:op7_4 = { ?, ?, ?, ? }, string VLD2LN:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD2LN:op11_8{3}, VLD2LN:op11_8{2}, VLD2LN:op11_8{1}, VLD2LN:op11_8{0}, VLD2LN:op7_4{3}, VLD2LN:op7_4{2}, VLD2LN:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vld2", !strconcat("${p}", !strconcat(".", !strconcat(VLD2LN:Dt, "	\{$Vd[$lane], $dst2[$lane]\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src1 = $Vd, $src2 = $dst2";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VLD2LNWB<bits<4> VLD2LNWB:op11_8 = { ?, ?, ?, ? }, bits<4> VLD2LNWB:op7_4 = { ?, ?, ?, ? }, string VLD2LNWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD2LNWB:op11_8{3}, VLD2LNWB:op11_8{2}, VLD2LNWB:op11_8{1}, VLD2LNWB:op11_8{0}, VLD2LNWB:op7_4{3}, VLD2LNWB:op7_4{2}, VLD2LNWB:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vld2", !strconcat("${p}", !strconcat(".", !strconcat(VLD2LNWB:Dt, "	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VLD3D<bits<4> VLD3D:op11_8 = { ?, ?, ?, ? }, bits<4> VLD3D:op7_4 = { ?, ?, ?, ? }, string VLD3D:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD3D:op11_8{3}, VLD3D:op11_8{2}, VLD3D:op11_8{1}, VLD3D:op11_8{0}, VLD3D:op7_4{3}, VLD3D:op7_4{2}, VLD3D:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = !strconcat("vld3", !strconcat("${p}", !strconcat(".", !strconcat(VLD3D:Dt, "	\{$Vd, $dst2, $dst3\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD3DUP<bits<4> VLD3DUP:op7_4 = { ?, ?, ?, ? }, string VLD3DUP:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, VLD3DUP:op7_4{3}, VLD3DUP:op7_4{2}, VLD3DUP:op7_4{1}, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = !strconcat("vld3", !strconcat("${p}", !strconcat(".", !strconcat(VLD3DUP:Dt, "	\{$Vd[], $dst2[], $dst3[]\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD3DUPWB<bits<4> VLD3DUPWB:op7_4 = { ?, ?, ?, ? }, string VLD3DUPWB:Dt = ?, Operand VLD3DUPWB:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, VLD3DUPWB:op7_4{3}, VLD3DUPWB:op7_4{2}, VLD3DUPWB:op7_4{1}, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins VLD3DUPWB:AddrMode:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = !strconcat("vld3", !strconcat("${p}", !strconcat(".", !strconcat(VLD3DUPWB:Dt, "	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class VLD3DWB<bits<4> VLD3DWB:op11_8 = { ?, ?, ?, ? }, bits<4> VLD3DWB:op7_4 = { ?, ?, ?, ? }, string VLD3DWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD3DWB:op11_8{3}, VLD3DWB:op11_8{2}, VLD3DWB:op11_8{1}, VLD3DWB:op11_8{0}, VLD3DWB:op7_4{3}, VLD3DWB:op7_4{2}, VLD3DWB:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = !strconcat("vld3", !strconcat("${p}", !strconcat(".", !strconcat(VLD3DWB:Dt, "	\{$Vd, $dst2, $dst3\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class VLD3LN<bits<4> VLD3LN:op11_8 = { ?, ?, ?, ? }, bits<4> VLD3LN:op7_4 = { ?, ?, ?, ? }, string VLD3LN:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD3LN:op11_8{3}, VLD3LN:op11_8{2}, VLD3LN:op11_8{1}, VLD3LN:op11_8{0}, VLD3LN:op7_4{3}, VLD3LN:op7_4{2}, VLD3LN:op7_4{1}, VLD3LN:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vld3", !strconcat("${p}", !strconcat(".", !strconcat(VLD3LN:Dt, "	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VLD3LNWB<bits<4> VLD3LNWB:op11_8 = { ?, ?, ?, ? }, bits<4> VLD3LNWB:op7_4 = { ?, ?, ?, ? }, string VLD3LNWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD3LNWB:op11_8{3}, VLD3LNWB:op11_8{2}, VLD3LNWB:op11_8{1}, VLD3LNWB:op11_8{0}, VLD3LNWB:op7_4{3}, VLD3LNWB:op7_4{2}, VLD3LNWB:op7_4{1}, VLD3LNWB:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vld3", !strconcat("${p}", !strconcat(".", !strconcat(VLD3LNWB:Dt, "	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VLD4D<bits<4> VLD4D:op11_8 = { ?, ?, ?, ? }, bits<4> VLD4D:op7_4 = { ?, ?, ?, ? }, string VLD4D:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD4D:op11_8{3}, VLD4D:op11_8{2}, VLD4D:op11_8{1}, VLD4D:op11_8{0}, VLD4D:op7_4{3}, VLD4D:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = !strconcat("vld4", !strconcat("${p}", !strconcat(".", !strconcat(VLD4D:Dt, "	\{$Vd, $dst2, $dst3, $dst4\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD4DUP<bits<4> VLD4DUP:op7_4 = { ?, ?, ?, ? }, string VLD4DUP:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, VLD4DUP:op7_4{3}, VLD4DUP:op7_4{2}, VLD4DUP:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = !strconcat("vld4", !strconcat("${p}", !strconcat(".", !strconcat(VLD4DUP:Dt, "	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VLD4DUPWB<bits<4> VLD4DUPWB:op7_4 = { ?, ?, ?, ? }, string VLD4DUPWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, VLD4DUPWB:op7_4{3}, VLD4DUPWB:op7_4{2}, VLD4DUPWB:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6dup:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = !strconcat("vld4", !strconcat("${p}", !strconcat(".", !strconcat(VLD4DUPWB:Dt, "	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class VLD4DWB<bits<4> VLD4DWB:op11_8 = { ?, ?, ?, ? }, bits<4> VLD4DWB:op7_4 = { ?, ?, ?, ? }, string VLD4DWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD4DWB:op11_8{3}, VLD4DWB:op11_8{2}, VLD4DWB:op11_8{1}, VLD4DWB:op11_8{0}, VLD4DWB:op7_4{3}, VLD4DWB:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = !strconcat("vld4", !strconcat("${p}", !strconcat(".", !strconcat(VLD4DWB:Dt, "	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class VLD4LN<bits<4> VLD4LN:op11_8 = { ?, ?, ?, ? }, bits<4> VLD4LN:op7_4 = { ?, ?, ?, ? }, string VLD4LN:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD4LN:op11_8{3}, VLD4LN:op11_8{2}, VLD4LN:op11_8{1}, VLD4LN:op11_8{0}, VLD4LN:op7_4{3}, VLD4LN:op7_4{2}, VLD4LN:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vld4", !strconcat("${p}", !strconcat(".", !strconcat(VLD4LN:Dt, "	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VLD4LNWB<bits<4> VLD4LNWB:op11_8 = { ?, ?, ?, ? }, bits<4> VLD4LNWB:op7_4 = { ?, ?, ?, ? }, string VLD4LNWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VLD4LNWB:op11_8{3}, VLD4LNWB:op11_8{2}, VLD4LNWB:op11_8{1}, VLD4LNWB:op11_8{0}, VLD4LNWB:op7_4{3}, VLD4LNWB:op7_4{2}, VLD4LNWB:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vld4", !strconcat("${p}", !strconcat(".", !strconcat(VLD4LNWB:Dt, "	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VLDQLNPseudo<InstrItinClass VLDQLNPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQLNPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQLNWBPseudo<InstrItinClass VLDQLNWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQLNWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQPseudo<InstrItinClass VLDQPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQLNPseudo<InstrItinClass VLDQQLNPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQLNPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQLNWBPseudo<InstrItinClass VLDQQLNWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQLNWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQPseudo<InstrItinClass VLDQQPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQQQLNPseudo<InstrItinClass VLDQQQQLNPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQQQLNPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQQQLNWBPseudo<InstrItinClass VLDQQQQLNWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQQQLNWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQQQPseudo<InstrItinClass VLDQQQQPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQQQPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQQQWBPseudo<InstrItinClass VLDQQQQWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQQQWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQWBPseudo<InstrItinClass VLDQQWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQWBfixedPseudo<InstrItinClass VLDQQWBfixedPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQWBfixedPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQQWBregisterPseudo<InstrItinClass VLDQQWBregisterPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQQWBregisterPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQWBPseudo<InstrItinClass VLDQWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQWBfixedPseudo<InstrItinClass VLDQWBfixedPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQWBfixedPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VLDQWBregisterPseudo<InstrItinClass VLDQWBregisterPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VLDQWBregisterPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VNEGD<bits<2> VNEGD:size = { ?, ? }, string VNEGD:OpcodeStr = ?, string VNEGD:Dt = ?, ValueType VNEGD:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VNEGD:size{1}, VNEGD:size{0}, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = !strconcat(VNEGD:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VNEGD:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (VNEGD:Ty (vnegd DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VNEGQ<bits<2> VNEGQ:size = { ?, ? }, string VNEGQ:OpcodeStr = ?, string VNEGQ:Dt = ?, ValueType VNEGQ:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VNEGQ:size{1}, VNEGQ:size{0}, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = !strconcat(VNEGQ:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VNEGQ:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (VNEGQ:Ty (vnegq QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VREV16D<bits<2> VREV16D:op19_18 = { ?, ? }, string VREV16D:OpcodeStr = ?, string VREV16D:Dt = ?, ValueType VREV16D:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VREV16D:op19_18{1}, VREV16D:op19_18{0}, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = !strconcat(VREV16D:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VREV16D:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (VREV16D:Ty (NEONvrev16 (VREV16D:Ty DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VREV16Q<bits<2> VREV16Q:op19_18 = { ?, ? }, string VREV16Q:OpcodeStr = ?, string VREV16Q:Dt = ?, ValueType VREV16Q:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VREV16Q:op19_18{1}, VREV16Q:op19_18{0}, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = !strconcat(VREV16Q:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VREV16Q:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (VREV16Q:Ty (NEONvrev16 (VREV16Q:Ty QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VREV32D<bits<2> VREV32D:op19_18 = { ?, ? }, string VREV32D:OpcodeStr = ?, string VREV32D:Dt = ?, ValueType VREV32D:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VREV32D:op19_18{1}, VREV32D:op19_18{0}, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = !strconcat(VREV32D:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VREV32D:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (VREV32D:Ty (NEONvrev32 (VREV32D:Ty DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VREV32Q<bits<2> VREV32Q:op19_18 = { ?, ? }, string VREV32Q:OpcodeStr = ?, string VREV32Q:Dt = ?, ValueType VREV32Q:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VREV32Q:op19_18{1}, VREV32Q:op19_18{0}, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = !strconcat(VREV32Q:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VREV32Q:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (VREV32Q:Ty (NEONvrev32 (VREV32Q:Ty QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VREV64D<bits<2> VREV64D:op19_18 = { ?, ? }, string VREV64D:OpcodeStr = ?, string VREV64D:Dt = ?, ValueType VREV64D:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VREV64D:op19_18{1}, VREV64D:op19_18{0}, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = !strconcat(VREV64D:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VREV64D:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set DPR:$Vd, (VREV64D:Ty (NEONvrev64 (VREV64D:Ty DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VREV64Q<bits<2> VREV64Q:op19_18 = { ?, ? }, string VREV64Q:OpcodeStr = ?, string VREV64Q:Dt = ?, ValueType VREV64Q:Ty = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, VREV64Q:op19_18{1}, VREV64Q:op19_18{0}, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = !strconcat(VREV64Q:OpcodeStr, !strconcat("${p}", !strconcat(".", !strconcat(VREV64Q:Dt, "	$Vd, $Vm"))));
  list<dag> Pattern = [(set QPR:$Vd, (VREV64Q:Ty (NEONvrev64 (VREV64Q:Ty QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = N2RegFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
class VST1D<bits<4> VST1D:op7_4 = { ?, ?, ?, ? }, string VST1D:Dt = ?, Operand VST1D:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, VST1D:op7_4{3}, VST1D:op7_4{2}, VST1D:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VST1D:AddrMode:$Rn, VecListOneD:$Vd, pred:$p);
  string AsmString = !strconcat("vst1", !strconcat("${p}", !strconcat(".", !strconcat(VST1D:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VST1D3<bits<4> VST1D3:op7_4 = { ?, ?, ?, ? }, string VST1D3:Dt = ?, Operand VST1D3:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, VST1D3:op7_4{3}, VST1D3:op7_4{2}, VST1D3:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VST1D3:AddrMode:$Rn, VecListThreeD:$Vd, pred:$p);
  string AsmString = !strconcat("vst1", !strconcat("${p}", !strconcat(".", !strconcat(VST1D3:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VST1D4<bits<4> VST1D4:op7_4 = { ?, ?, ?, ? }, string VST1D4:Dt = ?, Operand VST1D4:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, VST1D4:op7_4{3}, VST1D4:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VST1D4:AddrMode:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = !strconcat("vst1", !strconcat("${p}", !strconcat(".", !strconcat(VST1D4:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VST1LN<bits<4> VST1LN:op11_8 = { ?, ?, ?, ? }, bits<4> VST1LN:op7_4 = { ?, ?, ?, ? }, string VST1LN:Dt = ?, ValueType VST1LN:Ty = ?, PatFrag VST1LN:StoreOp = ?, SDNode VST1LN:ExtractOp = ?, Operand VST1LN:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST1LN:op11_8{3}, VST1LN:op11_8{2}, VST1LN:op11_8{1}, VST1LN:op11_8{0}, VST1LN:op7_4{3}, VST1LN:op7_4{2}, VST1LN:op7_4{1}, VST1LN:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VST1LN:AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vst1", !strconcat("${p}", !strconcat(".", !strconcat(VST1LN:Dt, "	\{$Vd[$lane]\}, $Rn"))));
  list<dag> Pattern = [(VST1LN:StoreOp (VST1LN:ExtractOp (VST1LN:Ty DPR:$Vd), imm:$lane), VST1LN:AddrMode:$Rn)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VST1LNWB<bits<4> VST1LNWB:op11_8 = { ?, ?, ?, ? }, bits<4> VST1LNWB:op7_4 = { ?, ?, ?, ? }, string VST1LNWB:Dt = ?, ValueType VST1LNWB:Ty = ?, PatFrag VST1LNWB:StoreOp = ?, SDNode VST1LNWB:ExtractOp = ?, Operand VST1LNWB:AdrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST1LNWB:op11_8{3}, VST1LNWB:op11_8{2}, VST1LNWB:op11_8{1}, VST1LNWB:op11_8{0}, VST1LNWB:op7_4{3}, VST1LNWB:op7_4{2}, VST1LNWB:op7_4{1}, VST1LNWB:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins VST1LNWB:AdrMode:$Rn, am6offset:$Rm, DPR:$Vd, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vst1", !strconcat("${p}", !strconcat(".", !strconcat(VST1LNWB:Dt, "	\{$Vd[$lane]\}, $Rn$Rm"))));
  list<dag> Pattern = [(set GPR:$wb, (VST1LNWB:StoreOp (VST1LNWB:ExtractOp (VST1LNWB:Ty DPR:$Vd), imm:$lane), VST1LNWB:AdrMode:$Rn, am6offset:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VST1Q<bits<4> VST1Q:op7_4 = { ?, ?, ?, ? }, string VST1Q:Dt = ?, Operand VST1Q:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, VST1Q:op7_4{3}, VST1Q:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VST1Q:AddrMode:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = !strconcat("vst1", !strconcat("${p}", !strconcat(".", !strconcat(VST1Q:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x2;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VST1QLNPseudo<ValueType VST1QLNPseudo:Ty = ?, PatFrag VST1QLNPseudo:StoreOp = ?, SDNode VST1QLNPseudo:ExtractOp = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(VST1QLNPseudo:StoreOp (VST1QLNPseudo:ExtractOp (VST1QLNPseudo:Ty QPR:$src), imm:$lane), addrmode6:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VST1QLNWBPseudo<ValueType VST1QLNWBPseudo:Ty = ?, PatFrag VST1QLNWBPseudo:StoreOp = ?, SDNode VST1QLNWBPseudo:ExtractOp = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$wb, (VST1QLNWBPseudo:StoreOp (VST1QLNWBPseudo:ExtractOp (VST1QLNWBPseudo:Ty QPR:$src), imm:$lane), addrmode6:$addr, am6offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VST2<bits<4> VST2:op11_8 = { ?, ?, ?, ? }, bits<4> VST2:op7_4 = { ?, ?, ?, ? }, string VST2:Dt = ?, RegisterOperand VST2:VdTy = ?, InstrItinClass VST2:itin = ?, Operand VST2:AddrMode = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST2:op11_8{3}, VST2:op11_8{2}, VST2:op11_8{1}, VST2:op11_8{0}, VST2:op7_4{3}, VST2:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VST2:AddrMode:$Rn, VST2:VdTy:$Vd, pred:$p);
  string AsmString = !strconcat("vst2", !strconcat("${p}", !strconcat(".", !strconcat(VST2:Dt, "	$Vd, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VST2:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VST2LN<bits<4> VST2LN:op11_8 = { ?, ?, ?, ? }, bits<4> VST2LN:op7_4 = { ?, ?, ?, ? }, string VST2LN:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST2LN:op11_8{3}, VST2LN:op11_8{2}, VST2LN:op11_8{1}, VST2LN:op11_8{0}, VST2LN:op7_4{3}, VST2LN:op7_4{2}, VST2LN:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vst2", !strconcat("${p}", !strconcat(".", !strconcat(VST2LN:Dt, "	\{$Vd[$lane], $src2[$lane]\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VST2LNWB<bits<4> VST2LNWB:op11_8 = { ?, ?, ?, ? }, bits<4> VST2LNWB:op7_4 = { ?, ?, ?, ? }, string VST2LNWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST2LNWB:op11_8{3}, VST2LNWB:op11_8{2}, VST2LNWB:op11_8{1}, VST2LNWB:op11_8{0}, VST2LNWB:op7_4{3}, VST2LNWB:op7_4{2}, VST2LNWB:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vst2", !strconcat("${p}", !strconcat(".", !strconcat(VST2LNWB:Dt, "	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VST3D<bits<4> VST3D:op11_8 = { ?, ?, ?, ? }, bits<4> VST3D:op7_4 = { ?, ?, ?, ? }, string VST3D:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST3D:op11_8{3}, VST3D:op11_8{2}, VST3D:op11_8{1}, VST3D:op11_8{0}, VST3D:op7_4{3}, VST3D:op7_4{2}, VST3D:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = !strconcat("vst3", !strconcat("${p}", !strconcat(".", !strconcat(VST3D:Dt, "	\{$Vd, $src2, $src3\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VST3DWB<bits<4> VST3DWB:op11_8 = { ?, ?, ?, ? }, bits<4> VST3DWB:op7_4 = { ?, ?, ?, ? }, string VST3DWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST3DWB:op11_8{3}, VST3DWB:op11_8{2}, VST3DWB:op11_8{1}, VST3DWB:op11_8{0}, VST3DWB:op7_4{3}, VST3DWB:op7_4{2}, VST3DWB:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = !strconcat("vst3", !strconcat("${p}", !strconcat(".", !strconcat(VST3DWB:Dt, "	\{$Vd, $src2, $src3\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class VST3LN<bits<4> VST3LN:op11_8 = { ?, ?, ?, ? }, bits<4> VST3LN:op7_4 = { ?, ?, ?, ? }, string VST3LN:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST3LN:op11_8{3}, VST3LN:op11_8{2}, VST3LN:op11_8{1}, VST3LN:op11_8{0}, VST3LN:op7_4{3}, VST3LN:op7_4{2}, VST3LN:op7_4{1}, VST3LN:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vst3", !strconcat("${p}", !strconcat(".", !strconcat(VST3LN:Dt, "	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VST3LNWB<bits<4> VST3LNWB:op11_8 = { ?, ?, ?, ? }, bits<4> VST3LNWB:op7_4 = { ?, ?, ?, ? }, string VST3LNWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST3LNWB:op11_8{3}, VST3LNWB:op11_8{2}, VST3LNWB:op11_8{1}, VST3LNWB:op11_8{0}, VST3LNWB:op7_4{3}, VST3LNWB:op7_4{2}, VST3LNWB:op7_4{1}, VST3LNWB:op7_4{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vst3", !strconcat("${p}", !strconcat(".", !strconcat(VST3LNWB:Dt, "	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VST4D<bits<4> VST4D:op11_8 = { ?, ?, ?, ? }, bits<4> VST4D:op7_4 = { ?, ?, ?, ? }, string VST4D:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST4D:op11_8{3}, VST4D:op11_8{2}, VST4D:op11_8{1}, VST4D:op11_8{0}, VST4D:op7_4{3}, VST4D:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = !strconcat("vst4", !strconcat("${p}", !strconcat(".", !strconcat(VST4D:Dt, "	\{$Vd, $src2, $src3, $src4\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
class VST4DWB<bits<4> VST4DWB:op11_8 = { ?, ?, ?, ? }, bits<4> VST4DWB:op7_4 = { ?, ?, ?, ? }, string VST4DWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST4DWB:op11_8{3}, VST4DWB:op11_8{2}, VST4DWB:op11_8{1}, VST4DWB:op11_8{0}, VST4DWB:op7_4{3}, VST4DWB:op7_4{2}, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = !strconcat("vst4", !strconcat("${p}", !strconcat(".", !strconcat(VST4DWB:Dt, "	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
class VST4LN<bits<4> VST4LN:op11_8 = { ?, ?, ?, ? }, bits<4> VST4LN:op7_4 = { ?, ?, ?, ? }, string VST4LN:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST4LN:op11_8{3}, VST4LN:op11_8{2}, VST4LN:op11_8{1}, VST4LN:op11_8{0}, VST4LN:op7_4{3}, VST4LN:op7_4{2}, VST4LN:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vst4", !strconcat("${p}", !strconcat(".", !strconcat(VST4LN:Dt, "	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VST4LNWB<bits<4> VST4LNWB:op11_8 = { ?, ?, ?, ? }, bits<4> VST4LNWB:op7_4 = { ?, ?, ?, ? }, string VST4LNWB:Dt = ?> {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, VST4LNWB:op11_8{3}, VST4LNWB:op11_8{2}, VST4LNWB:op11_8{1}, VST4LNWB:op11_8{0}, VST4LNWB:op7_4{3}, VST4LNWB:op7_4{2}, VST4LNWB:op7_4{1}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = !strconcat("vst4", !strconcat("${p}", !strconcat(".", !strconcat(VST4LNWB:Dt, "	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm"))));
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = NLdStFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
class VSTQLNPseudo<InstrItinClass VSTQLNPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQLNPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQLNWBPseudo<InstrItinClass VSTQLNWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQLNWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQPseudo<InstrItinClass VSTQPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQLNPseudo<InstrItinClass VSTQQLNPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQLNPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQLNWBPseudo<InstrItinClass VSTQQLNWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQLNWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQPseudo<InstrItinClass VSTQQPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQQQLNPseudo<InstrItinClass VSTQQQQLNPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQQQLNPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQQQLNWBPseudo<InstrItinClass VSTQQQQLNWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQQQLNWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQQQPseudo<InstrItinClass VSTQQQQPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQQQPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQQQWBPseudo<InstrItinClass VSTQQQQWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQQQWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQWBPseudo<InstrItinClass VSTQQWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQWBfixedPseudo<InstrItinClass VSTQQWBfixedPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQWBfixedPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQQWBregisterPseudo<InstrItinClass VSTQQWBregisterPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQQWBregisterPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQWBPseudo<InstrItinClass VSTQWBPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQWBPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQWBfixedPseudo<InstrItinClass VSTQWBfixedPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQWBfixedPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class VSTQWBregisterPseudo<InstrItinClass VSTQWBregisterPseudo:itin = ?> {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, QPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = VSTQWBregisterPseudo:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class ValueType<int ValueType:size = ?, int ValueType:value = ?> {
  string Namespace = "MVT";
  int Size = ValueType:size;
  int Value = ValueType:value;
  string NAME = ?;
}
class ValueTypeByHwMode<list<HwMode> ValueTypeByHwMode:Ms = ?, list<ValueType> ValueTypeByHwMode:Ts = ?> {	// HwModeSelect ValueType
  list<HwMode> Modes = ValueTypeByHwMode:Ms;
  string Namespace = "MVT";
  int Size = 0;
  int Value = 0;
  list<ValueType> Objects = ValueTypeByHwMode:Ts;
  string NAME = ?;
}
class WriteOnly<int WriteOnly:argNo = ?> {	// IntrinsicProperty
  int ArgNo = WriteOnly:argNo;
  string NAME = ?;
}
class WriteRes<SchedWrite WriteRes:write = ?, list<ProcResourceKind> WriteRes:resources = ?> {	// ProcWriteResources
  list<ProcResourceKind> ProcResources = WriteRes:resources;
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = ?;
  SchedWrite WriteType = WriteRes:write;
  string NAME = ?;
}
class WriteSequence<list<SchedWrite> WriteSequence:writes = ?, int WriteSequence:rep = 1> {	// SchedReadWrite SchedWrite
  list<SchedWrite> Writes = WriteSequence:writes;
  int Repeat = WriteSequence:rep;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
class XI<dag XI:oops = ?, dag XI:iops = ?, AddrMode XI:am = ?, int XI:sz = ?, IndexMode XI:im = ?, Format XI:f = ?, InstrItinClass XI:itin = ?, string XI:asm = ?, string XI:cstr = ?, list<dag> XI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = XI:oops;
  dag InOperandList = XI:iops;
  string AsmString = XI:asm;
  list<dag> Pattern = XI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = XI:sz;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(XI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = XI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = XI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = XI:am;
  IndexMode IM = XI:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = XI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class Xform16Bit {
  bit canXformTo16Bit = 1;
  string NAME = ?;
}
class acquiring_load<PatFrag acquiring_load:base = ?> {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (acquiring_load:base node:$ptr);
  code PredicateCode = [{
  AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
  return isAcquireOrStronger(Ordering);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
class arglistconcat<list<list<AMDGPUArg>> arglistconcat:arglists = ?, int arglistconcat:shift = 0> {
  list<AMDGPUArg> ret = !foldl([], arglistconcat:arglists, lhs, rhs, !listconcat(lhs, arglistmatchshift<rhs, !add(arglistconcat:shift, !foldl(0, lhs, a, b, !add(a, b.Type.isAny)))>.ret));
  string NAME = ?;
}
class arglistmatchshift<list<AMDGPUArg> arglistmatchshift:arglist = ?, int arglistmatchshift:shift = ?> {
  list<AMDGPUArg> ret = !foreach(arg, arglistmatchshift:arglist, !if(!isa<LLVMMatchType>(arg.Type), AMDGPUArg<LLVMMatchType<!add(!cast<LLVMMatchType>(arg.Type).Number, arglistmatchshift:shift)>, arg.Name>, arg));
  string NAME = ?;
}
class makeArgList<list<string> makeArgList:names = ?, LLVMType makeArgList:basety = ?> {
  list<AMDGPUArg> ret = !listconcat([AMDGPUArg<makeArgList:basety, makeArgList:names[0]>], !foreach(name, !tail(makeArgList:names), AMDGPUArg<anonymous_6, name>));
  string NAME = ?;
}
class nImmVINVIAsmOperandReplicate<ValueType nImmVINVIAsmOperandReplicate:From = ?, ValueType nImmVINVIAsmOperandReplicate:To = ?> {	// AsmOperandClass
  string Name = !strconcat("NEONi", !strconcat(!cast<string>(nImmVINVIAsmOperandReplicate:To.Size), !strconcat("invi", !strconcat(!cast<string>(nImmVINVIAsmOperandReplicate:From.Size), "Replicate"))));
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = !strconcat("isNEONinvReplicate<", !strconcat(!cast<string>(nImmVINVIAsmOperandReplicate:From.Size), !strconcat(", ", !strconcat(!cast<string>(nImmVINVIAsmOperandReplicate:To.Size), ">"))));
  string RenderMethod = !strconcat("addNEONinvi", !strconcat(!cast<string>(nImmVINVIAsmOperandReplicate:From.Size), "ReplicateOperands"));
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
class nImmVINVIReplicate<ValueType nImmVINVIReplicate:From = ?, ValueType nImmVINVIReplicate:To = ?> {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmVINVIAsmOperandReplicate<nImmVINVIReplicate:From, nImmVINVIReplicate:To>;
  string NAME = ?;
}
class nImmVMOVIAsmOperandReplicate<ValueType nImmVMOVIAsmOperandReplicate:From = ?, ValueType nImmVMOVIAsmOperandReplicate:To = ?> {	// AsmOperandClass
  string Name = !strconcat("NEONi", !strconcat(!cast<string>(nImmVMOVIAsmOperandReplicate:To.Size), !strconcat("vmovi", !strconcat(!cast<string>(nImmVMOVIAsmOperandReplicate:From.Size), "Replicate"))));
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = !strconcat("isNEONmovReplicate<", !strconcat(!cast<string>(nImmVMOVIAsmOperandReplicate:From.Size), !strconcat(", ", !strconcat(!cast<string>(nImmVMOVIAsmOperandReplicate:To.Size), ">"))));
  string RenderMethod = !strconcat("addNEONvmovi", !strconcat(!cast<string>(nImmVMOVIAsmOperandReplicate:From.Size), "ReplicateOperands"));
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
class nImmVMOVIReplicate<ValueType nImmVMOVIReplicate:From = ?, ValueType nImmVMOVIReplicate:To = ?> {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmVMOVIAsmOperandReplicate<nImmVMOVIReplicate:From, nImmVMOVIReplicate:To>;
  string NAME = ?;
}
class releasing_store<PatFrag releasing_store:base = ?> {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (releasing_store:base node:$ptr, node:$val);
  code PredicateCode = [{
  AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
  return isReleaseOrStronger(Ordering);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
class sI<dag sI:oops = ?, dag sI:iops = ?, AddrMode sI:am = ?, int sI:sz = ?, IndexMode sI:im = ?, Format sI:f = ?, InstrItinClass sI:itin = ?, string sI:opc = ?, string sI:asm = ?, string sI:cstr = ?, list<dag> sI:pattern = ?> {	// Instruction InstTemplate Encoding InstARM
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, ?, ?, ?, ?, ?, ?, ?, s{0}, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = sI:oops;
  dag InOperandList = !con(sI:iops, (ins pred:$p, cc_out:$s));
  string AsmString = !strconcat(sI:opc, !strconcat("${s}${p}", sI:asm));
  list<dag> Pattern = sI:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = sI:sz;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = !eq(!cast<string>(sI:f), "Pseudo");
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = sI:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = sI:cstr;
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = sI:am;
  IndexMode IM = sI:im;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = sI:f;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  string NAME = ?;
}
class t2AsmPseudo<string t2AsmPseudo:asm = ?, dag t2AsmPseudo:iops = ?, dag t2AsmPseudo:oops = (outs)> {	// Instruction InstTemplate AsmPseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = t2AsmPseudo:oops;
  dag InOperandList = t2AsmPseudo:iops;
  string AsmString = t2AsmPseudo:asm;
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class t2CPS<dag t2CPS:iops = ?, string t2CPS:asm_op = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, imod{1}, imod{0}, M, iflags{2}, iflags{1}, iflags{0}, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = t2CPS:iops;
  string AsmString = !strconcat("cps", t2CPS:asm_op);
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2CPSInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<2> imod = { ?, ? };
  bits<3> iflags = { ?, ?, ? };
  bits<5> mode = { ?, ?, ?, ?, ? };
  bit M = ?;
  string NAME = ?;
}
class t2InstAlias<string t2InstAlias:Asm = ?, dag t2InstAlias:Result = ?, bit t2InstAlias:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = t2InstAlias:Asm;
  dag ResultInst = t2InstAlias:Result;
  int EmitPriority = !cast<int>(t2InstAlias:EmitPriority);
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class t2InstSubst<string t2InstSubst:Asm = ?, dag t2InstSubst:Result = ?, bit t2InstSubst:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = t2InstSubst:Asm;
  dag ResultInst = t2InstSubst:Result;
  int EmitPriority = !cast<int>(t2InstSubst:EmitPriority);
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class t2MovRCopro<bits<4> t2MovRCopro:Op = { ?, ?, ?, ? }, string t2MovRCopro:opc = ?, bit t2MovRCopro:direction = ?, dag t2MovRCopro:oops = ?, dag t2MovRCopro:iops = ?, list<dag> t2MovRCopro:pattern = ?> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop
  field bits<32> Inst = { t2MovRCopro:Op{3}, t2MovRCopro:Op{2}, t2MovRCopro:Op{1}, t2MovRCopro:Op{0}, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, t2MovRCopro:direction, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = t2MovRCopro:oops;
  dag InOperandList = !con(t2MovRCopro:iops, (ins pred:$p));
  string AsmString = !strconcat(t2MovRCopro:opc, "${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2");
  list<dag> Pattern = t2MovRCopro:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string NAME = ?;
}
class t2MovRRCopro<bits<4> t2MovRRCopro:Op = { ?, ?, ?, ? }, string t2MovRRCopro:opc = ?, bit t2MovRRCopro:direction = ?, dag t2MovRRCopro:oops = ?, dag t2MovRRCopro:iops = ?, list<dag> t2MovRRCopro:pattern = []> {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop
  field bits<32> Inst = { t2MovRRCopro:Op{3}, t2MovRRCopro:Op{2}, t2MovRRCopro:Op{1}, t2MovRRCopro:Op{0}, 1, 1, 0, 0, 0, 1, 0, t2MovRRCopro:direction, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { Unpredictable{31}, Unpredictable{30}, Unpredictable{29}, Unpredictable{28}, Unpredictable{27}, Unpredictable{26}, Unpredictable{25}, Unpredictable{24}, Unpredictable{23}, Unpredictable{22}, Unpredictable{21}, Unpredictable{20}, Unpredictable{19}, Unpredictable{18}, Unpredictable{17}, Unpredictable{16}, Unpredictable{15}, Unpredictable{14}, Unpredictable{13}, Unpredictable{12}, Unpredictable{11}, Unpredictable{10}, Unpredictable{9}, Unpredictable{8}, Unpredictable{7}, Unpredictable{6}, Unpredictable{5}, Unpredictable{4}, Unpredictable{3}, Unpredictable{2}, Unpredictable{1}, Unpredictable{0} };
  string Namespace = "ARM";
  dag OutOperandList = t2MovRRCopro:oops;
  dag InOperandList = !con(t2MovRRCopro:iops, (ins pred:$p));
  string AsmString = !strconcat(t2MovRRCopro:opc, "${p}	$cop, $opc1, $Rt, $Rt2, $CRm");
  list<dag> Pattern = t2MovRRCopro:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = ThumbFrm;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
class t2PseudoExpand<dag t2PseudoExpand:oops = ?, dag t2PseudoExpand:iops = ?, int t2PseudoExpand:sz = ?, InstrItinClass t2PseudoExpand:itin = ?, list<dag> t2PseudoExpand:pattern = ?, dag t2PseudoExpand:Result = ?> {	// Instruction InstTemplate PseudoInst t2PseudoInst PseudoInstExpansion
  string Namespace = "ARM";
  dag OutOperandList = t2PseudoExpand:oops;
  dag InOperandList = t2PseudoExpand:iops;
  string AsmString = "";
  list<dag> Pattern = t2PseudoExpand:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = t2PseudoExpand:sz;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = t2PseudoExpand:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = t2PseudoExpand:Result;
  string NAME = ?;
}
class t2PseudoInst<dag t2PseudoInst:oops = ?, dag t2PseudoInst:iops = ?, int t2PseudoInst:sz = ?, InstrItinClass t2PseudoInst:itin = ?, list<dag> t2PseudoInst:pattern = ?> {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = t2PseudoInst:oops;
  dag InOperandList = t2PseudoInst:iops;
  string AsmString = "";
  list<dag> Pattern = t2PseudoInst:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = t2PseudoInst:sz;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = t2PseudoInst:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class t2basePseudoInst<dag t2basePseudoInst:oops = ?, dag t2basePseudoInst:iops = ?, int t2basePseudoInst:sz = ?, InstrItinClass t2basePseudoInst:itin = ?, list<dag> t2basePseudoInst:pattern = ?> {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = t2basePseudoInst:oops;
  dag InOperandList = t2basePseudoInst:iops;
  string AsmString = "";
  list<dag> Pattern = t2basePseudoInst:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = t2basePseudoInst:sz;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = t2basePseudoInst:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class tAsmPseudo<string tAsmPseudo:asm = ?, dag tAsmPseudo:iops = ?, dag tAsmPseudo:oops = (outs)> {	// Instruction InstTemplate AsmPseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = tAsmPseudo:oops;
  dag InOperandList = tAsmPseudo:iops;
  string AsmString = tAsmPseudo:asm;
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class tHintAlias<string tHintAlias:Asm = ?, dag tHintAlias:Result = ?, bit tHintAlias:EmitPriority = 0> {	// InstAlias Requires tInstAlias
  string AsmString = tHintAlias:Asm;
  dag ResultInst = tHintAlias:Result;
  int EmitPriority = !cast<int>(tHintAlias:EmitPriority);
  list<Predicate> Predicates = [IsThumb, HasV6M];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class tInstAlias<string tInstAlias:Asm = ?, dag tInstAlias:Result = ?, bit tInstAlias:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = tInstAlias:Asm;
  dag ResultInst = tInstAlias:Result;
  int EmitPriority = !cast<int>(tInstAlias:EmitPriority);
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class tInstSubst<string tInstSubst:Asm = ?, dag tInstSubst:Result = ?, bit tInstSubst:EmitPriority = 0> {	// InstAlias Requires
  string AsmString = tInstSubst:Asm;
  dag ResultInst = tInstSubst:Result;
  int EmitPriority = !cast<int>(tInstSubst:EmitPriority);
  list<Predicate> Predicates = [IsThumb, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
class tPseudoExpand<dag tPseudoExpand:oops = ?, dag tPseudoExpand:iops = ?, int tPseudoExpand:sz = ?, InstrItinClass tPseudoExpand:itin = ?, list<dag> tPseudoExpand:pattern = ?, dag tPseudoExpand:Result = ?> {	// Instruction InstTemplate PseudoInst tPseudoInst PseudoInstExpansion
  string Namespace = "ARM";
  dag OutOperandList = tPseudoExpand:oops;
  dag InOperandList = tPseudoExpand:iops;
  string AsmString = "";
  list<dag> Pattern = tPseudoExpand:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = tPseudoExpand:sz;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = tPseudoExpand:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = tPseudoExpand:Result;
  string NAME = ?;
}
class tPseudoInst<dag tPseudoInst:oops = ?, dag tPseudoInst:iops = ?, int tPseudoInst:sz = ?, InstrItinClass tPseudoInst:itin = ?, list<dag> tPseudoInst:pattern = ?> {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = tPseudoInst:oops;
  dag InOperandList = tPseudoInst:iops;
  string AsmString = "";
  list<dag> Pattern = tPseudoInst:pattern;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = tPseudoInst:sz;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = tPseudoInst:itin;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, thumbArithFlagSetting, D.Value{2}, D.Value{1}, D.Value{0}, canXformTo16Bit, isUnaryDataProc, Form{5}, Form{4}, Form{3}, Form{2}, Form{1}, Form{0}, IndexModeBits{1}, IndexModeBits{0}, AM.Value{4}, AM.Value{3}, AM.Value{2}, AM.Value{1}, AM.Value{0} };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { IM.Value{1}, IM.Value{0} };
  Format F = Pseudo;
  bits<6> Form = { F.Value{5}, F.Value{4}, F.Value{3}, F.Value{2}, F.Value{1}, F.Value{0} };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
class unknown_class {
  string NAME = ?;
}
------------- Defs -----------------
def A57LDMOpsListNoregin {	// A57WriteLMOpsListType
  list<SchedWriteRes> Writes = [A57Write_3cyc_1L, A57Write_3cyc_1L, A57Write_4cyc_1L, A57Write_4cyc_1L, A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_10cyc_1L];
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57LDMOpsListRegin {	// A57WriteLMOpsListType
  list<SchedWriteRes> Writes = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_11cyc_1L_1I];
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57LDMOpsList_Upd {	// A57WriteLMOpsListType
  list<SchedWriteRes> Writes = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I];
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57LMAddrPred1 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA57Model;
  code Predicate = [{(TII->getLDMVariableDefsSize(*MI)+1)/2 == 1}];
  string NAME = ?;
}
def A57LMAddrPred2 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA57Model;
  code Predicate = [{(TII->getLDMVariableDefsSize(*MI)+1)/2 == 2}];
  string NAME = ?;
}
def A57LMAddrPred3 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA57Model;
  code Predicate = [{(TII->getLDMVariableDefsSize(*MI)+1)/2 == 3}];
  string NAME = ?;
}
def A57LMAddrPred4 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA57Model;
  code Predicate = [{(TII->getLDMVariableDefsSize(*MI)+1)/2 == 4}];
  string NAME = ?;
}
def A57LMAddrPred5 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA57Model;
  code Predicate = [{(TII->getLDMVariableDefsSize(*MI)+1)/2 == 5}];
  string NAME = ?;
}
def A57LMAddrPred6 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA57Model;
  code Predicate = [{(TII->getLDMVariableDefsSize(*MI)+1)/2 == 6}];
  string NAME = ?;
}
def A57LMAddrPred7 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA57Model;
  code Predicate = [{(TII->getLDMVariableDefsSize(*MI)+1)/2 == 7}];
  string NAME = ?;
}
def A57LMAddrPred8 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA57Model;
  code Predicate = [{(TII->getLDMVariableDefsSize(*MI)+1)/2 == 8}];
  string NAME = ?;
}
def A57ReadALUsr {	// SchedReadWrite SchedRead SchedVariant SchedReadVariant
  list<SchedVar> Variants = [anonymous_2433, anonymous_2434];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadMLA {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 2;
  list<SchedWrite> ValidWrites = [A57WriteMLA, A57WriteMLAL];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVABAD {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [A57WriteVABAD];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVABAL {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [A57WriteVABAL];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVABAQ {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [A57WriteVABAQ];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVFMA5 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 5;
  list<SchedWrite> ValidWrites = [A57WriteVFMA, A57WriteVMUL];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVMLAD_VecInt {	// SchedReadWrite SchedRead SchedVariant SchedReadVariant
  list<SchedVar> Variants = [anonymous_2720, anonymous_2722];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVMLAL_VecInt {	// SchedReadWrite SchedRead SchedVariant SchedReadVariant
  list<SchedVar> Variants = [anonymous_2730, anonymous_2732];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVMLAQ_VecInt {	// SchedReadWrite SchedRead SchedVariant SchedReadVariant
  list<SchedVar> Variants = [anonymous_2725, anonymous_2727];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVMLA_VecFP {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 5;
  list<SchedWrite> ValidWrites = [A57WriteVMLA_VecFP, A57WriteVMUL_VecFP];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVPADAL {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [A57WriteVPADAL];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVQDMLAL_VecInt {	// SchedReadWrite SchedRead SchedVariant SchedReadVariant
  list<SchedVar> Variants = [anonymous_2735, anonymous_2737];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57ReadVSRA {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [A57WriteVSRA];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57UnitB {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def A57UnitI {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 2;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def A57UnitL {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def A57UnitM {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def A57UnitS {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def A57UnitV {	// ProcResourceKind ProcResGroup
  list<ProcResource> Resources = [A57UnitX, A57UnitW];
  SchedMachineModel SchedModel = CortexA57Model;
  int BufferSize = -1;
  string NAME = ?;
}
def A57UnitW {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def A57UnitX {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def A57VLDMOpsListCond {	// A57WriteLMOpsListType
  list<SchedWriteRes> Writes = [A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L, A57Write_13cyc_1L, A57Write_14cyc_1L, A57Write_15cyc_1L, A57Write_16cyc_1L, A57Write_17cyc_1L, A57Write_18cyc_1L, A57Write_19cyc_1L, A57Write_20cyc_1L];
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57VLDMOpsListCond_Upd {	// A57WriteLMOpsListType
  list<SchedWriteRes> Writes = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I, A57Write_13cyc_1L_1I, A57Write_14cyc_1L_1I, A57Write_15cyc_1L_1I, A57Write_16cyc_1L_1I, A57Write_17cyc_1L_1I, A57Write_18cyc_1L_1I, A57Write_19cyc_1L_1I, A57Write_20cyc_1L_1I];
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57VLDMOpsListUncond {	// A57WriteLMOpsListType
  list<SchedWriteRes> Writes = [A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L, A57Write_12cyc_1L];
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57VLDMOpsListUncond_Upd {	// A57WriteLMOpsListType
  list<SchedWriteRes> Writes = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I, A57Write_12cyc_1L_1I];
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WrBackOne {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WrBackThree {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WrBackTwo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteALUSsr {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2432, anonymous_2431];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteALUsi {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2430, anonymous_2431];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteALUsr {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2432, anonymous_2431];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteCMPsr {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2432, anonymous_2431];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteI2ld {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A57Write_1cyc_1I, A57Write_1cyc_1I, A57Write_4cyc_1L];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteI2pc {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A57Write_1cyc_1I, A57Write_1cyc_1I, A57Write_1cyc_1I];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLDM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2552, anonymous_2553];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLDM_Upd {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2543, anonymous_2544, anonymous_2545, anonymous_2546, anonymous_2547, anonymous_2548, anonymous_2549, anonymous_2550, anonymous_2551];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLDMnoreginlist {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2525, anonymous_2526, anonymous_2527, anonymous_2528, anonymous_2529, anonymous_2530, anonymous_2531, anonymous_2532, anonymous_2533];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLDMreginlist {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2534, anonymous_2535, anonymous_2536, anonymous_2537, anonymous_2538, anonymous_2539, anonymous_2540, anonymous_2541, anonymous_2542];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrAm3 {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2488, anonymous_2489];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrAm3PostWrBack {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2510, anonymous_2502];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrAm3PostWrBackX3 {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2506, anonymous_2502];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrAm3PreWrBack {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2501, anonymous_2502];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrAm3X2 {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2491, anonymous_2489];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrAmLDSTSO {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2494, anonymous_2495, anonymous_2489];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrAmLDSTSOPre {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2498, anonymous_2499];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrDAm3Pre {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2505, anonymous_2499];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrDAm3PreWrBack {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2506, anonymous_2502];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrTRegPost {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2514, anonymous_2499];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteLdrTRegPostWrBack {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2515, anonymous_2516];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteMLA {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteMLAL {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteMOVT {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2448, anonymous_2431];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteMOVsi {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2443, anonymous_2444];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteMOVsr {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2446, anonymous_2443, anonymous_2432, anonymous_2444];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WritePLD {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2522, anonymous_2523, anonymous_2489];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteParArith {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2466, anonymous_2467];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteParArithExch {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2469, anonymous_2470];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteSEL {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2432, anonymous_2444];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteSTM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2582, anonymous_2583, anonymous_2584, anonymous_2585, anonymous_2586, anonymous_2587, anonymous_2588, anonymous_2589, anonymous_2590];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteSTM_Upd {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2591, anonymous_2592, anonymous_2593, anonymous_2594, anonymous_2595, anonymous_2596, anonymous_2597, anonymous_2598, anonymous_2599];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteStrAm3 {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2562, anonymous_2560];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteStrAm3PreWrBackX2 {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2574, anonymous_2502];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteStrAm3PreWrBackX3 {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2577, anonymous_2502];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteStrAm3PreX2 {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2564, anonymous_2570];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteStrAm3PreX3 {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2576, anonymous_2570];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteStrAm3X2 {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2564, anonymous_2560];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteStrAmLDSTSO {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2558, anonymous_2559, anonymous_2560];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteStrAmLDSTSOPre {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2567, anonymous_2568, anonymous_2569, anonymous_2570];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteStrAmLDSTSOPreWrBack {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2571, anonymous_2572, anonymous_2502];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVABAD {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVABAL {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVABAQ {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVFMA {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVLDM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2656, anonymous_2657];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVLDM_UPD {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2677, anonymous_2678];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVLDMcond {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2647, anonymous_2648, anonymous_2649, anonymous_2650, anonymous_2651, anonymous_2652, anonymous_2653, anonymous_2654, anonymous_2655];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVLDMcond_UPD {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2668, anonymous_2669, anonymous_2670, anonymous_2671, anonymous_2672, anonymous_2673, anonymous_2674, anonymous_2675, anonymous_2676];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVLDMuncond {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2638, anonymous_2639, anonymous_2640, anonymous_2641, anonymous_2642, anonymous_2643, anonymous_2644, anonymous_2645, anonymous_2646];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVLDMuncond_UPD {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2659, anonymous_2660, anonymous_2661, anonymous_2662, anonymous_2663, anonymous_2664, anonymous_2665, anonymous_2666, anonymous_2667];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVMLAD_VecInt {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2713, anonymous_2714];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVMLAL_VecInt {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2713, anonymous_2714];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVMLAQ_VecInt {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2716, anonymous_2717];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVMLA_VecFP {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVMUL {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVMULD_VecInt {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2713, anonymous_2714];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVMULL_VecInt {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2713, anonymous_2714];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVMULQ_VecInt {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2716, anonymous_2717];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVMUL_VecFP {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVPADAL {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVQDMLAL_VecInt {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2713, anonymous_2714];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVSRA {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVSTMd {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2682, anonymous_2683, anonymous_2684, anonymous_2685, anonymous_2686, anonymous_2687, anonymous_2688, anonymous_2689, anonymous_2690];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVSTMd_Upd {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2691, anonymous_2692, anonymous_2693, anonymous_2694, anonymous_2695, anonymous_2696, anonymous_2697, anonymous_2698, anonymous_2599];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVSTMs {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2582, anonymous_2583, anonymous_2584, anonymous_2585, anonymous_2586, anonymous_2587, anonymous_2588, anonymous_2589, anonymous_2590];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVSTMs_Upd {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2591, anonymous_2592, anonymous_2593, anonymous_2594, anonymous_2595, anonymous_2596, anonymous_2597, anonymous_2598, anonymous_2599];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57WriteVcmp {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2606, anonymous_2607];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_10cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_10cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_10cyc_1L_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_10cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_10cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_10cyc_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_10cyc_2V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_10cyc_3V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV, A57UnitV, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_11cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_11cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_11cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_11cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_12cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_12cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_12cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_12cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_13cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 13;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_13cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 13;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_13cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 13;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_13cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 13;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_14cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 14;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_14cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 14;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_14cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 14;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_14cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 14;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_15cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_15cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_15cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_15cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_16cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 16;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_16cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 16;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_16cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 16;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_16cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 16;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_17cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 17;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_17cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 17;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_17cyc_1W {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitW];
  list<int> ResourceCycles = [17];
  int Latency = 17;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_18cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 18;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_18cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 18;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_18cyc_1X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [18];
  int Latency = 18;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_19cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 19;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_19cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 19;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_19cyc_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitM];
  list<int> ResourceCycles = [19];
  int Latency = 19;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_1cyc_1B {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitB];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_1cyc_1B_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitB, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_1cyc_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_1cyc_1I_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_1cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_1cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_1cyc_1S_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_20cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 20;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_20cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 20;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_20cyc_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitM];
  list<int> ResourceCycles = [20];
  int Latency = 20;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_2cyc_1B_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitB, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_2cyc_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_2cyc_1I_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_2cyc_1I_2S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitS, A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_2cyc_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_2cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_2cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_2cyc_2S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_2cyc_2V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_32cyc_1W {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitW];
  list<int> ResourceCycles = [32];
  int Latency = 32;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_32cyc_1X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [32];
  int Latency = 32;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_35cyc_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitM];
  list<int> ResourceCycles = [35];
  int Latency = 35;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_36cyc_2X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX, A57UnitX];
  list<int> ResourceCycles = [18, 18];
  int Latency = 36;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1B_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitB, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1I_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1I_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1I_1S_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitS, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1S_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1S_1V_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitV, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1W {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitW];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_1X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_3cyc_2V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1I_1L_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitL, A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1I_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1S_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1S_1V_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitV, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1W {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitW];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_1X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_4cyc_2X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX, A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1I_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1I_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1W {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitW];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_1X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_2V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_5cyc_2X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX, A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_64cyc_2X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX, A57UnitX];
  list<int> ResourceCycles = [32, 32];
  int Latency = 64;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1B_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitB, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1I_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitI, A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1M {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitM];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1V_1X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV, A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1W {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitW];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_1X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_2L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_2V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_6cyc_2W {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitW, A57UnitW];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_7cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_7cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_7cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_7cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_7cyc_1V_1X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV, A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_8cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_8cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_8cyc_1L_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_8cyc_1L_1V_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitV, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_8cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_8cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_8cyc_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_8cyc_2X {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitX, A57UnitX];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_9cyc_1L {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_9cyc_1L_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_9cyc_1L_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_9cyc_1L_1V_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitL, A57UnitV, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_9cyc_1S {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_9cyc_1S_1I {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitS, A57UnitI];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_9cyc_1V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A57Write_9cyc_2V {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A57UnitV, A57UnitV];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def A8_LSPipe {	// FuncUnit
  string NAME = ?;
}
def A8_NLSPipe {	// FuncUnit
  string NAME = ?;
}
def A8_NPipe {	// FuncUnit
  string NAME = ?;
}
def A8_Pipe0 {	// FuncUnit
  string NAME = ?;
}
def A8_Pipe1 {	// FuncUnit
  string NAME = ?;
}
def A9LMAdr1Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{(TII->getNumLDMAddresses(*MI)+1)/2 == 1}];
  string NAME = ?;
}
def A9LMAdr2Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{(TII->getNumLDMAddresses(*MI)+1)/2 == 2}];
  string NAME = ?;
}
def A9LMAdr3Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{(TII->getNumLDMAddresses(*MI)+1)/2 == 3}];
  string NAME = ?;
}
def A9LMAdr4Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{(TII->getNumLDMAddresses(*MI)+1)/2 == 4}];
  string NAME = ?;
}
def A9LMAdr5Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{(TII->getNumLDMAddresses(*MI)+1)/2 == 5}];
  string NAME = ?;
}
def A9LMAdr6Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{(TII->getNumLDMAddresses(*MI)+1)/2 == 6}];
  string NAME = ?;
}
def A9LMAdr7Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{(TII->getNumLDMAddresses(*MI)+1)/2 == 7}];
  string NAME = ?;
}
def A9LMAdr8Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{(TII->getNumLDMAddresses(*MI)+1)/2 == 8}];
  string NAME = ?;
}
def A9LMUnknownPred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 0}];
  string NAME = ?;
}
def A9PostRA {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{TargetRegisterInfo::isPhysicalRegister(MI->getOperand(0).getReg())}];
  string NAME = ?;
}
def A9PreRA {	// SchedPredicate
  SchedMachineModel SchedModel = CortexA9Model;
  code Predicate = [{TargetRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg())}];
  string NAME = ?;
}
def A9Read2 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 1;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9Read3 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 2;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9Read4 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9ReadALU {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 1;
  list<SchedWrite> ValidWrites = [A9WriteL, A9WriteLHi, A9WriteLsi, A9WriteLb, A9WriteLbsi, A9WriteL1, A9WriteL2, A9WriteL3, A9WriteL4, A9WriteL5, A9WriteL6, A9WriteL7, A9WriteL8, A9WriteL1Hi, A9WriteL2Hi, A9WriteL3Hi, A9WriteL4Hi, A9WriteL5Hi, A9WriteL6Hi, A9WriteL7Hi, A9WriteL8Hi];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9UnitAGU {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9UnitALU {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 2;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9UnitB {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9UnitFP {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9UnitLS {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9UnitMul {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = A9UnitALU;
  int BufferSize = -1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9Write2V4 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [2, 1];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9Write2V7 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [2, 1];
  int Latency = 7;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9Write2V9 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [2, 1];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteALU {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteALUsr {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteAdr {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteAdr1 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteAdr];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteAdr2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteAdr];
  int Repeat = 2;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteAdr3 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteAdr];
  int Repeat = 3;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteAdr4 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteAdr];
  int Repeat = 4;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteAdr5 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteAdr];
  int Repeat = 5;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteAdr6 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteAdr];
  int Repeat = 6;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteAdr7 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteAdr];
  int Repeat = 7;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteAdr8 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteAdr];
  int Repeat = 8;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteB {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitB];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteCycle1 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteCycle2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteCycle1];
  int Repeat = 2;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteCycle3 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteCycle1];
  int Repeat = 3;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteCycle4 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteCycle1];
  int Repeat = 4;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteCycle5 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteCycle1];
  int Repeat = 5;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteCycle6 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteCycle1];
  int Repeat = 6;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteCycle7 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteCycle1];
  int Repeat = 7;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteCycle8 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteCycle1];
  int Repeat = 8;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteF {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteFDivD {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 25;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteFDivS {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteFMAD {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteFMAS {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteFMov {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteFMulD {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteFMulS {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteFSqrtD {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 32;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteFSqrtS {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 17;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteI {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteI2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteI, A9WriteI];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteI2ld {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteI, A9WriteI, A9WriteL];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteI2pc {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteI, A9WriteI, WriteALU];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteIsr {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteIssue {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitLS];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL1 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMLo, A9WriteCycle1];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL1Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle1];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMLo, A9WriteCycle2];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL2Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle2];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL3 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMLo, A9WriteCycle3];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL3Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle3];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL4 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMLo, A9WriteCycle4];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL4Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle4];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL5 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMLo, A9WriteCycle5];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL5Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle5];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL6 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMLo, A9WriteCycle6];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL6Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle6];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL7 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMLo, A9WriteCycle7];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL7Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle7];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL8 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMLo, A9WriteCycle8];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteL8Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle8];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLHi {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1677, anonymous_1678, anonymous_1679, anonymous_1680, anonymous_1681, anonymous_1682, anonymous_1683, anonymous_1684, anonymous_1685];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMAdr {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1668, anonymous_1669, anonymous_1670, anonymous_1671, anonymous_1672, anonymous_1673, anonymous_1674, anonymous_1675, anonymous_1676];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMHi {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMLo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitLS];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMOpsList {	// A9WriteLMOpsListType
  list<WriteSequence> Writes = [A9WriteL1, A9WriteL1Hi, A9WriteL2, A9WriteL2Hi, A9WriteL3, A9WriteL3Hi, A9WriteL4, A9WriteL4Hi, A9WriteL5, A9WriteL5Hi, A9WriteL6, A9WriteL6Hi, A9WriteL7, A9WriteL7Hi, A9WriteL8, A9WriteL8Hi];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1704, anonymous_1705];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp1 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMfpLo, A9WriteCycle1];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp1Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle1];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMfpLo, A9WriteCycle2];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp2Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle2];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp3 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMfpLo, A9WriteCycle3];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp3Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle3];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp4 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMfpLo, A9WriteCycle4];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp4Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle4];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp5 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMfpLo, A9WriteCycle5];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp5Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle5];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp6 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMfpLo, A9WriteCycle6];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp6Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle6];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp7 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMfpLo, A9WriteCycle7];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp7Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle7];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp8 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMfpLo, A9WriteCycle8];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfp8Hi {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLMHi, A9WriteCycle8];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfpLo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitLS, A9UnitFP];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfpPostRA {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1695, anonymous_1696, anonymous_1697, anonymous_1698, anonymous_1699, anonymous_1700, anonymous_1701, anonymous_1702, anonymous_1703];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfpPostRAOpsList {	// A9WriteLMOpsListType
  list<WriteSequence> Writes = [A9WriteLMfp1, A9WriteLMfp2, A9WriteLMfp3, A9WriteLMfp4, A9WriteLMfp5, A9WriteLMfp6, A9WriteLMfp7, A9WriteLMfp8, A9WriteLMfp1Hi, A9WriteLMfp2Hi, A9WriteLMfp2Hi, A9WriteLMfp3Hi, A9WriteLMfp3Hi, A9WriteLMfp4Hi, A9WriteLMfp4Hi, A9WriteLMfp5Hi, A9WriteLMfp5Hi, A9WriteLMfp6Hi, A9WriteLMfp6Hi, A9WriteLMfp7Hi, A9WriteLMfp7Hi, A9WriteLMfp8Hi, A9WriteLMfp8Hi];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLMfpPreRA {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1686, anonymous_1687, anonymous_1688, anonymous_1689, anonymous_1690, anonymous_1691, anonymous_1692, anonymous_1693, anonymous_1694];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLSfp {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitLS, A9UnitFP];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLb {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitLS];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLbsi {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitLS];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp1 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteIssue, A9WriteLfp1Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp1Mov {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteF, A9WriteLfp1Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp1Seq {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLfpOp];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteIssue, A9WriteLfp2Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp2Mov {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteF, A9WriteLfp2Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp2Seq {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLfpOp];
  int Repeat = 2;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp3 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteIssue, A9WriteLfp3Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp3Mov {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteF, A9WriteLfp3Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp3Seq {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLfpOp];
  int Repeat = 3;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp4 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteIssue, A9WriteLfp4Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp4Mov {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteF, A9WriteLfp4Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp4Seq {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLfpOp];
  int Repeat = 4;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp5 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteIssue, A9WriteLfp5Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp5Mov {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteF, A9WriteLfp5Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp5Seq {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLfpOp];
  int Repeat = 5;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp6 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteIssue, A9WriteLfp6Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp6Mov {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteF, A9WriteLfp6Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp6Seq {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLfpOp];
  int Repeat = 6;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp7 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteIssue, A9WriteLfp7Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp7Mov {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteF, A9WriteLfp7Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp7Seq {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLfpOp];
  int Repeat = 7;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp8 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteIssue, A9WriteLfp8Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp8Mov {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteF, A9WriteLfp8Seq];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfp8Seq {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [A9WriteLfpOp];
  int Repeat = 8;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLfpOp {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitLS, A9UnitFP];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteLsi {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitLS];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteM {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitMul, A9UnitMul];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteM16 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitMul];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteM16Hi {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitMul];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteMHi {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitMul];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteS {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitLS];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteV1 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteV10 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteV2 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteV3 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteV4 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteV5 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteV6 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteV7 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9WriteV9 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def A9_AGU {	// FuncUnit
  string NAME = ?;
}
def A9_ALU0 {	// FuncUnit
  string NAME = ?;
}
def A9_ALU1 {	// FuncUnit
  string NAME = ?;
}
def A9_Branch {	// FuncUnit
  string NAME = ?;
}
def A9_DRegsN {	// FuncUnit
  string NAME = ?;
}
def A9_DRegsVFP {	// FuncUnit
  string NAME = ?;
}
def A9_Issue0 {	// FuncUnit
  string NAME = ?;
}
def A9_Issue1 {	// FuncUnit
  string NAME = ?;
}
def A9_LSUnit {	// FuncUnit
  string NAME = ?;
}
def A9_LdBypass {	// Bypass
  string NAME = ?;
}
def A9_MUX0 {	// FuncUnit
  string NAME = ?;
}
def A9_NPipe {	// FuncUnit
  string NAME = ?;
}
def ABS {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins GPR:$src);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 8;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def ADCri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 0, 1, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "adc${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMadde GPR:$Rn, mod_imm:$imm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ADCrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "adc${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMadde GPR:$Rn, GPR:$Rm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def ADCrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "adc${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMadde GPR:$Rn, so_reg_imm:$shift, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ADCrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "adc${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPRnopc:$Rd, CPSR, (ARMadde GPRnopc:$Rn, so_reg_reg:$shift, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ADDSri {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMaddc GPR:$Rn, mod_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def ADDSrr {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMaddc GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def ADDSrsi {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMaddc GPR:$Rn, so_reg_imm:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def ADDSrsr {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMaddc GPR:$Rn, so_reg_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUSsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def ADDri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 0, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "add${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, (add GPR:$Rn, mod_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ADDrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "add${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (add GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def ADDrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "add${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (add GPR:$Rn, so_reg_imm:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ADDrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "add${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (add GPR:$Rn, so_reg_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ADJCALLSTACKDOWN {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$amt, i32imm:$amt2, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(ARMcallseq_start timm:$amt, timm:$amt2)];
  list<Register> Uses = [SP];
  list<Register> Defs = [SP];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def ADJCALLSTACKUP {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$amt1, i32imm:$amt2, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(ARMcallseq_end timm:$amt1, timm:$amt2)];
  list<Register> Uses = [SP];
  list<Register> Defs = [SP];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def ADR {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 0, label{13}, label{12}, 0, 0, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, label{11}, label{10}, label{9}, label{8}, label{7}, label{6}, label{5}, label{4}, label{3}, label{2}, label{1}, label{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins adrlabel:$label, pred:$p);
  string AsmString = "adr${p}	$Rd, $label";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<14> label = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def AESD {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntX2np Requires AES2Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vm);
  string AsmString = "aesd.8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_aesd (v16i8 QPR:$src), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def AESE {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntX2np Requires AES2Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vm);
  string AsmString = "aese.8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_aese (v16i8 QPR:$src), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def AESIMC {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntXnp Requires AES
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "aesimc.8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_aesimc (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def AESMC {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntXnp Requires AES
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "aesmc.8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_aesmc (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def AM2OffsetImmAsmOperand {	// AsmOperandClass
  string Name = "AM2OffsetImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AM3OffsetAsmOperand {	// AsmOperandClass
  string Name = "AM3Offset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseAM3Offset";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AMDGPUDim1D {	// AMDGPUDimProps
  string Name = "1d";
  bit DA = 0;
  list<AMDGPUArg> CoordSliceArgs = [anonymous_31];
  list<AMDGPUArg> CoordSliceIntArgs = [anonymous_33];
  list<AMDGPUArg> GradientArgs = [anonymous_35, anonymous_36];
  string NAME = ?;
}
def AMDGPUDim1DArray {	// AMDGPUDimProps
  string Name = "1darray";
  bit DA = 1;
  list<AMDGPUArg> CoordSliceArgs = [anonymous_31, anonymous_53];
  list<AMDGPUArg> CoordSliceIntArgs = [anonymous_33, anonymous_53];
  list<AMDGPUArg> GradientArgs = [anonymous_35, anonymous_36];
  string NAME = ?;
}
def AMDGPUDim2D {	// AMDGPUDimProps
  string Name = "2d";
  bit DA = 0;
  list<AMDGPUArg> CoordSliceArgs = [anonymous_31, anonymous_38];
  list<AMDGPUArg> CoordSliceIntArgs = [anonymous_33, anonymous_38];
  list<AMDGPUArg> GradientArgs = [anonymous_35, anonymous_41, anonymous_36, anonymous_42];
  string NAME = ?;
}
def AMDGPUDim2DArray {	// AMDGPUDimProps
  string Name = "2darray";
  bit DA = 1;
  list<AMDGPUArg> CoordSliceArgs = [anonymous_31, anonymous_38, anonymous_53];
  list<AMDGPUArg> CoordSliceIntArgs = [anonymous_33, anonymous_38, anonymous_53];
  list<AMDGPUArg> GradientArgs = [anonymous_35, anonymous_41, anonymous_36, anonymous_42];
  string NAME = ?;
}
def AMDGPUDim2DArrayMsaa {	// AMDGPUDimProps
  string Name = "2darraymsaa";
  bit DA = 1;
  list<AMDGPUArg> CoordSliceArgs = [anonymous_31, anonymous_38, anonymous_53, anonymous_58];
  list<AMDGPUArg> CoordSliceIntArgs = [anonymous_33, anonymous_38, anonymous_53, anonymous_58];
  list<AMDGPUArg> GradientArgs = [anonymous_35, anonymous_41, anonymous_36, anonymous_42];
  string NAME = ?;
}
def AMDGPUDim2DMsaa {	// AMDGPUDimProps
  string Name = "2dmsaa";
  bit DA = 0;
  list<AMDGPUArg> CoordSliceArgs = [anonymous_31, anonymous_38, anonymous_58];
  list<AMDGPUArg> CoordSliceIntArgs = [anonymous_33, anonymous_38, anonymous_58];
  list<AMDGPUArg> GradientArgs = [anonymous_35, anonymous_41, anonymous_36, anonymous_42];
  string NAME = ?;
}
def AMDGPUDim3D {	// AMDGPUDimProps
  string Name = "3d";
  bit DA = 0;
  list<AMDGPUArg> CoordSliceArgs = [anonymous_31, anonymous_38, anonymous_44];
  list<AMDGPUArg> CoordSliceIntArgs = [anonymous_33, anonymous_38, anonymous_44];
  list<AMDGPUArg> GradientArgs = [anonymous_35, anonymous_41, anonymous_47, anonymous_36, anonymous_42, anonymous_48];
  string NAME = ?;
}
def AMDGPUDimCube {	// AMDGPUDimProps
  string Name = "cube";
  bit DA = 1;
  list<AMDGPUArg> CoordSliceArgs = [anonymous_31, anonymous_38, anonymous_50];
  list<AMDGPUArg> CoordSliceIntArgs = [anonymous_33, anonymous_38, anonymous_50];
  list<AMDGPUArg> GradientArgs = [anonymous_35, anonymous_41, anonymous_36, anonymous_42];
  string NAME = ?;
}
def AMDGPUDims {
  list<AMDGPUDimProps> NoMsaa = [AMDGPUDim1D, AMDGPUDim2D, AMDGPUDim3D, AMDGPUDimCube, AMDGPUDim1DArray, AMDGPUDim2DArray];
  list<AMDGPUDimProps> Msaa = [AMDGPUDim2DMsaa, AMDGPUDim2DArrayMsaa];
  list<AMDGPUDimProps> All = [AMDGPUDim1D, AMDGPUDim2D, AMDGPUDim3D, AMDGPUDimCube, AMDGPUDim1DArray, AMDGPUDim2DArray, AMDGPUDim2DMsaa, AMDGPUDim2DArrayMsaa];
  string NAME = ?;
}
def AMDGPUSample {	// AMDGPUSampleVariant
  string UpperCaseMod = "";
  string LowerCaseMod = "";
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_b {	// AMDGPUSampleVariant
  string UpperCaseMod = "_B";
  string LowerCaseMod = "_b";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_b_cl {	// AMDGPUSampleVariant
  string UpperCaseMod = "_B_CL";
  string LowerCaseMod = "_b_cl";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_b_cl_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_B_CL_O";
  string LowerCaseMod = "_b_cl_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_b_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_B_O";
  string LowerCaseMod = "_b_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C";
  string LowerCaseMod = "_c";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c_b {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_B";
  string LowerCaseMod = "_c_b";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c_b_cl {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_B_CL";
  string LowerCaseMod = "_c_b_cl";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_c_b_cl_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_B_CL_O";
  string LowerCaseMod = "_c_b_cl_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_c_b_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_B_O";
  string LowerCaseMod = "_c_b_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c_cd {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_CD";
  string LowerCaseMod = "_c_cd";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c_cd_cl {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_CD_CL";
  string LowerCaseMod = "_c_cd_cl";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_c_cd_cl_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_CD_CL_O";
  string LowerCaseMod = "_c_cd_cl_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_c_cd_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_CD_O";
  string LowerCaseMod = "_c_cd_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c_cl {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_CL";
  string LowerCaseMod = "_c_cl";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_c_cl_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_CL_O";
  string LowerCaseMod = "_c_cl_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_c_d {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_D";
  string LowerCaseMod = "_c_d";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c_d_cl {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_D_CL";
  string LowerCaseMod = "_c_d_cl";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_c_d_cl_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_D_CL_O";
  string LowerCaseMod = "_c_d_cl_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_c_d_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_D_O";
  string LowerCaseMod = "_c_d_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c_l {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_L";
  string LowerCaseMod = "_c_l";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "lod";
  string NAME = ?;
}
def AMDGPUSample_c_l_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_L_O";
  string LowerCaseMod = "_c_l_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "lod";
  string NAME = ?;
}
def AMDGPUSample_c_lz {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_LZ";
  string LowerCaseMod = "_c_lz";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c_lz_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_LZ_O";
  string LowerCaseMod = "_c_lz_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_c_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_C_O";
  string LowerCaseMod = "_c_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_cd {	// AMDGPUSampleVariant
  string UpperCaseMod = "_CD";
  string LowerCaseMod = "_cd";
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_cd_cl {	// AMDGPUSampleVariant
  string UpperCaseMod = "_CD_CL";
  string LowerCaseMod = "_cd_cl";
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_cd_cl_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_CD_CL_O";
  string LowerCaseMod = "_cd_cl_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_cd_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_CD_O";
  string LowerCaseMod = "_cd_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_cl {	// AMDGPUSampleVariant
  string UpperCaseMod = "_CL";
  string LowerCaseMod = "_cl";
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_cl_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_CL_O";
  string LowerCaseMod = "_cl_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_d {	// AMDGPUSampleVariant
  string UpperCaseMod = "_D";
  string LowerCaseMod = "_d";
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_d_cl {	// AMDGPUSampleVariant
  string UpperCaseMod = "_D_CL";
  string LowerCaseMod = "_d_cl";
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_d_cl_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_D_CL_O";
  string LowerCaseMod = "_d_cl_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodOrClamp = "clamp";
  string NAME = ?;
}
def AMDGPUSample_d_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_D_O";
  string LowerCaseMod = "_d_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_l {	// AMDGPUSampleVariant
  string UpperCaseMod = "_L";
  string LowerCaseMod = "_l";
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodOrClamp = "lod";
  string NAME = ?;
}
def AMDGPUSample_l_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_L_O";
  string LowerCaseMod = "_l_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodOrClamp = "lod";
  string NAME = ?;
}
def AMDGPUSample_lz {	// AMDGPUSampleVariant
  string UpperCaseMod = "_LZ";
  string LowerCaseMod = "_lz";
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_lz_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_LZ_O";
  string LowerCaseMod = "_lz_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def AMDGPUSample_o {	// AMDGPUSampleVariant
  string UpperCaseMod = "_O";
  string LowerCaseMod = "_o";
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodOrClamp = "";
  string NAME = ?;
}
def ANDri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 0, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "and${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, (and GPR:$Rn, mod_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ANDrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "and${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (and GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def ANDrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "and${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (and GPR:$Rn, so_reg_imm:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ANDrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "and${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (and GPR:$Rn, so_reg_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ANNOTATION_LABEL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$id);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 1;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def APSR {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "apsr";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def APSR_NZCV {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "apsr_nzcv";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def ARM {	// Target
  InstrInfo InstructionSet = ARMInstrInfo;
  list<AsmParser> AssemblyParsers = [ARMAsmParser];
  list<AsmParserVariant> AssemblyParserVariants = [ARMAsmParserVariant];
  list<AsmWriter> AssemblyWriters = [ARMAsmWriter];
  int AllowRegisterRenaming = 1;
  string NAME = ?;
}
def ARMAsmParser {	// AsmParser
  string AsmParserClassName = "AsmParser";
  string AsmParserInstCleanup = "";
  bit ShouldEmitMatchRegisterName = 1;
  bit ShouldEmitMatchRegisterAltName = 0;
  bit AllowDuplicateRegisterNames = 0;
  bit HasMnemonicFirst = 1;
  bit ReportMultipleNearMisses = 1;
  string NAME = ?;
}
def ARMAsmParserVariant {	// AsmParserVariant
  int Variant = 0;
  string Name = "ARM";
  string CommentDelimiter = "";
  string RegisterPrefix = "";
  string TokenizingCharacters = "[]*!";
  string SeparatorCharacters = " 	,";
  string BreakCharacters = ".";
  string NAME = ?;
}
def ARMAsmWriter {	// AsmWriter
  string AsmWriterClassName = "InstPrinter";
  int PassSubtarget = 1;
  int Variant = 0;
  bit isMCAsmWriter = 1;
  string NAME = ?;
}
def ARMBcci64 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ARMISD::BCC_i64";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMBCC_i64;
  string NAME = ?;
}
def ARMBranchTarget {	// AsmOperandClass
  string Name = "ARMBranchTarget";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ARMInstrInfo {	// InstrInfo
  bit isLittleEndianEncoding = 0;
  bit guessInstructionProperties = 1;
  bit decodePositionallyEncodedOperands = 0;
  bit noNamedPositionallyEncodedOperands = 0;
  string NAME = ?;
}
def ARMMemBarrierMCR {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ARMISD::MEMBARRIER_MCR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMMEMBARRIER;
  string NAME = ?;
}
def ARMPreload {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayLoad, SDNPMayStore];
  string Opcode = "ARMISD::PRELOAD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMPREFETCH;
  string NAME = ?;
}
def ARMSmlald {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMLALD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_LongMac;
  string NAME = ?;
}
def ARMSmlaldx {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMLALDX";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_LongMac;
  string NAME = ?;
}
def ARMSmlsld {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMLSLD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_LongMac;
  string NAME = ?;
}
def ARMSmlsldx {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMLSLDX";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_LongMac;
  string NAME = ?;
}
def ARMV6Itineraries {	// ProcessorItineraries
  list<FuncUnit> FU = [V6_Pipe];
  list<Bypass> BP = [];
  list<InstrItinData> IID = [anonymous_940, anonymous_941, anonymous_942, anonymous_943, anonymous_945, anonymous_946, anonymous_947, anonymous_948, anonymous_949, anonymous_950, anonymous_951, anonymous_952, anonymous_953, anonymous_954, anonymous_955, anonymous_956, anonymous_957, anonymous_958, anonymous_959, anonymous_960, anonymous_961, anonymous_962, anonymous_963, anonymous_964, anonymous_965, anonymous_966, anonymous_967, anonymous_968, anonymous_969, anonymous_970, anonymous_971, anonymous_972, anonymous_973, anonymous_974, anonymous_975, anonymous_976, anonymous_977, anonymous_978, anonymous_979, anonymous_980, anonymous_981, anonymous_982, anonymous_984, anonymous_985, anonymous_986, anonymous_987, anonymous_988, anonymous_989, anonymous_990, anonymous_991, anonymous_992, anonymous_993, anonymous_994, anonymous_995, anonymous_996, anonymous_997, anonymous_998, anonymous_999, anonymous_1000, anonymous_1001, anonymous_1002, anonymous_1003, anonymous_1004, anonymous_1005, anonymous_1006, anonymous_1007, anonymous_1008, anonymous_1009, anonymous_1010, anonymous_1011, anonymous_1012, anonymous_1013, anonymous_1014, anonymous_1015, anonymous_1016, anonymous_1017, anonymous_1018, anonymous_1019, anonymous_1020, anonymous_1021, anonymous_1022, anonymous_1023, anonymous_1024, anonymous_1025, anonymous_1026, anonymous_1027, anonymous_1028, anonymous_1029, anonymous_1030, anonymous_1031, anonymous_1032, anonymous_1033, anonymous_1034, anonymous_1035, anonymous_1036, anonymous_1037, anonymous_1038, anonymous_1039, anonymous_1040, anonymous_1041, anonymous_1042, anonymous_1043, anonymous_1045, anonymous_1047, anonymous_1048, anonymous_1049, anonymous_1050, anonymous_1051, anonymous_1052, anonymous_1053, anonymous_1054, anonymous_1055, anonymous_1056, anonymous_1057, anonymous_1058, anonymous_1059, anonymous_1060, anonymous_1061];
  string NAME = ?;
}
def ARMWrapper {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::Wrapper";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def ARMWrapperJT {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::WrapperJT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def ARMWrapperPIC {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::WrapperPIC";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def ARMaddc {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative];
  string Opcode = "ARMISD::ADDC";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTBinaryArithWithFlags;
  string NAME = ?;
}
def ARMadde {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::ADDE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTBinaryArithWithFlagsInOut;
  string NAME = ?;
}
def ARMbfi {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::BFI";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMBFI;
  string NAME = ?;
}
def ARMbr2jt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ARMISD::BR2_JT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMBr2JT;
  string NAME = ?;
}
def ARMbrcond {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPInGlue, SDNPOutGlue];
  string Opcode = "ARMISD::BRCOND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMBrcond;
  string NAME = ?;
}
def ARMbrjt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ARMISD::BR_JT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMBrJT;
  string NAME = ?;
}
def ARMcall {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic];
  string Opcode = "ARMISD::CALL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMcall;
  string NAME = ?;
}
def ARMcall_nolink {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic];
  string Opcode = "ARMISD::CALL_NOLINK";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMcall;
  string NAME = ?;
}
def ARMcall_pred {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic];
  string Opcode = "ARMISD::CALL_PRED";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMcall;
  string NAME = ?;
}
def ARMcallseq_end {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue];
  string Opcode = "ISD::CALLSEQ_END";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMCallSeqEnd;
  string NAME = ?;
}
def ARMcallseq_start {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect, SDNPOutGlue];
  string Opcode = "ISD::CALLSEQ_START";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMCallSeqStart;
  string NAME = ?;
}
def ARMcmn {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPOutGlue];
  string Opcode = "ARMISD::CMN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMCmp;
  string NAME = ?;
}
def ARMcmov {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPInGlue];
  string Opcode = "ARMISD::CMOV";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMCMov;
  string NAME = ?;
}
def ARMcmp {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPOutGlue];
  string Opcode = "ARMISD::CMP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMCmp;
  string NAME = ?;
}
def ARMcmpZ {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPOutGlue, SDNPCommutative];
  string Opcode = "ARMISD::CMPZ";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMCmp;
  string NAME = ?;
}
def ARMcopystructbyval {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, SDNPMayLoad];
  string Opcode = "ARMISD::COPY_STRUCT_BYVAL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMStructByVal;
  string NAME = ?;
}
def ARMeh_sjlj_longjmp {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ARMISD::EH_SJLJ_LONGJMP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMEH_SJLJ_Longjmp;
  string NAME = ?;
}
def ARMeh_sjlj_setjmp {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ARMISD::EH_SJLJ_SETJMP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMEH_SJLJ_Setjmp;
  string NAME = ?;
}
def ARMeh_sjlj_setup_dispatch {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ARMISD::EH_SJLJ_SETUP_DISPATCH";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMEH_SJLJ_SetupDispatch;
  string NAME = ?;
}
def ARMintretflag {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPOptInGlue, SDNPVariadic];
  string Opcode = "ARMISD::INTRET_FLAG";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMcall;
  string NAME = ?;
}
def ARMmemcopy {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, SDNPMayLoad];
  string Opcode = "ARMISD::MEMCPY";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMMEMCPY;
  string NAME = ?;
}
def ARMpic_add {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::PIC_ADD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMPICAdd;
  string NAME = ?;
}
def ARMretflag {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPOptInGlue, SDNPVariadic];
  string Opcode = "ARMISD::RET_FLAG";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTNone;
  string NAME = ?;
}
def ARMrrx {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPInGlue];
  string Opcode = "ARMISD::RRX";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def ARMsmlalbb {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMLALBB";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_LongMac;
  string NAME = ?;
}
def ARMsmlalbt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMLALBT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_LongMac;
  string NAME = ?;
}
def ARMsmlaltb {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMLALTB";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_LongMac;
  string NAME = ?;
}
def ARMsmlaltt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMLALTT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_LongMac;
  string NAME = ?;
}
def ARMsmmlar {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMMLAR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_MulHSR;
  string NAME = ?;
}
def ARMsmmlsr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMMLSR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_MulHSR;
  string NAME = ?;
}
def ARMsmulwb {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMULWB";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def ARMsmulwt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SMULWT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def ARMsra_flag {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPOutGlue];
  string Opcode = "ARMISD::SRA_FLAG";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def ARMsrl_flag {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPOutGlue];
  string Opcode = "ARMISD::SRL_FLAG";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def ARMssatnoshift {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SSAT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntSatNoShOp;
  string NAME = ?;
}
def ARMsubc {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SUBC";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTBinaryArithWithFlags;
  string NAME = ?;
}
def ARMsube {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::SUBE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTBinaryArithWithFlagsInOut;
  string NAME = ?;
}
def ARMtcret {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPOptInGlue, SDNPVariadic];
  string Opcode = "ARMISD::TC_RETURN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMTCRET;
  string NAME = ?;
}
def ARMthread_pointer {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::THREAD_POINTER";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMThreadPointer;
  string NAME = ?;
}
def ARMusatnoshift {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::USAT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntSatNoShOp;
  string NAME = ?;
}
def ARMv2 {	// SubtargetFeature Architecture
  string Name = "armv2";
  string Attribute = "ARMArch";
  string Value = "ARMv2";
  string Desc = "ARMv2 architecture";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ARMv2a {	// SubtargetFeature Architecture
  string Name = "armv2a";
  string Attribute = "ARMArch";
  string Value = "ARMv2a";
  string Desc = "ARMv2a architecture";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ARMv3 {	// SubtargetFeature Architecture
  string Name = "armv3";
  string Attribute = "ARMArch";
  string Value = "ARMv3";
  string Desc = "ARMv3 architecture";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ARMv3m {	// SubtargetFeature Architecture
  string Name = "armv3m";
  string Attribute = "ARMArch";
  string Value = "ARMv3m";
  string Desc = "ARMv3m architecture";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ARMv4 {	// SubtargetFeature Architecture
  string Name = "armv4";
  string Attribute = "ARMArch";
  string Value = "ARMv4";
  string Desc = "ARMv4 architecture";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ARMv4t {	// SubtargetFeature Architecture
  string Name = "armv4t";
  string Attribute = "ARMArch";
  string Value = "ARMv4t";
  string Desc = "ARMv4t architecture";
  list<SubtargetFeature> Implies = [HasV4TOps];
  string NAME = ?;
}
def ARMv5t {	// SubtargetFeature Architecture
  string Name = "armv5t";
  string Attribute = "ARMArch";
  string Value = "ARMv5t";
  string Desc = "ARMv5t architecture";
  list<SubtargetFeature> Implies = [HasV5TOps];
  string NAME = ?;
}
def ARMv5te {	// SubtargetFeature Architecture
  string Name = "armv5te";
  string Attribute = "ARMArch";
  string Value = "ARMv5te";
  string Desc = "ARMv5te architecture";
  list<SubtargetFeature> Implies = [HasV5TEOps];
  string NAME = ?;
}
def ARMv5tej {	// SubtargetFeature Architecture
  string Name = "armv5tej";
  string Attribute = "ARMArch";
  string Value = "ARMv5tej";
  string Desc = "ARMv5tej architecture";
  list<SubtargetFeature> Implies = [HasV5TEOps];
  string NAME = ?;
}
def ARMv6 {	// SubtargetFeature Architecture
  string Name = "armv6";
  string Attribute = "ARMArch";
  string Value = "ARMv6";
  string Desc = "ARMv6 architecture";
  list<SubtargetFeature> Implies = [HasV6Ops, FeatureDSP];
  string NAME = ?;
}
def ARMv6j {	// SubtargetFeature Architecture
  string Name = "armv6j";
  string Attribute = "ARMArch";
  string Value = "ARMv7a";
  string Desc = "ARMv7a architecture";
  list<SubtargetFeature> Implies = [ARMv6];
  string NAME = ?;
}
def ARMv6k {	// SubtargetFeature Architecture
  string Name = "armv6k";
  string Attribute = "ARMArch";
  string Value = "ARMv6k";
  string Desc = "ARMv6k architecture";
  list<SubtargetFeature> Implies = [HasV6KOps];
  string NAME = ?;
}
def ARMv6kz {	// SubtargetFeature Architecture
  string Name = "armv6kz";
  string Attribute = "ARMArch";
  string Value = "ARMv6kz";
  string Desc = "ARMv6kz architecture";
  list<SubtargetFeature> Implies = [HasV6KOps, FeatureTrustZone];
  string NAME = ?;
}
def ARMv6m {	// SubtargetFeature Architecture
  string Name = "armv6-m";
  string Attribute = "ARMArch";
  string Value = "ARMv6m";
  string Desc = "ARMv6m architecture";
  list<SubtargetFeature> Implies = [HasV6MOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureMClass];
  string NAME = ?;
}
def ARMv6sm {	// SubtargetFeature Architecture
  string Name = "armv6s-m";
  string Attribute = "ARMArch";
  string Value = "ARMv6sm";
  string Desc = "ARMv6sm architecture";
  list<SubtargetFeature> Implies = [HasV6MOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureMClass];
  string NAME = ?;
}
def ARMv6t2 {	// SubtargetFeature Architecture
  string Name = "armv6t2";
  string Attribute = "ARMArch";
  string Value = "ARMv6t2";
  string Desc = "ARMv6t2 architecture";
  list<SubtargetFeature> Implies = [HasV6T2Ops, FeatureDSP];
  string NAME = ?;
}
def ARMv7a {	// SubtargetFeature Architecture
  string Name = "armv7-a";
  string Attribute = "ARMArch";
  string Value = "ARMv7a";
  string Desc = "ARMv7a architecture";
  list<SubtargetFeature> Implies = [HasV7Ops, FeatureNEON, FeatureDB, FeatureDSP, FeatureAClass];
  string NAME = ?;
}
def ARMv7em {	// SubtargetFeature Architecture
  string Name = "armv7e-m";
  string Attribute = "ARMArch";
  string Value = "ARMv7em";
  string Desc = "ARMv7em architecture";
  list<SubtargetFeature> Implies = [HasV7Ops, FeatureThumb2, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass, FeatureDSP];
  string NAME = ?;
}
def ARMv7k {	// SubtargetFeature Architecture
  string Name = "armv7k";
  string Attribute = "ARMArch";
  string Value = "ARMv7a";
  string Desc = "ARMv7a architecture";
  list<SubtargetFeature> Implies = [ARMv7a];
  string NAME = ?;
}
def ARMv7m {	// SubtargetFeature Architecture
  string Name = "armv7-m";
  string Attribute = "ARMArch";
  string Value = "ARMv7m";
  string Desc = "ARMv7m architecture";
  list<SubtargetFeature> Implies = [HasV7Ops, FeatureThumb2, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass];
  string NAME = ?;
}
def ARMv7r {	// SubtargetFeature Architecture
  string Name = "armv7-r";
  string Attribute = "ARMArch";
  string Value = "ARMv7r";
  string Desc = "ARMv7r architecture";
  list<SubtargetFeature> Implies = [HasV7Ops, FeatureDB, FeatureDSP, FeatureHWDivThumb, FeatureRClass];
  string NAME = ?;
}
def ARMv7s {	// SubtargetFeature Architecture
  string Name = "armv7s";
  string Attribute = "ARMArch";
  string Value = "ARMv7a";
  string Desc = "ARMv7a architecture";
  list<SubtargetFeature> Implies = [ARMv7a];
  string NAME = ?;
}
def ARMv7ve {	// SubtargetFeature Architecture
  string Name = "armv7ve";
  string Attribute = "ARMArch";
  string Value = "ARMv7ve";
  string Desc = "ARMv7ve architecture";
  list<SubtargetFeature> Implies = [HasV7Ops, FeatureNEON, FeatureDB, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureAClass];
  string NAME = ?;
}
def ARMv81a {	// SubtargetFeature Architecture
  string Name = "armv8.1-a";
  string Attribute = "ARMArch";
  string Value = "ARMv81a";
  string Desc = "ARMv81a architecture";
  list<SubtargetFeature> Implies = [HasV8_1aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def ARMv82a {	// SubtargetFeature Architecture
  string Name = "armv8.2-a";
  string Attribute = "ARMArch";
  string Value = "ARMv82a";
  string Desc = "ARMv82a architecture";
  list<SubtargetFeature> Implies = [HasV8_2aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS];
  string NAME = ?;
}
def ARMv83a {	// SubtargetFeature Architecture
  string Name = "armv8.3-a";
  string Attribute = "ARMArch";
  string Value = "ARMv83a";
  string Desc = "ARMv83a architecture";
  list<SubtargetFeature> Implies = [HasV8_3aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS];
  string NAME = ?;
}
def ARMv8a {	// SubtargetFeature Architecture
  string Name = "armv8-a";
  string Attribute = "ARMArch";
  string Value = "ARMv8a";
  string Desc = "ARMv8a architecture";
  list<SubtargetFeature> Implies = [HasV8Ops, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def ARMv8mBaseline {	// SubtargetFeature Architecture
  string Name = "armv8-m.base";
  string Attribute = "ARMArch";
  string Value = "ARMv8mBaseline";
  string Desc = "ARMv8mBaseline architecture";
  list<SubtargetFeature> Implies = [HasV8MBaselineOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureV7Clrex, Feature8MSecExt, FeatureAcquireRelease, FeatureMClass];
  string NAME = ?;
}
def ARMv8mMainline {	// SubtargetFeature Architecture
  string Name = "armv8-m.main";
  string Attribute = "ARMArch";
  string Value = "ARMv8mMainline";
  string Desc = "ARMv8mMainline architecture";
  list<SubtargetFeature> Implies = [HasV8MMainlineOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, Feature8MSecExt, FeatureAcquireRelease, FeatureMClass];
  string NAME = ?;
}
def ARMv8r {	// SubtargetFeature Architecture
  string Name = "armv8-r";
  string Attribute = "ARMArch";
  string Value = "ARMv8r";
  string Desc = "ARMv8r architecture";
  list<SubtargetFeature> Implies = [HasV8Ops, FeatureRClass, FeatureDB, FeatureDFB, FeatureDSP, FeatureCRC, FeatureMP, FeatureVirtualization, FeatureFPARMv8, FeatureNEON];
  string NAME = ?;
}
def ASRi {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s);
  string AsmString = "asr${s}${p} $Rd, $Rm, $imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rm = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def ASRr {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s);
  string AsmString = "asr${s}${p} $Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def AddrMode1 {	// AddrMode
  bits<5> Value = { 0, 0, 0, 0, 1 };
  string NAME = ?;
}
def AddrMode2 {	// AddrMode
  bits<5> Value = { 0, 0, 0, 1, 0 };
  string NAME = ?;
}
def AddrMode3 {	// AddrMode
  bits<5> Value = { 0, 0, 0, 1, 1 };
  string NAME = ?;
}
def AddrMode3AsmOperand {	// AsmOperandClass
  string Name = "AddrMode3";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode4 {	// AddrMode
  bits<5> Value = { 0, 0, 1, 0, 0 };
  string NAME = ?;
}
def AddrMode5 {	// AddrMode
  bits<5> Value = { 0, 0, 1, 0, 1 };
  string NAME = ?;
}
def AddrMode5AsmOperand {	// AsmOperandClass
  string Name = "AddrMode5";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode5FP16 {	// AddrMode
  bits<5> Value = { 1, 0, 0, 0, 1 };
  string NAME = ?;
}
def AddrMode5FP16AsmOperand {	// AsmOperandClass
  string Name = "AddrMode5FP16";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6 {	// AddrMode
  bits<5> Value = { 0, 0, 1, 1, 0 };
  string NAME = ?;
}
def AddrMode6Align16AsmOperand {	// AsmOperandClass
  string Name = "AlignedMemory16";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be 16 or omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6Align32AsmOperand {	// AsmOperandClass
  string Name = "AlignedMemory32";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be 32 or omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6Align64AsmOperand {	// AsmOperandClass
  string Name = "AlignedMemory64";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be 64 or omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6Align64or128AsmOperand {	// AsmOperandClass
  string Name = "AlignedMemory64or128";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be 64, 128 or omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6Align64or128or256AsmOperand {	// AsmOperandClass
  string Name = "AlignedMemory64or128or256";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be 64, 128, 256 or omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6AlignNoneAsmOperand {	// AsmOperandClass
  string Name = "AlignedMemoryNone";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6AsmOperand {	// AsmOperandClass
  string Name = "AlignedMemory";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6dupAlign16AsmOperand {	// AsmOperandClass
  string Name = "DupAlignedMemory16";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be 16 or omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6dupAlign32AsmOperand {	// AsmOperandClass
  string Name = "DupAlignedMemory32";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be 32 or omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6dupAlign64AsmOperand {	// AsmOperandClass
  string Name = "DupAlignedMemory64";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be 64 or omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6dupAlign64or128AsmOperand {	// AsmOperandClass
  string Name = "DupAlignedMemory64or128";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be 64, 128 or omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrMode6dupAlignNoneAsmOperand {	// AsmOperandClass
  string Name = "DupAlignedMemoryNone";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "alignment must be omitted";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def AddrModeNone {	// AddrMode
  bits<5> Value = { 0, 0, 0, 0, 0 };
  string NAME = ?;
}
def AddrModeT1_1 {	// AddrMode
  bits<5> Value = { 0, 0, 1, 1, 1 };
  string NAME = ?;
}
def AddrModeT1_2 {	// AddrMode
  bits<5> Value = { 0, 1, 0, 0, 0 };
  string NAME = ?;
}
def AddrModeT1_4 {	// AddrMode
  bits<5> Value = { 0, 1, 0, 0, 1 };
  string NAME = ?;
}
def AddrModeT1_s {	// AddrMode
  bits<5> Value = { 0, 1, 0, 1, 0 };
  string NAME = ?;
}
def AddrModeT2_i12 {	// AddrMode
  bits<5> Value = { 0, 1, 0, 1, 1 };
  string NAME = ?;
}
def AddrModeT2_i8 {	// AddrMode
  bits<5> Value = { 0, 1, 1, 0, 0 };
  string NAME = ?;
}
def AddrModeT2_i8s4 {	// AddrMode
  bits<5> Value = { 0, 1, 1, 1, 1 };
  string NAME = ?;
}
def AddrModeT2_pc {	// AddrMode
  bits<5> Value = { 0, 1, 1, 1, 0 };
  string NAME = ?;
}
def AddrModeT2_so {	// AddrMode
  bits<5> Value = { 0, 1, 1, 0, 1 };
  string NAME = ?;
}
def AddrMode_i12 {	// AddrMode
  bits<5> Value = { 1, 0, 0, 0, 0 };
  string NAME = ?;
}
def AdrLabelAsmOperand {	// AsmOperandClass
  string Name = "AdrLabel";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Any {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 255;
  string NAME = ?;
}
def ArithMiscFrm {	// Format
  bits<6> Value = { 0, 0, 1, 1, 0, 0 };
  string NAME = ?;
}
def B {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins arm_br_target:$target);
  string AsmString = "";
  list<dag> Pattern = [(br bb:$target)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 1;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (Bcc arm_br_target:$target, (ops 14, zero_reg));
  string NAME = ?;
}
def BCCZi64 {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst);
  string AsmString = "";
  list<dag> Pattern = [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def BCCi64 {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst);
  string AsmString = "";
  list<dag> Pattern = [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def BFC {	// Instruction InstTemplate Encoding InstARM I Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 1, 1, 0, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0}, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$src, bf_inv_mask_imm:$imm, pred:$p);
  string AsmString = "bfc${p}	$Rd, $imm";
  list<dag> Pattern = [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAsi;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<10> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BFI {	// Instruction InstTemplate Encoding InstARM I Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 1, 1, 0, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0}, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm, pred:$p);
  string AsmString = "bfi${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAsi;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<10> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BICri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "bic${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, (anonymous_3184 GPR:$Rn, mod_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BICrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "bic${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (anonymous_3184 GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def BICrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "bic${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (anonymous_3184 GPR:$Rn, so_reg_imm:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BICrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "bic${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (anonymous_3184 GPR:$Rn, so_reg_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BKPT {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, val{15}, val{14}, val{13}, val{12}, val{11}, val{10}, val{9}, val{8}, val{7}, val{6}, val{5}, val{4}, 0, 1, 1, 1, val{3}, val{2}, val{1}, val{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_65535:$val);
  string AsmString = "bkpt	$val";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<16> val = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BL {	// Instruction InstTemplate Encoding InstARM XI ABXI Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, func{23}, func{22}, func{21}, func{20}, func{19}, func{18}, func{17}, func{16}, func{15}, func{14}, func{13}, func{12}, func{11}, func{10}, func{9}, func{8}, func{7}, func{6}, func{5}, func{4}, func{3}, func{2}, func{1}, func{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins arm_bl_target:$func);
  string AsmString = "bl	$func";
  list<dag> Pattern = [(ARMcall tglobaladdr:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeBranchImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<24> func = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BLX {	// Instruction InstTemplate Encoding InstARM XI AXI Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, func{3}, func{2}, func{1}, func{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$func);
  string AsmString = "blx	$func";
  list<dag> Pattern = [(ARMcall GPR:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsARM, HasV5T];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrMiscFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> func = { ?, ?, ?, ? };
  string NAME = ?;
}
def BLX_pred {	// Instruction InstTemplate Encoding InstARM I AI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, func{3}, func{2}, func{1}, func{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$func, pred:$p);
  string AsmString = "blx${p}	$func";
  list<dag> Pattern = [(ARMcall_pred GPR:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsARM, HasV5T];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrMiscFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> func = { ?, ?, ?, ? };
  string NAME = ?;
}
def BLXi {	// Instruction InstTemplate Encoding InstARM XI AXI Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, target{0}, target{24}, target{23}, target{22}, target{21}, target{20}, target{19}, target{18}, target{17}, target{16}, target{15}, target{14}, target{13}, target{12}, target{11}, target{10}, target{9}, target{8}, target{7}, target{6}, target{5}, target{4}, target{3}, target{2}, target{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins arm_blx_target:$target);
  string AsmString = "blx	$target";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5T];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrMiscFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<25> target = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BL_pred {	// Instruction InstTemplate Encoding InstARM I ABI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 1, 1, func{23}, func{22}, func{21}, func{20}, func{19}, func{18}, func{17}, func{16}, func{15}, func{14}, func{13}, func{12}, func{11}, func{10}, func{9}, func{8}, func{7}, func{6}, func{5}, func{4}, func{3}, func{2}, func{1}, func{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins arm_bl_target:$func, pred:$p);
  string AsmString = "bl${p}	$func";
  list<dag> Pattern = [(ARMcall_pred tglobaladdr:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeBranchImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<24> func = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BMOVPCB_CALL {	// Instruction InstTemplate PseudoInst ARMPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins arm_bl_target:$func);
  string AsmString = "";
  list<dag> Pattern = [(ARMcall_nolink tglobaladdr:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsARM];
  int Size = 8;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def BMOVPCRX_CALL {	// Instruction InstTemplate PseudoInst ARMPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$func);
  string AsmString = "";
  list<dag> Pattern = [(ARMcall_nolink tGPR:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsARM, NoV4T];
  int Size = 8;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def BR_JTadd {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$target, GPR:$idx, i32imm:$jt);
  string AsmString = "";
  list<dag> Pattern = [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrTbl];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def BR_JTm_i12 {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode_imm12:$target, i32imm:$jt);
  string AsmString = "";
  list<dag> Pattern = [(ARMbrjt (i32 (load addrmode_imm12:$target)), tjumptable:$jt)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrTbl];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def BR_JTm_rs {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins ldst_so_reg:$target, i32imm:$jt);
  string AsmString = "";
  list<dag> Pattern = [(ARMbrjt (i32 (load ldst_so_reg:$target)), tjumptable:$jt)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrTbl];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def BR_JTr {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$target, i32imm:$jt);
  string AsmString = "";
  list<dag> Pattern = [(ARMbrjt GPR:$target, tjumptable:$jt)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def BUNDLE {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins variable_ops);
  string AsmString = "BUNDLE";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def BX {	// Instruction InstTemplate Encoding InstARM XI AXI Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, dst{3}, dst{2}, dst{1}, dst{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$dst);
  string AsmString = "bx	$dst";
  list<dag> Pattern = [(brind GPR:$dst)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV4T];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrMiscFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> dst = { ?, ?, ?, ? };
  string NAME = ?;
}
def BXJ {	// Instruction InstTemplate Encoding InstARM I ABI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, func{3}, func{2}, func{1}, func{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$func, pred:$p);
  string AsmString = "bxj${p}	$func";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> func = { ?, ?, ?, ? };
  string NAME = ?;
}
def BX_CALL {	// Instruction InstTemplate PseudoInst ARMPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$func);
  string AsmString = "";
  list<dag> Pattern = [(ARMcall_nolink tGPR:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsARM, HasV4T];
  int Size = 8;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def BX_RET {	// Instruction InstTemplate Encoding InstARM I AI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "bx${p}	lr";
  list<dag> Pattern = [(ARMretflag)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV4T];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrMiscFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
def BX_pred {	// Instruction InstTemplate Encoding InstARM I AI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, dst{3}, dst{2}, dst{1}, dst{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$dst, pred:$p);
  string AsmString = "bx${p}	$dst";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV4T];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrMiscFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> dst = { ?, ?, ?, ? };
  string NAME = ?;
}
def BankedRegOperand {	// AsmOperandClass
  string Name = "BankedReg";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseBankedRegOperand";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Bcc {	// Instruction InstTemplate Encoding InstARM I ABI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 1, 0, target{23}, target{22}, target{21}, target{20}, target{19}, target{18}, target{17}, target{16}, target{15}, target{14}, target{13}, target{12}, target{11}, target{10}, target{9}, target{8}, target{7}, target{6}, target{5}, target{4}, target{3}, target{2}, target{1}, target{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins arm_br_target:$target, pred:$p);
  string AsmString = "b${p}	$target";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeBranchImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<24> target = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def BitfieldAsmOperand {	// AsmOperandClass
  string Name = "Bitfield";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseBitfield";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def BrFrm {	// Format
  bits<6> Value = { 0, 0, 0, 0, 1, 0 };
  string NAME = ?;
}
def BrMiscFrm {	// Format
  bits<6> Value = { 0, 0, 0, 0, 1, 1 };
  string NAME = ?;
}
def CCOutOperand {	// AsmOperandClass
  string Name = "CCOut";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def CCR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = -1;
  dag MemberList = (add CPSR);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 0;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def CC_ARM_AAPCS {	// CallingConv
  list<CCAction> Actions = [anonymous_3015, anonymous_3085, anonymous_3086, anonymous_3087, anonymous_3020, anonymous_3023, anonymous_3089, anonymous_3031, anonymous_3090];
  bit Custom = 0;
  string NAME = ?;
}
def CC_ARM_AAPCS_Common {	// CallingConv
  list<CCAction> Actions = [anonymous_3017, anonymous_3069, anonymous_3071, anonymous_3074, anonymous_3076, anonymous_3051, anonymous_3078, anonymous_3081, anonymous_3083];
  bit Custom = 0;
  string NAME = ?;
}
def CC_ARM_AAPCS_VFP {	// CallingConv
  list<CCAction> Actions = [anonymous_3015, anonymous_3086, anonymous_3087, anonymous_3020, anonymous_3023, anonymous_3095, anonymous_3045, anonymous_3047, anonymous_3049, anonymous_3090];
  bit Custom = 0;
  string NAME = ?;
}
def CC_ARM_APCS {	// CallingConv
  list<CCAction> Actions = [anonymous_3015, anonymous_3017, anonymous_3020, anonymous_3023, anonymous_3025, anonymous_3027, anonymous_3029, anonymous_3031, anonymous_3033, anonymous_3035, anonymous_3037, anonymous_3039];
  bit Custom = 0;
  string NAME = ?;
}
def CC_ARM_APCS_GHC {	// CallingConv
  list<CCAction> Actions = [anonymous_3025, anonymous_3027, anonymous_3059, anonymous_3061, anonymous_3063, anonymous_3064, anonymous_3066];
  bit Custom = 0;
  string NAME = ?;
}
def CDP {	// Instruction InstTemplate Encoding InstARM I ABI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRn{3}, CRn{2}, CRn{1}, CRn{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 0, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2, pred:$p);
  string AsmString = "cdp${p}	$cop, $opc1, $CRd, $CRn, $CRm, $opc2";
  list<dag> Pattern = [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CDP2 {	// Instruction InstTemplate Encoding InstARM XI ABXI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRn{3}, CRn{2}, CRn{1}, CRn{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 0, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2);
  string AsmString = "cdp2	$cop, $opc1, $CRd, $CRn, $CRm, $opc2";
  list<dag> Pattern = [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CFI_INSTRUCTION {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$id);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 1;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def CLREX {	// Instruction InstTemplate Encoding InstARM XI AXI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "clrex";
  list<dag> Pattern = [(int_arm_clrex)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6K];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def CLZ {	// Instruction InstTemplate Encoding InstARM I AMiscA1I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rm, pred:$p);
  string AsmString = "clz${p}	$Rd, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (ctlz GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5T];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ArithMiscFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CMNri {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p);
  string AsmString = "cmn${p}	$Rn, $imm";
  list<dag> Pattern = [(ARMcmn GPR:$Rn, mod_imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPi;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def CMNzrr {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "cmn${p}	$Rn, $Rm";
  list<dag> Pattern = [(anonymous_3214 GPR:$Rn, GPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPr;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CMNzrsi {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p);
  string AsmString = "cmn${p}	$Rn, $shift";
  list<dag> Pattern = [(anonymous_3214 GPR:$Rn, so_reg_imm:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPsr;
  list<SchedReadWrite> SchedRW = [WriteCMPsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def CMNzrsr {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p);
  string AsmString = "cmn${p}	$Rn, $shift";
  list<dag> Pattern = [(anonymous_3214 GPRnopc:$Rn, so_reg_reg:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPsr;
  list<SchedReadWrite> SchedRW = [WriteCMPsr, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def CMP_SWAP_16 {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd, GPR:$temp);
  dag InOperandList = (ins GPR:$addr, GPR:$desired, GPR:$new);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [];
  string Constraints = "@earlyclobber $Rd,@earlyclobber $temp";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def CMP_SWAP_32 {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd, GPR:$temp);
  dag InOperandList = (ins GPR:$addr, GPR:$desired, GPR:$new);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [];
  string Constraints = "@earlyclobber $Rd,@earlyclobber $temp";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def CMP_SWAP_64 {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRPair:$Rd, GPR:$temp);
  dag InOperandList = (ins GPR:$addr, GPRPair:$desired, GPRPair:$new);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [];
  string Constraints = "@earlyclobber $Rd,@earlyclobber $temp";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def CMP_SWAP_8 {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd, GPR:$temp);
  dag InOperandList = (ins GPR:$addr, GPR:$desired, GPR:$new);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [];
  string Constraints = "@earlyclobber $Rd,@earlyclobber $temp";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def CMPri {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p);
  string AsmString = "cmp${p}	$Rn, $imm";
  list<dag> Pattern = [(ARMcmp GPR:$Rn, mod_imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPi;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def CMPrr {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "cmp${p}	$Rn, $Rm";
  list<dag> Pattern = [(ARMcmp GPR:$Rn, GPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPr;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CMPrsi {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p);
  string AsmString = "cmp${p}	$Rn, $shift";
  list<dag> Pattern = [(ARMcmp GPR:$Rn, so_reg_imm:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPsr;
  list<SchedReadWrite> SchedRW = [WriteCMPsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def CMPrsr {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p);
  string AsmString = "cmp${p}	$Rn, $shift";
  list<dag> Pattern = [(ARMcmp GPRnopc:$Rn, so_reg_reg:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPsr;
  list<SchedReadWrite> SchedRW = [WriteCMPsr, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def CONSTPOOL_ENTRY {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def COPY {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins unknown:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def COPY_STRUCT_BYVAL_I32 {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment);
  string AsmString = "";
  list<dag> Pattern = [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def COPY_TO_REGCLASS {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins unknown:$src, i32imm:$regclass);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def CPS1p {	// Instruction InstTemplate Encoding InstARM XI AXI Requires CPS
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "cps	$mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCPSInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<2> imod = { 0, 0 };
  bits<3> iflags = { 0, 0, 0 };
  bits<5> mode = { ?, ?, ?, ?, ? };
  bit M = 1;
  string NAME = ?;
}
def CPS2p {	// Instruction InstTemplate Encoding InstARM XI AXI Requires CPS
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, imod{1}, imod{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, iflags{2}, iflags{1}, iflags{0}, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imod_op:$imod, iflags_op:$iflags);
  string AsmString = "cps$imod	$iflags";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCPSInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<2> imod = { ?, ? };
  bits<3> iflags = { ?, ?, ? };
  bits<5> mode = { 0, 0, 0, 0, 0 };
  bit M = 0;
  string NAME = ?;
}
def CPS3p {	// Instruction InstTemplate Encoding InstARM XI AXI Requires CPS
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, imod{1}, imod{0}, 1, 0, 0, 0, 0, 0, 0, 0, 0, iflags{2}, iflags{1}, iflags{0}, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode);
  string AsmString = "cps$imod	$iflags, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCPSInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<2> imod = { ?, ? };
  bits<3> iflags = { ?, ?, ? };
  bits<5> mode = { ?, ?, ?, ?, ? };
  bit M = 1;
  string NAME = ?;
}
def CPSR {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "cpsr";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def CRC32B {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires AI_crc32
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm);
  string AsmString = "crc32b	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_crc32b GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CRC32CB {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires AI_crc32
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm);
  string AsmString = "crc32cb	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_crc32cb GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CRC32CH {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires AI_crc32
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm);
  string AsmString = "crc32ch	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_crc32ch GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CRC32CW {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires AI_crc32
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm);
  string AsmString = "crc32cw	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_crc32cw GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CRC32H {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires AI_crc32
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm);
  string AsmString = "crc32h	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_crc32h GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CRC32W {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires AI_crc32
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm);
  string AsmString = "crc32w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_crc32w GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def CSR_AAPCS {	// CalleeSavedRegs
  dag SaveList = (add LR, R11, R10, R9, R8, R7, R6, R5, R4, (sequence "D%u", 15, 8));
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_AAPCS_SplitPush {	// CalleeSavedRegs
  dag SaveList = (add LR, R7, R6, R5, R4, R11, R10, R9, R8, (sequence "D%u", 15, 8));
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_AAPCS_SplitPush_SwiftError {	// CalleeSavedRegs
  dag SaveList = (sub CSR_AAPCS_SplitPush, R8);
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_AAPCS_SwiftError {	// CalleeSavedRegs
  dag SaveList = (sub CSR_AAPCS, R8);
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_AAPCS_ThisReturn {	// CalleeSavedRegs
  dag SaveList = (add LR, R11, R10, R9, R8, R7, R6, R5, R4, (sequence "D%u", 15, 8), R0);
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_FIQ {	// CalleeSavedRegs
  dag SaveList = (add LR, R11, (sequence "R%u", 7, 0));
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_FPRegs {	// CalleeSavedRegs
  dag SaveList = (add (sequence "D%u", 0, 31));
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_GenericInt {	// CalleeSavedRegs
  dag SaveList = (add LR, (sequence "R%u", 12, 0));
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_NoRegs {	// CalleeSavedRegs
  dag SaveList = (add);
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_iOS {	// CalleeSavedRegs
  dag SaveList = (add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9));
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_iOS_CXX_TLS {	// CalleeSavedRegs
  dag SaveList = (add CSR_iOS, (sequence "R%u", 12, 1), (sequence "D%u", 31, 0));
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_iOS_CXX_TLS_PE {	// CalleeSavedRegs
  dag SaveList = (add LR, R12, R11, R7, R5, R4);
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_iOS_CXX_TLS_ViaCopy {	// CalleeSavedRegs
  dag SaveList = (sub CSR_iOS_CXX_TLS, CSR_iOS_CXX_TLS_PE);
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_iOS_SwiftError {	// CalleeSavedRegs
  dag SaveList = (sub CSR_iOS, R8);
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_iOS_TLSCall {	// CalleeSavedRegs
  dag SaveList = (add LR, SP, (sub (sequence "R%u", 12, 1), R9, R12), (sequence "D%u", 31, 0));
  dag OtherPreserved = ?;
  string NAME = ?;
}
def CSR_iOS_ThisReturn {	// CalleeSavedRegs
  dag SaveList = (add LR, R7, R6, R5, R4, (sub CSR_AAPCS_ThisReturn, R9));
  dag OtherPreserved = ?;
  string NAME = ?;
}
def Commutative {	// IntrinsicProperty
  string NAME = ?;
}
def CompilerBarrier {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$ordering);
  string AsmString = "@ COMPILER BARRIER";
  list<dag> Pattern = [(atomic_fence imm:$ordering, 0)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def CondCodeOperand {	// AsmOperandClass
  string Name = "CondCode";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def CoprocNumAsmOperand {	// AsmOperandClass
  string Name = "CoprocNum";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseCoprocNumOperand";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def CoprocOptionAsmOperand {	// AsmOperandClass
  string Name = "CoprocOption";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseCoprocOptionOperand";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def CoprocRegAsmOperand {	// AsmOperandClass
  string Name = "CoprocReg";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseCoprocRegOperand";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def CortexA57Model {	// SchedMachineModel
  int IssueWidth = 3;
  int MicroOpBufferSize = 128;
  int LoopMicroOpBufferSize = 16;
  int LoadLatency = 4;
  int HighLatency = -1;
  int MispredictPenalty = 16;
  ProcessorItineraries Itineraries = NoItineraries;
  bit PostRAScheduler = 0;
  bit CompleteModel = 1;
  bit FullInstRWOverlapCheck = 0;
  list<Predicate> UnsupportedFeatures = [];
  bit NoModel = 0;
  string NAME = ?;
}
def CortexA8Itineraries {	// ProcessorItineraries
  list<FuncUnit> FU = [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe];
  list<Bypass> BP = [];
  list<InstrItinData> IID = [anonymous_1063, anonymous_1064, anonymous_1065, anonymous_1066, anonymous_1067, anonymous_1068, anonymous_1069, anonymous_1070, anonymous_1071, anonymous_1072, anonymous_1073, anonymous_1074, anonymous_1075, anonymous_1076, anonymous_1077, anonymous_1078, anonymous_1079, anonymous_1080, anonymous_1081, anonymous_1082, anonymous_1083, anonymous_1084, anonymous_1085, anonymous_1086, anonymous_1087, anonymous_1088, anonymous_1089, anonymous_1090, anonymous_1091, anonymous_1093, anonymous_1094, anonymous_1095, anonymous_1096, anonymous_1097, anonymous_1098, anonymous_1099, anonymous_1100, anonymous_1101, anonymous_1102, anonymous_1104, anonymous_1106, anonymous_1107, anonymous_1108, anonymous_1110, anonymous_1111, anonymous_1113, anonymous_1114, anonymous_1115, anonymous_1116, anonymous_1117, anonymous_1118, anonymous_1120, anonymous_1121, anonymous_1122, anonymous_1123, anonymous_1124, anonymous_1125, anonymous_1126, anonymous_1128, anonymous_1129, anonymous_1131, anonymous_1134, anonymous_1135, anonymous_1136, anonymous_1137, anonymous_1138, anonymous_1139, anonymous_1140, anonymous_1141, anonymous_1142, anonymous_1143, anonymous_1144, anonymous_1145, anonymous_1146, anonymous_1147, anonymous_1148, anonymous_1149, anonymous_1150, anonymous_1151, anonymous_1152, anonymous_1153, anonymous_1154, anonymous_1155, anonymous_1156, anonymous_1157, anonymous_1159, anonymous_1161, anonymous_1164, anonymous_1165, anonymous_1166, anonymous_1169, anonymous_1172, anonymous_1173, anonymous_1176, anonymous_1177, anonymous_1178, anonymous_1179, anonymous_1182, anonymous_1183, anonymous_1186, anonymous_1187, anonymous_1190, anonymous_1191, anonymous_1192, anonymous_1195, anonymous_1198, anonymous_1199, anonymous_1200, anonymous_1201, anonymous_1202, anonymous_1203, anonymous_1204, anonymous_1206, anonymous_1207, anonymous_1208, anonymous_1209, anonymous_1210, anonymous_1211, anonymous_1212, anonymous_1213, anonymous_1215, anonymous_1216, anonymous_1218, anonymous_1219, anonymous_1220, anonymous_1221, anonymous_1222, anonymous_1223, anonymous_1224, anonymous_1225, anonymous_1226, anonymous_1227, anonymous_1228, anonymous_1229, anonymous_1230, anonymous_1231, anonymous_1232, anonymous_1233, anonymous_1234, anonymous_1235, anonymous_1238, anonymous_1241, anonymous_1242, anonymous_1243, anonymous_1244, anonymous_1245, anonymous_1246, anonymous_1247, anonymous_1248, anonymous_1249, anonymous_1250, anonymous_1251, anonymous_1252, anonymous_1253, anonymous_1254, anonymous_1255, anonymous_1256, anonymous_1257, anonymous_1258, anonymous_1259, anonymous_1260, anonymous_1261, anonymous_1262, anonymous_1263, anonymous_1264, anonymous_1265, anonymous_1266, anonymous_1267, anonymous_1268, anonymous_1269, anonymous_1270, anonymous_1271, anonymous_1272, anonymous_1273, anonymous_1274, anonymous_1275, anonymous_1276, anonymous_1278, anonymous_1279, anonymous_1280, anonymous_1281, anonymous_1282, anonymous_1283, anonymous_1284, anonymous_1285, anonymous_1286, anonymous_1288, anonymous_1289, anonymous_1290, anonymous_1291, anonymous_1292, anonymous_1293, anonymous_1294, anonymous_1295, anonymous_1296, anonymous_1298, anonymous_1299, anonymous_1300, anonymous_1301, anonymous_1302, anonymous_1303, anonymous_1304, anonymous_1305, anonymous_1306, anonymous_1307, anonymous_1308, anonymous_1309, anonymous_1310, anonymous_1311, anonymous_1312, anonymous_1313, anonymous_1314, anonymous_1315, anonymous_1316, anonymous_1317, anonymous_1318, anonymous_1319, anonymous_1320, anonymous_1321, anonymous_1322, anonymous_1323, anonymous_1324, anonymous_1325, anonymous_1326, anonymous_1327, anonymous_1328, anonymous_1329, anonymous_1331, anonymous_1332, anonymous_1333, anonymous_1334, anonymous_1335, anonymous_1336, anonymous_1337, anonymous_1338, anonymous_1339, anonymous_1340, anonymous_1341, anonymous_1342, anonymous_1343, anonymous_1344, anonymous_1345];
  string NAME = ?;
}
def CortexA8Model {	// SchedMachineModel
  int IssueWidth = 2;
  int MicroOpBufferSize = -1;
  int LoopMicroOpBufferSize = -1;
  int LoadLatency = 2;
  int HighLatency = -1;
  int MispredictPenalty = 13;
  ProcessorItineraries Itineraries = CortexA8Itineraries;
  bit PostRAScheduler = 0;
  bit CompleteModel = 0;
  bit FullInstRWOverlapCheck = 1;
  list<Predicate> UnsupportedFeatures = [];
  bit NoModel = 0;
  string NAME = ?;
}
def CortexA9Itineraries {	// ProcessorItineraries
  list<FuncUnit> FU = [A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0, A9_LSUnit, A9_DRegsVFP, A9_DRegsN];
  list<Bypass> BP = [A9_LdBypass];
  list<InstrItinData> IID = [anonymous_1348, anonymous_1349, anonymous_1350, anonymous_1352, anonymous_1353, anonymous_1354, anonymous_1358, anonymous_1359, anonymous_1360, anonymous_1361, anonymous_1363, anonymous_1364, anonymous_1365, anonymous_1366, anonymous_1367, anonymous_1368, anonymous_1369, anonymous_1370, anonymous_1371, anonymous_1372, anonymous_1373, anonymous_1374, anonymous_1375, anonymous_1376, anonymous_1377, anonymous_1378, anonymous_1379, anonymous_1380, anonymous_1381, anonymous_1382, anonymous_1383, anonymous_1384, anonymous_1385, anonymous_1386, anonymous_1387, anonymous_1388, anonymous_1389, anonymous_1390, anonymous_1391, anonymous_1393, anonymous_1394, anonymous_1395, anonymous_1396, anonymous_1398, anonymous_1399, anonymous_1400, anonymous_1402, anonymous_1403, anonymous_1404, anonymous_1405, anonymous_1406, anonymous_1408, anonymous_1409, anonymous_1410, anonymous_1411, anonymous_1412, anonymous_1413, anonymous_1414, anonymous_1415, anonymous_1416, anonymous_1419, anonymous_1420, anonymous_1423, anonymous_1424, anonymous_1425, anonymous_1426, anonymous_1427, anonymous_1428, anonymous_1429, anonymous_1430, anonymous_1431, anonymous_1432, anonymous_1433, anonymous_1434, anonymous_1435, anonymous_1436, anonymous_1437, anonymous_1438, anonymous_1439, anonymous_1440, anonymous_1441, anonymous_1442, anonymous_1443, anonymous_1445, anonymous_1448, anonymous_1452, anonymous_1454, anonymous_1455, anonymous_1457, anonymous_1458, anonymous_1459, anonymous_1460, anonymous_1461, anonymous_1462, anonymous_1463, anonymous_1464, anonymous_1465, anonymous_1466, anonymous_1467, anonymous_1468, anonymous_1470, anonymous_1473, anonymous_1475, anonymous_1477, anonymous_1478, anonymous_1479, anonymous_1482, anonymous_1485, anonymous_1488, anonymous_1491, anonymous_1492, anonymous_1493, anonymous_1494, anonymous_1495, anonymous_1497, anonymous_1498, anonymous_1499, anonymous_1500, anonymous_1501, anonymous_1502, anonymous_1503, anonymous_1504, anonymous_1507, anonymous_1508, anonymous_1511, anonymous_1512, anonymous_1513, anonymous_1514, anonymous_1515, anonymous_1516, anonymous_1517, anonymous_1518, anonymous_1519, anonymous_1520, anonymous_1521, anonymous_1522, anonymous_1523, anonymous_1524, anonymous_1525, anonymous_1526, anonymous_1527, anonymous_1528, anonymous_1532, anonymous_1536, anonymous_1537, anonymous_1538, anonymous_1539, anonymous_1540, anonymous_1541, anonymous_1545, anonymous_1546, anonymous_1547, anonymous_1548, anonymous_1549, anonymous_1551, anonymous_1552, anonymous_1554, anonymous_1555, anonymous_1556, anonymous_1557, anonymous_1558, anonymous_1559, anonymous_1560, anonymous_1561, anonymous_1562, anonymous_1564, anonymous_1565, anonymous_1566, anonymous_1567, anonymous_1568, anonymous_1569, anonymous_1570, anonymous_1571, anonymous_1572, anonymous_1573, anonymous_1574, anonymous_1575, anonymous_1576, anonymous_1577, anonymous_1578, anonymous_1579, anonymous_1580, anonymous_1581, anonymous_1582, anonymous_1583, anonymous_1584, anonymous_1585, anonymous_1586, anonymous_1587, anonymous_1588, anonymous_1589, anonymous_1590, anonymous_1591, anonymous_1592, anonymous_1593, anonymous_1594, anonymous_1595, anonymous_1596, anonymous_1597, anonymous_1598, anonymous_1599, anonymous_1600, anonymous_1601, anonymous_1603, anonymous_1604, anonymous_1605, anonymous_1606, anonymous_1607, anonymous_1608, anonymous_1609, anonymous_1610, anonymous_1611, anonymous_1612, anonymous_1613, anonymous_1614, anonymous_1615, anonymous_1617, anonymous_1618, anonymous_1619, anonymous_1620, anonymous_1621, anonymous_1622, anonymous_1623, anonymous_1624, anonymous_1625, anonymous_1626, anonymous_1627, anonymous_1628, anonymous_1629, anonymous_1630, anonymous_1632, anonymous_1633, anonymous_1634, anonymous_1636, anonymous_1637, anonymous_1638, anonymous_1639, anonymous_1641, anonymous_1642, anonymous_1643, anonymous_1644, anonymous_1645, anonymous_1646, anonymous_1647];
  string NAME = ?;
}
def CortexA9Model {	// SchedMachineModel
  int IssueWidth = 2;
  int MicroOpBufferSize = 56;
  int LoopMicroOpBufferSize = -1;
  int LoadLatency = 2;
  int HighLatency = -1;
  int MispredictPenalty = 8;
  ProcessorItineraries Itineraries = CortexA9Itineraries;
  bit PostRAScheduler = 0;
  bit CompleteModel = 0;
  bit FullInstRWOverlapCheck = 0;
  list<Predicate> UnsupportedFeatures = [];
  bit NoModel = 0;
  string NAME = ?;
}
def CortexM3Model {	// SchedMachineModel
  int IssueWidth = 1;
  int MicroOpBufferSize = 0;
  int LoopMicroOpBufferSize = -1;
  int LoadLatency = 2;
  int HighLatency = -1;
  int MispredictPenalty = 2;
  ProcessorItineraries Itineraries = NoItineraries;
  bit PostRAScheduler = 0;
  bit CompleteModel = 0;
  bit FullInstRWOverlapCheck = 1;
  list<Predicate> UnsupportedFeatures = [];
  bit NoModel = 0;
  string NAME = ?;
}
def CortexR52Model {	// SchedMachineModel
  int IssueWidth = 2;
  int MicroOpBufferSize = 0;
  int LoopMicroOpBufferSize = -1;
  int LoadLatency = 1;
  int HighLatency = -1;
  int MispredictPenalty = 8;
  ProcessorItineraries Itineraries = NoItineraries;
  bit PostRAScheduler = 0;
  bit CompleteModel = 0;
  bit FullInstRWOverlapCheck = 1;
  list<Predicate> UnsupportedFeatures = [];
  bit NoModel = 0;
  string NAME = ?;
}
def D0 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d0";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S0, S1];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [256];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D1 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d1";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S2, S3];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [257];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D10 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d10";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S20, S21];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [266];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D11 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d11";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S22, S23];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [267];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D12 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d12";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S24, S25];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [268];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D13 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d13";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S26, S27];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [269];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D14 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d14";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S28, S29];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [270];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D15 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d15";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S30, S31];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [271];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D16 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d16";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [272];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D17 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d17";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [273];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D18 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d18";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [274];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D19 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d19";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [275];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D2 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d2";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S4, S5];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [258];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D20 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d20";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [276];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D21 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d21";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [277];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D22 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d22";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [278];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D23 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d23";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [279];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D24 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d24";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [280];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D25 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d25";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [281];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D26 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d26";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [282];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D27 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d27";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [283];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D28 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d28";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [284];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D29 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d29";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [285];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D3 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d3";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S6, S7];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [259];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D30 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d30";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [286];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D31 {	// Register ARMFReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d31";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [287];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D4 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d4";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S8, S9];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [260];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D5 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d5";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S10, S11];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [261];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D6 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d6";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S12, S13];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [262];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D7 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d7";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S14, S15];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [263];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D8 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d8";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S16, S17];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [264];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def D9 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "d9";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [S18, S19];
  list<SubRegIndex> SubRegIndices = [ssub_0, ssub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [265];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def DBG {	// Instruction InstTemplate Encoding InstARM I AI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, opt{3}, opt{2}, opt{1}, opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_15:$opt, pred:$p);
  string AsmString = "dbg${p}	$opt";
  list<dag> Pattern = [(int_arm_dbg imm0_15:$opt)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV7];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def DBG_LABEL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins unknown:$label);
  string AsmString = "DBG_LABEL";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def DBG_VALUE {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins variable_ops);
  string AsmString = "DBG_VALUE";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def DMB {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, opt{3}, opt{2}, opt{1}, opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins memb_opt:$opt);
  string AsmString = "dmb	$opt";
  list<dag> Pattern = [(int_arm_dmb (i32 imm0_15:$opt))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasDB];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def DPFrm {	// Format
  bits<6> Value = { 0, 0, 0, 1, 0, 0 };
  string NAME = ?;
}
def DPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16];
  int Size = 0;
  int Alignment = 64;
  int CopyCost = 1;
  dag MemberList = (sequence "D%u", 0, 31);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(rotl DPR, 16), (add (decimate (rotl DPR, 16), 2), (rotl DPR, 16))];
  code AltOrderSelect = [{
    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
  }];
  int AllocationPriority = 0;
  string DiagnosticType = "DPR";
  string DiagnosticString = "";
  string NAME = ?;
}
def DPRRegListAsmOperand {	// AsmOperandClass
  string Name = "DPRRegList";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "DPR_RegList";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def DPR_8 {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16];
  int Size = 0;
  int Alignment = 64;
  int CopyCost = 1;
  dag MemberList = (trunc DPR, 8);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [d0, d7]";
  string NAME = ?;
}
def DPR_VFP2 {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16];
  int Size = 0;
  int Alignment = 64;
  int CopyCost = 1;
  dag MemberList = (trunc DPR, 16);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [d0, d15]";
  string NAME = ?;
}
def DPSoRegImmFrm {	// Format
  bits<6> Value = { 1, 0, 1, 0, 1, 0 };
  string NAME = ?;
}
def DPSoRegRegFrm {	// Format
  bits<6> Value = { 0, 0, 0, 1, 0, 1 };
  string NAME = ?;
}
def DPair {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64];
  int Size = 0;
  int Alignment = 128;
  int CopyCost = 1;
  dag MemberList = (interleave QPR, TuplesOE2D);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
  code AltOrderSelect = [{ return 1; }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def DPairSpc {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [v2i64];
  int Size = 0;
  int Alignment = 64;
  int CopyCost = 1;
  dag MemberList = (add Tuples2DSpc);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def DQuad {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [v4i64];
  int Size = 0;
  int Alignment = 256;
  int CopyCost = 1;
  dag MemberList = (interleave Tuples2Q, TuplesOE4D);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def DQuadSpc {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [v4i64];
  int Size = 0;
  int Alignment = 64;
  int CopyCost = 1;
  dag MemberList = (add Tuples3DSpc);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def DSB {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, opt{3}, opt{2}, opt{1}, opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins memb_opt:$opt);
  string AsmString = "dsb	$opt";
  list<dag> Pattern = [(int_arm_dsb (i32 imm0_15:$opt))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasDB];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def DSubReg_f64_reg {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
  return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def DSubReg_i16_reg {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
  return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def DSubReg_i32_reg {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
  return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def DSubReg_i8_reg {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
  return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def DTriple {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [untyped];
  int Size = 192;
  int Alignment = 64;
  int CopyCost = 1;
  dag MemberList = (add Tuples3D);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def DTripleSpc {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [untyped];
  int Size = 192;
  int Alignment = 64;
  int CopyCost = 1;
  dag MemberList = (add Tuples3DSpc);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def DefaultAsmParser {	// AsmParser
  string AsmParserClassName = "AsmParser";
  string AsmParserInstCleanup = "";
  bit ShouldEmitMatchRegisterName = 1;
  bit ShouldEmitMatchRegisterAltName = 0;
  bit AllowDuplicateRegisterNames = 0;
  bit HasMnemonicFirst = 1;
  bit ReportMultipleNearMisses = 0;
  string NAME = ?;
}
def DefaultAsmParserVariant {	// AsmParserVariant
  int Variant = 0;
  string Name = "";
  string CommentDelimiter = "";
  string RegisterPrefix = "";
  string TokenizingCharacters = "[]*!";
  string SeparatorCharacters = " 	,";
  string BreakCharacters = "";
  string NAME = ?;
}
def DefaultAsmWriter {	// AsmWriter
  string AsmWriterClassName = "InstPrinter";
  int PassSubtarget = 0;
  int Variant = 0;
  string NAME = ?;
}
def DefaultMode {	// HwMode
  string Features = "";
  string NAME = ?;
}
def DontUseFusedMAC {	// Predicate
  string CondString = "!(TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->hasVFP4()) || Subtarget->isTargetDarwin()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def DontUseMovt {	// Predicate
  string CondString = "!Subtarget->useMovt(*MF)";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 1;
  string NAME = ?;
}
def DontUseMovtInPic {	// Predicate
  string CondString = "!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 1;
  string NAME = ?;
}
def DontUseNEONForFP {	// Predicate
  string CondString = "!Subtarget->useNEONForSinglePrecisionFP()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def DontUseNaClTrap {	// Predicate
  string CondString = "!Subtarget->useNaClTrap()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def DontUseVMOVSR {	// Predicate
  string CondString = "!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def EH_LABEL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$id);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 1;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def EORri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 0, 0, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "eor${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, (xor GPR:$Rn, mod_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def EORrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "eor${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (xor GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def EORrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "eor${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (xor GPR:$Rn, so_reg_imm:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def EORrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "eor${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (xor GPR:$Rn, so_reg_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ERET {	// Instruction InstTemplate Encoding InstARM I ABI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "eret${p}";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [PC];
  list<Predicate> Predicates = [IsARM, HasVirtualization];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
def EXTRACT_SUBREG {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def EponymousProcResourceKind {	// ProcResourceKind
  string NAME = ?;
}
def ExceptRef {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 113;
  string NAME = ?;
}
def ExtFrm {	// Format
  bits<6> Value = { 0, 0, 1, 1, 1, 0 };
  string NAME = ?;
}
def FAULTING_OP {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def FCONSTD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, imm{7}, imm{6}, imm{5}, imm{4}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 0, 0, 0, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins vfp_f64imm:$imm, pred:$p);
  string AsmString = "vmov${p}.f64	$Dd, $imm";
  list<dag> Pattern = [(set DPR:$Dd, vfp_f64imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP3, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<8> imm = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def FCONSTH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, imm{7}, imm{6}, imm{5}, imm{4}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 0, 0, 0, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins vfp_f16imm:$imm, pred:$p);
  string AsmString = "vmov${p}.f16	$Sd, $imm";
  list<dag> Pattern = [(set HPR:$Sd, vfp_f16imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<8> imm = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def FCONSTS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, imm{7}, imm{6}, imm{5}, imm{4}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 0, 0, 0, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins vfp_f32imm:$imm, pred:$p);
  string AsmString = "vmov${p}.f32	$Sd, $imm";
  list<dag> Pattern = [(set SPR:$Sd, vfp_f32imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP3];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<8> imm = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def FENTRY_CALL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins variable_ops);
  string AsmString = "# FEntry call";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def FLDMXDB_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "fldmdbx${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def FLDMXIA {	// Instruction InstTemplate Encoding InstARM VFPXI AXXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "fldmiax${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def FLDMXIA_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "fldmiax${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def FMSTAT {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovFromVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "vmrs${p}	APSR_nzcv, fpscr";
  list<dag> Pattern = [(arm_fmstat)];
  list<Register> Uses = [FPSCR_NZCV];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { 1, 1, 1, 1 };
  string NAME = ?;
}
def FPEXC {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "fpexc";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def FPINST {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "fpinst";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def FPINST2 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "fpinst2";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def FPImmOperand {	// AsmOperandClass
  string Name = "FPImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseFPImm";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def FPRRegBank {	// RegisterBank
  string Name = "FPRB";
  list<RegisterClass> RegisterClasses = [SPR, DPR];
  string NAME = ?;
}
def FPSCR {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "fpscr";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def FPSCR_NZCV {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "fpscr_nzcv";
  list<string> AltNames = [];
  list<Register> Aliases = [FPSCR];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def FPSID {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "fpsid";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def FSTMXDB_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "fstmdbx${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def FSTMXIA {	// Instruction InstTemplate Encoding InstARM VFPXI AXXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "fstmiax${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def FSTMXIA_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "fstmiax${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def FastCC_ARM_APCS {	// CallingConv
  list<CCAction> Actions = [anonymous_3025, anonymous_3027, anonymous_3045, anonymous_3047, anonymous_3049, anonymous_3051, anonymous_3053, anonymous_3055, anonymous_3056];
  bit Custom = 0;
  string NAME = ?;
}
def Feature8MSecExt {	// SubtargetFeature
  string Name = "8msecext";
  string Attribute = "Has8MSecExt";
  string Value = "true";
  string Desc = "Enable support for ARMv8-M Security Extensions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureAClass {	// SubtargetFeature
  string Name = "aclass";
  string Attribute = "ARMProcClass";
  string Value = "AClass";
  string Desc = "Is application profile ('A' series)";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureAcquireRelease {	// SubtargetFeature
  string Name = "acquire-release";
  string Attribute = "HasAcquireRelease";
  string Value = "true";
  string Desc = "Has v8 acquire/release (lda/ldaex  etc) instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureAvoidMOVsShOp {	// SubtargetFeature
  string Name = "avoid-movs-shop";
  string Attribute = "AvoidMOVsShifterOperand";
  string Value = "true";
  string Desc = "Avoid movs instructions with shifter operand";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureAvoidPartialCPSR {	// SubtargetFeature
  string Name = "avoid-partial-cpsr";
  string Attribute = "AvoidCPSRPartialUpdate";
  string Value = "true";
  string Desc = "Avoid CPSR partial update for OOO execution";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureCRC {	// SubtargetFeature
  string Name = "crc";
  string Attribute = "HasCRC";
  string Value = "true";
  string Desc = "Enable support for CRC instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureCheapPredicableCPSR {	// SubtargetFeature
  string Name = "cheap-predicable-cpsr";
  string Attribute = "CheapPredicableCPSRDef";
  string Value = "true";
  string Desc = "Disable +1 predication cost for instructions updating CPSR";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureCheckVLDnAlign {	// SubtargetFeature
  string Name = "vldn-align";
  string Attribute = "CheckVLDnAlign";
  string Value = "true";
  string Desc = "Check for VLDn unaligned access";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureCrypto {	// SubtargetFeature
  string Name = "crypto";
  string Attribute = "HasCrypto";
  string Value = "true";
  string Desc = "Enable support for Cryptography extensions";
  list<SubtargetFeature> Implies = [FeatureNEON];
  string NAME = ?;
}
def FeatureD16 {	// SubtargetFeature
  string Name = "d16";
  string Attribute = "HasD16";
  string Value = "true";
  string Desc = "Restrict FP to 16 double registers";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureDB {	// SubtargetFeature
  string Name = "db";
  string Attribute = "HasDataBarrier";
  string Value = "true";
  string Desc = "Has data barrier (dmb/dsb) instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureDFB {	// SubtargetFeature
  string Name = "dfb";
  string Attribute = "HasFullDataBarrier";
  string Value = "true";
  string Desc = "Has full data barrier (dfb) instruction";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureDSP {	// SubtargetFeature
  string Name = "dsp";
  string Attribute = "HasDSP";
  string Value = "true";
  string Desc = "Supports DSP instructions in ARM and/or Thumb2";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureDontWidenVMOVS {	// SubtargetFeature
  string Name = "dont-widen-vmovs";
  string Attribute = "DontWidenVMOVS";
  string Value = "true";
  string Desc = "Don't widen VMOVS to VMOVD";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureDotProd {	// SubtargetFeature
  string Name = "dotprod";
  string Attribute = "HasDotProd";
  string Value = "true";
  string Desc = "Enable support for dot product instructions";
  list<SubtargetFeature> Implies = [FeatureNEON];
  string NAME = ?;
}
def FeatureExecuteOnly {	// SubtargetFeature
  string Name = "execute-only";
  string Attribute = "GenExecuteOnly";
  string Value = "true";
  string Desc = "Enable the generation of execute only code.";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureExpandMLx {	// SubtargetFeature
  string Name = "expand-fp-mlx";
  string Attribute = "ExpandMLx";
  string Value = "true";
  string Desc = "Expand VFP/NEON MLA/MLS instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureFP16 {	// SubtargetFeature
  string Name = "fp16";
  string Attribute = "HasFP16";
  string Value = "true";
  string Desc = "Enable half-precision floating point";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureFPAO {	// SubtargetFeature
  string Name = "fpao";
  string Attribute = "HasFPAO";
  string Value = "true";
  string Desc = "Enable fast computation of positive address offsets";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureFPARMv8 {	// SubtargetFeature
  string Name = "fp-armv8";
  string Attribute = "HasFPARMv8";
  string Value = "true";
  string Desc = "Enable ARMv8 FP";
  list<SubtargetFeature> Implies = [FeatureVFP4];
  string NAME = ?;
}
def FeatureFullFP16 {	// SubtargetFeature
  string Name = "fullfp16";
  string Attribute = "HasFullFP16";
  string Value = "true";
  string Desc = "Enable full half-precision floating point";
  list<SubtargetFeature> Implies = [FeatureFPARMv8];
  string NAME = ?;
}
def FeatureFuseAES {	// SubtargetFeature
  string Name = "fuse-aes";
  string Attribute = "HasFuseAES";
  string Value = "true";
  string Desc = "CPU fuses AES crypto operations";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureHWDivARM {	// SubtargetFeature
  string Name = "hwdiv-arm";
  string Attribute = "HasHardwareDivideInARM";
  string Value = "true";
  string Desc = "Enable divide instructions in ARM mode";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureHWDivThumb {	// SubtargetFeature
  string Name = "hwdiv";
  string Attribute = "HasHardwareDivideInThumb";
  string Value = "true";
  string Desc = "Enable divide instructions in Thumb";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureHasNoBranchPredictor {	// SubtargetFeature
  string Name = "no-branch-predictor";
  string Attribute = "HasBranchPredictor";
  string Value = "false";
  string Desc = "Has no branch predictor";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureHasRetAddrStack {	// SubtargetFeature
  string Name = "ret-addr-stack";
  string Attribute = "HasRetAddrStack";
  string Value = "true";
  string Desc = "Has return address stack";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureHasSlowFPVMLx {	// SubtargetFeature
  string Name = "slowfpvmlx";
  string Attribute = "SlowFPVMLx";
  string Value = "true";
  string Desc = "Disable VFP / NEON MAC instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureHasVMLxHazards {	// SubtargetFeature
  string Name = "vmlx-hazards";
  string Attribute = "HasVMLxHazards";
  string Value = "true";
  string Desc = "Has VMLx hazards";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureLongCalls {	// SubtargetFeature
  string Name = "long-calls";
  string Attribute = "GenLongCalls";
  string Value = "true";
  string Desc = "Generate calls via indirect call instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureMClass {	// SubtargetFeature
  string Name = "mclass";
  string Attribute = "ARMProcClass";
  string Value = "MClass";
  string Desc = "Is microcontroller profile ('M' series)";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureMP {	// SubtargetFeature
  string Name = "mp";
  string Attribute = "HasMPExtension";
  string Value = "true";
  string Desc = "Supports Multiprocessing extension";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureMuxedUnits {	// SubtargetFeature
  string Name = "muxed-units";
  string Attribute = "HasMuxedUnits";
  string Value = "true";
  string Desc = "Has muxed AGU and NEON/FPU";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureNEON {	// SubtargetFeature
  string Name = "neon";
  string Attribute = "HasNEON";
  string Value = "true";
  string Desc = "Enable NEON instructions";
  list<SubtargetFeature> Implies = [FeatureVFP3];
  string NAME = ?;
}
def FeatureNEONForFP {	// SubtargetFeature
  string Name = "neonfp";
  string Attribute = "UseNEONForSinglePrecisionFP";
  string Value = "true";
  string Desc = "Use NEON for single precision FP";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureNEONForFPMovs {	// SubtargetFeature
  string Name = "neon-fpmovs";
  string Attribute = "UseNEONForFPMovs";
  string Value = "true";
  string Desc = "Convert VMOVSR, VMOVRS, VMOVS to NEON";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureNaClTrap {	// SubtargetFeature
  string Name = "nacl-trap";
  string Attribute = "UseNaClTrap";
  string Value = "true";
  string Desc = "NaCl trap";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureNoARM {	// SubtargetFeature
  string Name = "noarm";
  string Attribute = "NoARM";
  string Value = "true";
  string Desc = "Does not support ARM mode execution";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureNoMovt {	// SubtargetFeature
  string Name = "no-movt";
  string Attribute = "NoMovt";
  string Value = "true";
  string Desc = "Don't use movt/movw pairs for 32-bit imms";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureNoNegativeImmediates {	// SubtargetFeature
  string Name = "no-neg-immediates";
  string Attribute = "NegativeImmediates";
  string Value = "false";
  string Desc = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureNoPostRASched {	// SubtargetFeature
  string Name = "disable-postra-scheduler";
  string Attribute = "DisablePostRAScheduler";
  string Value = "true";
  string Desc = "Don't schedule again after register allocation";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureNonpipelinedVFP {	// SubtargetFeature
  string Name = "nonpipelined-vfp";
  string Attribute = "NonpipelinedVFP";
  string Value = "true";
  string Desc = "VFP instructions are not pipelined";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeaturePerfMon {	// SubtargetFeature
  string Name = "perfmon";
  string Attribute = "HasPerfMon";
  string Value = "true";
  string Desc = "Enable support for Performance Monitor extensions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeaturePref32BitThumb {	// SubtargetFeature
  string Name = "32bit";
  string Attribute = "Pref32BitThumb";
  string Value = "true";
  string Desc = "Prefer 32-bit Thumb instrs";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeaturePrefISHSTBarrier {	// SubtargetFeature
  string Name = "prefer-ishst";
  string Attribute = "PreferISHST";
  string Value = "true";
  string Desc = "Prefer ISHST barriers";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeaturePreferVMOVSR {	// SubtargetFeature
  string Name = "prefer-vmovsr";
  string Attribute = "PreferVMOVSR";
  string Value = "true";
  string Desc = "Prefer VMOVSR";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureProfUnpredicate {	// SubtargetFeature
  string Name = "prof-unpr";
  string Attribute = "IsProfitableToUnpredicate";
  string Value = "true";
  string Desc = "Is profitable to unpredicate";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureRAS {	// SubtargetFeature
  string Name = "ras";
  string Attribute = "HasRAS";
  string Value = "true";
  string Desc = "Enable Reliability, Availability and Serviceability extensions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureRClass {	// SubtargetFeature
  string Name = "rclass";
  string Attribute = "ARMProcClass";
  string Value = "RClass";
  string Desc = "Is realtime profile ('R' series)";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureReadTp {	// SubtargetFeature
  string Name = "read-tp-hard";
  string Attribute = "ReadTPHard";
  string Value = "true";
  string Desc = "Reading thread pointer from register";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureReserveR9 {	// SubtargetFeature
  string Name = "reserve-r9";
  string Attribute = "ReserveR9";
  string Value = "true";
  string Desc = "Reserve R9, making it unavailable as GPR";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureSlowFPBrcc {	// SubtargetFeature
  string Name = "slow-fp-brcc";
  string Attribute = "SlowFPBrcc";
  string Value = "true";
  string Desc = "FP compare + branch is slow";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureSlowLoadDSubreg {	// SubtargetFeature
  string Name = "slow-load-D-subreg";
  string Attribute = "SlowLoadDSubregister";
  string Value = "true";
  string Desc = "Loading into D subregs is slow";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureSlowOddRegister {	// SubtargetFeature
  string Name = "slow-odd-reg";
  string Attribute = "SlowOddRegister";
  string Value = "true";
  string Desc = "VLDM/VSTM starting with an odd register is slow";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureSlowVDUP32 {	// SubtargetFeature
  string Name = "slow-vdup32";
  string Attribute = "HasSlowVDUP32";
  string Value = "true";
  string Desc = "Has slow VDUP32 - prefer VMOV";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureSlowVGETLNi32 {	// SubtargetFeature
  string Name = "slow-vgetlni32";
  string Attribute = "HasSlowVGETLNi32";
  string Value = "true";
  string Desc = "Has slow VGETLNi32 - prefer VMOV";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureStrictAlign {	// SubtargetFeature
  string Name = "strict-align";
  string Attribute = "StrictAlign";
  string Value = "true";
  string Desc = "Disallow all unaligned memory access";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureThumb2 {	// SubtargetFeature
  string Name = "thumb2";
  string Attribute = "HasThumb2";
  string Value = "true";
  string Desc = "Enable Thumb2 instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureTrustZone {	// SubtargetFeature
  string Name = "trustzone";
  string Attribute = "HasTrustZone";
  string Value = "true";
  string Desc = "Enable support for TrustZone security extensions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureUseMISched {	// SubtargetFeature
  string Name = "use-misched";
  string Attribute = "UseMISched";
  string Value = "true";
  string Desc = "Use the MachineScheduler";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureV7Clrex {	// SubtargetFeature
  string Name = "v7clrex";
  string Attribute = "HasV7Clrex";
  string Value = "true";
  string Desc = "Has v7 clrex instruction";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureVFP2 {	// SubtargetFeature
  string Name = "vfp2";
  string Attribute = "HasVFPv2";
  string Value = "true";
  string Desc = "Enable VFP2 instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureVFP3 {	// SubtargetFeature
  string Name = "vfp3";
  string Attribute = "HasVFPv3";
  string Value = "true";
  string Desc = "Enable VFP3 instructions";
  list<SubtargetFeature> Implies = [FeatureVFP2];
  string NAME = ?;
}
def FeatureVFP4 {	// SubtargetFeature
  string Name = "vfp4";
  string Attribute = "HasVFPv4";
  string Value = "true";
  string Desc = "Enable VFP4 instructions";
  list<SubtargetFeature> Implies = [FeatureVFP3, FeatureFP16];
  string NAME = ?;
}
def FeatureVFPOnlySP {	// SubtargetFeature
  string Name = "fp-only-sp";
  string Attribute = "FPOnlySP";
  string Value = "true";
  string Desc = "Floating point unit supports single precision only";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureVMLxForwarding {	// SubtargetFeature
  string Name = "vmlx-forwarding";
  string Attribute = "HasVMLxForwarding";
  string Value = "true";
  string Desc = "Has multiplier accumulator forwarding";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FeatureVirtualization {	// SubtargetFeature
  string Name = "virtualization";
  string Attribute = "HasVirtualization";
  string Value = "true";
  string Desc = "Supports Virtualization extension";
  list<SubtargetFeature> Implies = [FeatureHWDivThumb, FeatureHWDivARM];
  string NAME = ?;
}
def FeatureZCZeroing {	// SubtargetFeature
  string Name = "zcz";
  string Attribute = "HasZeroCycleZeroing";
  string Value = "true";
  string Desc = "Has zero-cycle zeroing instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def FlagVT {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 110;
  string NAME = ?;
}
def GC_LABEL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$id);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 1;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def GPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (add (sequence "R%u", 0, 12), SP, LR, PC);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(add LR, GPR), (trunc GPR, 8)];
  code AltOrderSelect = [{
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [r0, r15]";
  string NAME = ?;
}
def GPRPair {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [untyped];
  int Size = 64;
  int Alignment = 64;
  int CopyCost = 1;
  dag MemberList = (add Tuples2R);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def GPRPairOp {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = GPRPair;
  string PrintMethod = "printGPRPairOperand";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = ?;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def GPRRegBank {	// RegisterBank
  string Name = "GPRB";
  list<RegisterClass> RegisterClasses = [GPR, GPRwithAPSR];
  string NAME = ?;
}
def GPRnopc {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (sub GPR, PC);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
  code AltOrderSelect = [{
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [r0, r14]";
  string NAME = ?;
}
def GPRsp {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (add SP);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register sp";
  string NAME = ?;
}
def GPRwithAPSR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (add (sub GPR, PC), APSR_NZCV);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
  code AltOrderSelect = [{
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv";
  string NAME = ?;
}
def G_ADD {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_AND {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ANYEXT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ASHR {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_ADD {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_AND {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_MAX {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_MIN {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_NAND {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_OR {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_SUB {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_UMAX {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_UMIN {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_XCHG {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMICRMW_XOR {	// Instruction StandardPseudoInstruction GenericInstruction G_ATOMICRMW_OP
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$val);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMIC_CMPXCHG {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval);
  dag InOperandList = (ins ptype1:$addr, type0:$cmpval, type0:$newval);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ATOMIC_CMPXCHG_WITH_SUCCESS {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$oldval, type1:$success);
  dag InOperandList = (ins type2:$addr, type0:$cmpval, type0:$newval);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_BITCAST {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_BR {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins unknown:$src1);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_BRCOND {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins type0:$tst, unknown:$truebb);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_BRINDIRECT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins type0:$src1);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_BSWAP {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_CONSTANT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins unknown:$imm);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_EXTRACT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$res);
  dag InOperandList = (ins type1:$src, unknown:$offset);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_EXTRACT_VECTOR_ELT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src, type2:$idx);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FABS {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FADD {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FCMP {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins unknown:$tst, type1:$src1, type1:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FCONSTANT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins unknown:$imm);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FDIV {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FEXP {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FEXP2 {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FLOG {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FLOG2 {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FMA {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FMUL {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FNEG {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FPEXT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FPOW {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FPTOSI {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FPTOUI {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FPTRUNC {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FRAME_INDEX {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins unknown:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FREM {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_FSUB {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_GEP {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type1:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_GLOBAL_VALUE {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins unknown:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ICMP {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins unknown:$tst, type1:$src1, type1:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_IMPLICIT_DEF {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_INSERT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src, type1:$op, unknown:$offset);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_INSERT_VECTOR_ELT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src, type1:$elt, type2:$idx);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_INTRINSIC {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins unknown:$intrin, variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_INTRINSIC_W_SIDE_EFFECTS {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins unknown:$intrin, variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_INTTOPTR {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_LOAD {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins ptype1:$addr);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_LSHR {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_MERGE_VALUES {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src0, variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_MUL {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_OR {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_PHI {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_PTRTOINT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_PTR_MASK {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src, unknown:$bits);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SADDO {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst, type1:$carry_out);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SDIV {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SELECT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$tst, type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SEXT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SEXTLOAD {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins ptype1:$addr);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SHL {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SHUFFLE_VECTOR {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$v1, type1:$v2, type2:$mask);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SITOFP {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SMULH {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SMULO {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst, type1:$carry_out);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SREM {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SSUBO {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst, type1:$carry_out);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_STORE {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins type0:$src, ptype1:$addr);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_SUB {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_TRUNC {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_UADDE {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst, type1:$carry_out);
  dag InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_UDIV {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_UITOFP {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_UMULH {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_UMULO {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst, type1:$carry_out);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_UNMERGE_VALUES {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst0, variable_ops);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_UREM {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_USUBE {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst, type1:$carry_out);
  dag InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_VAARG {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$val);
  dag InOperandList = (ins type1:$list, unknown:$align);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_VASTART {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins type0:$list);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_XOR {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type0:$src1, type0:$src2);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ZEXT {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins type1:$src);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def G_ZEXTLOAD {	// Instruction StandardPseudoInstruction GenericInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs type0:$dst);
  dag InOperandList = (ins ptype1:$addr);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def GenExecuteOnly {	// Predicate
  string CondString = "Subtarget->genExecuteOnly()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def GenericDomain {	// Domain
  bits<3> Value = { 0, 0, 0 };
  string NAME = ?;
}
def HINT {	// Instruction InstTemplate Encoding InstARM I AI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_239:$imm, pred:$p);
  string AsmString = "hint${p}	$imm";
  list<dag> Pattern = [(int_arm_hint imm0_239:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeHINTInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<8> imm = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def HLT {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, val{15}, val{14}, val{13}, val{12}, val{11}, val{10}, val{9}, val{8}, val{7}, val{6}, val{5}, val{4}, 0, 1, 1, 1, val{3}, val{2}, val{1}, val{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_65535:$val);
  string AsmString = "hlt	$val";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV8];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<16> val = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def HPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [f16];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (sequence "S%u", 0, 31);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(add (decimate HPR, 2), SPR), (add (decimate HPR, 4), (decimate HPR, 2), (decimate (rotl HPR, 1), 4), (decimate (rotl HPR, 1), 2))];
  code AltOrderSelect = [{
    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
  }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [s0, s31]";
  string NAME = ?;
}
def HVC {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires
  field bits<32> Inst = { 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, imm{15}, imm{14}, imm{13}, imm{12}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, 0, 1, 1, 1, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_65535:$imm);
  string AsmString = "hvc	$imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasVirtualization];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<16> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def Has8MSecExt {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->has8MSecExt()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "Feature8MSecExt";
  string PredicateName = "ARMv8-M Security Extensions";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasAcquireRelease {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasAcquireRelease()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureAcquireRelease";
  string PredicateName = "acquire/release";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasCRC {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasCRC()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureCRC";
  string PredicateName = "crc";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasCrypto {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasCrypto()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureCrypto";
  string PredicateName = "crypto";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasDB {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasDataBarrier()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureDB";
  string PredicateName = "data-barriers";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasDFB {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasFullDataBarrier()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureDFB";
  string PredicateName = "full-data-barrier";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasDPVFP {	// Predicate AssemblerPredicate
  string CondString = "!Subtarget->isFPOnlySP()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "!FeatureVFPOnlySP";
  string PredicateName = "double precision VFP";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasDSP {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasDSP()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureDSP";
  string PredicateName = "dsp";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasDivideInARM {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasDivideInARMMode()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureHWDivARM";
  string PredicateName = "divide in ARM";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasDivideInThumb {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasDivideInThumbMode()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureHWDivThumb";
  string PredicateName = "divide in THUMB";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasDotProd {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasDotProd()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureDotProd";
  string PredicateName = "dotprod";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasFP16 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasFP16()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureFP16";
  string PredicateName = "half-float conversions";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasFPARMv8 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasFPARMv8()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureFPARMv8";
  string PredicateName = "FPARMv8";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasFastVDUP32 {	// Predicate
  string CondString = "!Subtarget->hasSlowVDUP32()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasFastVGETLNi32 {	// Predicate
  string CondString = "!Subtarget->hasSlowVGETLNi32()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasFullFP16 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasFullFP16()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureFullFP16";
  string PredicateName = "full half-float";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasMP {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasMPExtension()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureMP";
  string PredicateName = "mp-extensions";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasNEON {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasNEON()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureNEON";
  string PredicateName = "NEON";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasRAS {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasRAS()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureRAS";
  string PredicateName = "ras";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasSlowVDUP32 {	// Predicate
  string CondString = "Subtarget->hasSlowVDUP32()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasSlowVGETLNi32 {	// Predicate
  string CondString = "Subtarget->hasSlowVGETLNi32()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasTrustZone {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasTrustZone()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureTrustZone";
  string PredicateName = "TrustZone";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV4T {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV4TOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV4TOps";
  string PredicateName = "armv4t";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV4TOps {	// SubtargetFeature
  string Name = "v4t";
  string Attribute = "HasV4TOps";
  string Value = "true";
  string Desc = "Support ARM v4T instructions";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def HasV5T {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV5TOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV5TOps";
  string PredicateName = "armv5t";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV5TE {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV5TEOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV5TEOps";
  string PredicateName = "armv5te";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV5TEOps {	// SubtargetFeature
  string Name = "v5te";
  string Attribute = "HasV5TEOps";
  string Value = "true";
  string Desc = "Support ARM v5TE, v5TEj, and v5TExp instructions";
  list<SubtargetFeature> Implies = [HasV5TOps];
  string NAME = ?;
}
def HasV5TOps {	// SubtargetFeature
  string Name = "v5t";
  string Attribute = "HasV5TOps";
  string Value = "true";
  string Desc = "Support ARM v5T instructions";
  list<SubtargetFeature> Implies = [HasV4TOps];
  string NAME = ?;
}
def HasV6 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV6Ops()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV6Ops";
  string PredicateName = "armv6";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV6K {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV6KOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV6KOps";
  string PredicateName = "armv6k";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV6KOps {	// SubtargetFeature
  string Name = "v6k";
  string Attribute = "HasV6KOps";
  string Value = "true";
  string Desc = "Support ARM v6k instructions";
  list<SubtargetFeature> Implies = [HasV6Ops];
  string NAME = ?;
}
def HasV6M {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV6MOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV6MOps";
  string PredicateName = "armv6m or armv6t2";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV6MOps {	// SubtargetFeature
  string Name = "v6m";
  string Attribute = "HasV6MOps";
  string Value = "true";
  string Desc = "Support ARM v6M instructions";
  list<SubtargetFeature> Implies = [HasV6Ops];
  string NAME = ?;
}
def HasV6Ops {	// SubtargetFeature
  string Name = "v6";
  string Attribute = "HasV6Ops";
  string Value = "true";
  string Desc = "Support ARM v6 instructions";
  list<SubtargetFeature> Implies = [HasV5TEOps];
  string NAME = ?;
}
def HasV6T2 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV6T2Ops()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV6T2Ops";
  string PredicateName = "armv6t2";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV6T2Ops {	// SubtargetFeature
  string Name = "v6t2";
  string Attribute = "HasV6T2Ops";
  string Value = "true";
  string Desc = "Support ARM v6t2 instructions";
  list<SubtargetFeature> Implies = [HasV8MBaselineOps, HasV6KOps, FeatureThumb2];
  string NAME = ?;
}
def HasV7 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV7Ops()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV7Ops";
  string PredicateName = "armv7";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV7Clrex {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV7Clrex()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureV7Clrex";
  string PredicateName = "v7 clrex";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV7Ops {	// SubtargetFeature
  string Name = "v7";
  string Attribute = "HasV7Ops";
  string Value = "true";
  string Desc = "Support ARM v7 instructions";
  list<SubtargetFeature> Implies = [HasV6T2Ops, FeaturePerfMon, FeatureV7Clrex];
  string NAME = ?;
}
def HasV8 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV8Ops()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV8Ops";
  string PredicateName = "armv8";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV8MBaseline {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV8MBaselineOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV8MBaselineOps";
  string PredicateName = "armv8m.base";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV8MBaselineOps {	// SubtargetFeature
  string Name = "v8m";
  string Attribute = "HasV8MBaselineOps";
  string Value = "true";
  string Desc = "Support ARM v8M Baseline instructions";
  list<SubtargetFeature> Implies = [HasV6MOps];
  string NAME = ?;
}
def HasV8MMainline {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV8MMainlineOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV8MMainlineOps";
  string PredicateName = "armv8m.main";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV8MMainlineOps {	// SubtargetFeature
  string Name = "v8m.main";
  string Attribute = "HasV8MMainlineOps";
  string Value = "true";
  string Desc = "Support ARM v8M Mainline instructions";
  list<SubtargetFeature> Implies = [HasV7Ops];
  string NAME = ?;
}
def HasV8Ops {	// SubtargetFeature
  string Name = "v8";
  string Attribute = "HasV8Ops";
  string Value = "true";
  string Desc = "Support ARM v8 instructions";
  list<SubtargetFeature> Implies = [HasV7Ops, FeatureAcquireRelease];
  string NAME = ?;
}
def HasV8_1a {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV8_1aOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV8_1aOps";
  string PredicateName = "armv8.1a";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV8_1aOps {	// SubtargetFeature
  string Name = "v8.1a";
  string Attribute = "HasV8_1aOps";
  string Value = "true";
  string Desc = "Support ARM v8.1a instructions";
  list<SubtargetFeature> Implies = [HasV8Ops];
  string NAME = ?;
}
def HasV8_2a {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV8_2aOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV8_2aOps";
  string PredicateName = "armv8.2a";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV8_2aOps {	// SubtargetFeature
  string Name = "v8.2a";
  string Attribute = "HasV8_2aOps";
  string Value = "true";
  string Desc = "Support ARM v8.2a instructions";
  list<SubtargetFeature> Implies = [HasV8_1aOps];
  string NAME = ?;
}
def HasV8_3a {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasV8_3aOps()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "HasV8_3aOps";
  string PredicateName = "armv8.3a";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasV8_3aOps {	// SubtargetFeature
  string Name = "v8.3a";
  string Attribute = "HasV8_3aOps";
  string Value = "true";
  string Desc = "Support ARM v8.3a instructions";
  list<SubtargetFeature> Implies = [HasV8_2aOps];
  string NAME = ?;
}
def HasVFP2 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasVFP2()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureVFP2";
  string PredicateName = "VFP2";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasVFP3 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasVFP3()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureVFP3";
  string PredicateName = "VFP3";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasVFP4 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->hasVFP4()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureVFP4";
  string PredicateName = "VFP4";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasVirtualization {	// Predicate AssemblerPredicate
  string CondString = "false";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureVirtualization";
  string PredicateName = "virtualization-extensions";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def HasZCZ {	// Predicate
  string CondString = "Subtarget->hasZeroCycleZeroing()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def ICALL_BRANCH_FUNNEL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def IIC_Br {	// InstrItinClass
  string NAME = ?;
}
def IIC_Preload {	// InstrItinClass
  string NAME = ?;
}
def IIC_VABAD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VABAQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VBIND {	// InstrItinClass
  string NAME = ?;
}
def IIC_VBINQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VBINi4D {	// InstrItinClass
  string NAME = ?;
}
def IIC_VBINi4Q {	// InstrItinClass
  string NAME = ?;
}
def IIC_VBINiD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VBINiQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VCNTiD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VCNTiQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VDOTPROD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VEXTD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VEXTQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VFMACD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VFMACQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VFMULD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VFMULQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1dup {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1dupu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1ln {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1lnu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1x2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1x2u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1x3 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1x3u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1x4 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD1x4u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD2dup {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD2dupu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD2ln {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD2lnu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD2u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD2x2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD2x2u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD3 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD3dup {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD3dupu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD3ln {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD3lnu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD3u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD4 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD4dup {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD4dupu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD4ln {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD4lnu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VLD4u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMACD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMACQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMACi16D {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMACi16Q {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMACi32D {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMACi32Q {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOV {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOVD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOVDI {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOVID {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOVIS {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOVISL {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOVImm {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOVN {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOVQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMOVSI {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMULi16D {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMULi16Q {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMULi32D {	// InstrItinClass
  string NAME = ?;
}
def IIC_VMULi32Q {	// InstrItinClass
  string NAME = ?;
}
def IIC_VPALiD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VPALiQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VPBIND {	// InstrItinClass
  string NAME = ?;
}
def IIC_VPERMD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VPERMQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VPERMQ3 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VQUNAiD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VQUNAiQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VRECSD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VRECSQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VSHLi4D {	// InstrItinClass
  string NAME = ?;
}
def IIC_VSHLi4Q {	// InstrItinClass
  string NAME = ?;
}
def IIC_VSHLiD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VSHLiQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1ln {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1lnu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1x2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1x2u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1x3 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1x3u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1x4 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST1x4u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST2ln {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST2lnu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST2u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST2x2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST2x2u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST3 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST3ln {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST3lnu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST3u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST4 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST4ln {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST4lnu {	// InstrItinClass
  string NAME = ?;
}
def IIC_VST4u {	// InstrItinClass
  string NAME = ?;
}
def IIC_VSUBi4D {	// InstrItinClass
  string NAME = ?;
}
def IIC_VSUBi4Q {	// InstrItinClass
  string NAME = ?;
}
def IIC_VSUBiD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VSUBiQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VTB1 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VTB2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VTB3 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VTB4 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VTBX1 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VTBX2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VTBX3 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VTBX4 {	// InstrItinClass
  string NAME = ?;
}
def IIC_VUNAD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VUNAQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_VUNAiD {	// InstrItinClass
  string NAME = ?;
}
def IIC_VUNAiQ {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpALU16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpALU32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpALU64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCMP16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCMP32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCMP64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTDI {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTDS {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTHI {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTHS {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTID {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTIH {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTIS {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTSD {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTSH {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpCVTSI {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpDIV16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpDIV32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpDIV64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpFMAC16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpFMAC32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpFMAC64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpLoad16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpLoad32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpLoad64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpLoad_m {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpLoad_mu {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMAC16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMAC32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMAC64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMOVDI {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMOVID {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMOVIS {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMOVSI {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMUL16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMUL32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpMUL64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpSQRT16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpSQRT32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpSQRT64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpSTAT {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpStore16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpStore32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpStore64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpStore_m {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpStore_mu {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpUNA16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpUNA32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_fpUNA64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_iALUi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iALUr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iALUsi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iALUsir {	// InstrItinClass
  string NAME = ?;
}
def IIC_iALUsr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iALUx {	// InstrItinClass
  string NAME = ?;
}
def IIC_iBITi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iBITr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iBITsi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iBITsr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iCMOVi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iCMOVix2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_iCMOVr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iCMOVsi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iCMOVsr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iCMPi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iCMPr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iCMPsi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iCMPsr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iDIV {	// InstrItinClass
  string NAME = ?;
}
def IIC_iEXTAr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iEXTAsr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iEXTr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_bh_i {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_bh_iu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_bh_r {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_bh_ru {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_bh_si {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_bh_siu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_d_i {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_d_r {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_d_ru {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_i {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_iu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_m {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_mBr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_mu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_r {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_ru {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_si {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoad_siu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iLoadiALU {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMAC16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMAC32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMAC64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMOVi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMOVix2 {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMOVix2addpc {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMOVix2ld {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMOVr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMOVsi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMOVsr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMUL16 {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMUL32 {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMUL64 {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMVNi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMVNr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMVNsi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iMVNsr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iPop {	// InstrItinClass
  string NAME = ?;
}
def IIC_iPop_Br {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_bh_i {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_bh_iu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_bh_r {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_bh_ru {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_bh_si {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_bh_siu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_d_i {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_d_r {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_d_ru {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_i {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_iu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_m {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_mu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_r {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_ru {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_si {	// InstrItinClass
  string NAME = ?;
}
def IIC_iStore_siu {	// InstrItinClass
  string NAME = ?;
}
def IIC_iTSTi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iTSTr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iTSTsi {	// InstrItinClass
  string NAME = ?;
}
def IIC_iTSTsr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iUNAr {	// InstrItinClass
  string NAME = ?;
}
def IIC_iUNAsi {	// InstrItinClass
  string NAME = ?;
}
def IMPLICIT_DEF {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def INLINEASM {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def INSERT_SUBREG {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$supersrc = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def ISB {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, opt{3}, opt{2}, opt{1}, opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins instsyncb_opt:$opt);
  string AsmString = "isb	$opt";
  list<dag> Pattern = [(int_arm_isb (i32 imm0_15:$opt))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasDB];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def ITSTATE {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "itstate";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def ITasm {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo ComplexDeprecationPredicate
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins it_pred:$cc, it_mask:$mask);
  string AsmString = "it$mask $cc";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string ComplexDeprecationPredicate = "IT";
  string NAME = ?;
}
def IWMMXT {	// SubtargetFeature Architecture
  string Name = "iwmmxt";
  string Attribute = "ARMArch";
  string Value = "ARMv5te";
  string Desc = "ARMv5te architecture";
  list<SubtargetFeature> Implies = [ARMv5te];
  string NAME = ?;
}
def IWMMXT2 {	// SubtargetFeature Architecture
  string Name = "iwmmxt2";
  string Attribute = "ARMArch";
  string Value = "ARMv5te";
  string Desc = "ARMv5te architecture";
  list<SubtargetFeature> Implies = [ARMv5te];
  string NAME = ?;
}
def Imm0_15AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_15";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,15>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,15]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_1AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_1";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,1>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,1]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_239AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_239";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,239>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,239]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_255AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_255";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,255>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,255]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_31AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_31";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,31>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,31]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_32AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_32";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,32>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,32]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_3AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_3";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,3>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,3]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_63AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_63";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,63>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,63]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_65535AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_65535";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,65535>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,65535]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_65535ExprAsmOperand {	// AsmOperandClass
  string Name = "Imm0_65535Expr";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm0_7AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_7";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,7>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,7]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm16AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm16";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<16,16>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [16,16]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm1_15AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm1_15";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,15>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [1,15]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm1_16AsmOperand {	// AsmOperandClass ImmAsmOperandMinusOne
  string Name = "Imm1_16";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,16>";
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "ImmRange1_16";
  string DiagnosticString = "operand must be an immediate in the range [1,16]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm1_31AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm1_31";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,31>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [1,31]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm1_32AsmOperand {	// AsmOperandClass ImmAsmOperandMinusOne
  string Name = "Imm1_32";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,32>";
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "ImmRange1_32";
  string DiagnosticString = "operand must be an immediate in the range [1,32]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm1_7AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm1_7";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,7>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [1,7]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm24bitAsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm24bit";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,16777215>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,0xffffff]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm256_65535ExprAsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm256_65535Expr";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<256,65535>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [256,65535]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm32AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm32";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<32,32>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [32,32]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm8AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm8";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<8,8>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [8,8]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Imm8_255AsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm8_255";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<8,255>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [8,255]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ImmAsmOperand {	// AsmOperandClass
  string Name = "Imm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def IndexModeNone {	// IndexMode
  bits<2> Value = { 0, 0 };
  string NAME = ?;
}
def IndexModePost {	// IndexMode
  bits<2> Value = { 1, 0 };
  string NAME = ?;
}
def IndexModePre {	// IndexMode
  bits<2> Value = { 0, 1 };
  string NAME = ?;
}
def IndexModeUpd {	// IndexMode
  bits<2> Value = { 1, 1 };
  string NAME = ?;
}
def InstSyncBarrierOptOperand {	// AsmOperandClass
  string Name = "InstSyncBarrierOpt";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseInstSyncBarrierOptOperand";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Int_eh_sjlj_dispatchsetup {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def Int_eh_sjlj_longjmp {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$src, GPR:$scratch);
  string AsmString = "";
  list<dag> Pattern = [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)];
  list<Register> Uses = [];
  list<Register> Defs = [R7, LR, SP];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def Int_eh_sjlj_setjmp {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$src, GPR:$val);
  string AsmString = "";
  list<dag> Pattern = [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))];
  list<Register> Uses = [];
  list<Register> Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15];
  list<Predicate> Predicates = [IsARM, HasVFP2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def Int_eh_sjlj_setjmp_nofp {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$src, GPR:$val);
  string AsmString = "";
  list<dag> Pattern = [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))];
  list<Register> Uses = [];
  list<Register> Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR];
  list<Predicate> Predicates = [IsARM, NoVFP];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def Int_eh_sjlj_setup_dispatch {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = [(ARMeh_sjlj_setup_dispatch)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def IntrArgMemOnly {	// IntrinsicProperty
  string NAME = ?;
}
def IntrConvergent {	// IntrinsicProperty
  string NAME = ?;
}
def IntrHasSideEffects {	// IntrinsicProperty
  string NAME = ?;
}
def IntrInaccessibleMemOnly {	// IntrinsicProperty
  string NAME = ?;
}
def IntrInaccessibleMemOrArgMemOnly {	// IntrinsicProperty
  string NAME = ?;
}
def IntrNoDuplicate {	// IntrinsicProperty
  string NAME = ?;
}
def IntrNoMem {	// IntrinsicProperty
  string NAME = ?;
}
def IntrNoReturn {	// IntrinsicProperty
  string NAME = ?;
}
def IntrReadMem {	// IntrinsicProperty
  string NAME = ?;
}
def IntrSpeculatable {	// IntrinsicProperty
  string NAME = ?;
}
def IntrWriteMem {	// IntrinsicProperty
  string NAME = ?;
}
def IsARM {	// Predicate AssemblerPredicate
  string CondString = "!Subtarget->isThumb()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "!ModeThumb";
  string PredicateName = "arm-mode";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsBE {	// Predicate
  string CondString = "MF->getDataLayout().isBigEndian()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 1;
  string NAME = ?;
}
def IsCPSRDefinedAndPredicatedPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isCPSRDefined(*MI) && TII->isPredicated(*MI)}];
  string NAME = ?;
}
def IsCPSRDefinedPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isCPSRDefined(*MI)}];
  string NAME = ?;
}
def IsFastImmShiftSwiftPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isSwiftFastImmShift(MI)}];
  string NAME = ?;
}
def IsLE {	// Predicate
  string CondString = "MF->getDataLayout().isLittleEndian()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 1;
  string NAME = ?;
}
def IsLdmBaseRegInList {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isLDMBaseRegInList(*MI)}];
  string NAME = ?;
}
def IsLdrAm2ScaledPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isAm2ScaledReg(*MI, 1)}];
  string NAME = ?;
}
def IsLdrAm3NegRegOffPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isAddrMode3OpMinusReg(*MI, 1)}];
  string NAME = ?;
}
def IsLdrAm3NegRegOffPredX2 {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isAddrMode3OpMinusReg(*MI, 2)}];
  string NAME = ?;
}
def IsLdrAm3NegRegOffPredX3 {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isAddrMode3OpMinusReg(*MI, 3)}];
  string NAME = ?;
}
def IsLdrAm3RegOffPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{!TII->isAddrMode3OpImm(*MI, 1)}];
  string NAME = ?;
}
def IsLdrAm3RegOffPredX2 {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{!TII->isAddrMode3OpImm(*MI, 2)}];
  string NAME = ?;
}
def IsLdrAm3RegOffPredX3 {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{!TII->isAddrMode3OpImm(*MI, 3)}];
  string NAME = ?;
}
def IsLdstsoMinusRegPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isLdstSoMinusReg(*MI, 1)}];
  string NAME = ?;
}
def IsLdstsoMinusRegPredX0 {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isLdstSoMinusReg(*MI, 0)}];
  string NAME = ?;
}
def IsLdstsoMinusRegPredX2 {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isLdstSoMinusReg(*MI, 2)}];
  string NAME = ?;
}
def IsLdstsoScaledNotOptimalPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isLdstScaledRegNotPlusLsl2(*MI, 1)}];
  string NAME = ?;
}
def IsLdstsoScaledNotOptimalPredX0 {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isLdstScaledRegNotPlusLsl2(*MI, 0)}];
  string NAME = ?;
}
def IsLdstsoScaledNotOptimalPredX2 {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isLdstScaledRegNotPlusLsl2(*MI, 2)}];
  string NAME = ?;
}
def IsLdstsoScaledPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isLdstScaledReg(*MI, 1)}];
  string NAME = ?;
}
def IsLdstsoScaledPredX2 {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isLdstScaledReg(*MI, 2)}];
  string NAME = ?;
}
def IsMClass {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->isMClass()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureMClass";
  string PredicateName = "armv*m";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsMachO {	// Predicate
  string CondString = "Subtarget->isTargetMachO()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsNaCl {	// Predicate
  string CondString = "Subtarget->isTargetNaCl()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsNotMClass {	// Predicate AssemblerPredicate
  string CondString = "!Subtarget->isMClass()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "!FeatureMClass";
  string PredicateName = "!armv*m";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsNotMachO {	// Predicate
  string CondString = "!Subtarget->isTargetMachO()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsNotWindows {	// Predicate
  string CondString = "!Subtarget->isTargetWindows()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsPredicatedPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{TII->isPredicated(*MI)}];
  string NAME = ?;
}
def IsR1P0AndLaterPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{false}];
  string NAME = ?;
}
def IsReadTPHard {	// Predicate
  string CondString = "Subtarget->isReadTPHard()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsReadTPSoft {	// Predicate
  string CondString = "!Subtarget->isReadTPHard()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsThumb {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->isThumb()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "ModeThumb";
  string PredicateName = "thumb";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsThumb1Only {	// Predicate
  string CondString = "Subtarget->isThumb1Only()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsThumb2 {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->isThumb2()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "ModeThumb,FeatureThumb2";
  string PredicateName = "thumb2";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def IsWindows {	// Predicate
  string CondString = "Subtarget->isTargetWindows()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def JUMPTABLE_ADDRS {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def JUMPTABLE_INSTS {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def JUMPTABLE_TBB {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def JUMPTABLE_TBH {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def KILL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def LDA {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq Requires AIldracq
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "lda${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDAB {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq Requires AIldracq
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldab${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDAEX {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq Requires AIldaex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldaex${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDAEXB {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq Requires AIldaex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldaexb${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDAEXD {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq Requires AIldaex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRPairOp:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldaexd${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeDoubleRegLoad";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDAEXH {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq Requires AIldaex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldaexh${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDAH {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq Requires AIldracq
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldah${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC2L_OFFSET {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 1, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr);
  string AsmString = "ldc2l	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC2L_OPTION {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option);
  string AsmString = "ldc2l	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC2L_POST {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, offset{8}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset);
  string AsmString = "ldc2l	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC2L_PRE {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 1, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr);
  string AsmString = "ldc2l	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC2_OFFSET {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr);
  string AsmString = "ldc2	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC2_OPTION {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option);
  string AsmString = "ldc2	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC2_POST {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, offset{8}, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset);
  string AsmString = "ldc2	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC2_PRE {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr);
  string AsmString = "ldc2	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDCL_OFFSET {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, 1, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "ldcl${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDCL_OPTION {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "ldcl${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDCL_POST {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, offset{8}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "ldcl${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDCL_PRE {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, 1, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "ldcl${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC_OFFSET {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "ldc${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC_OPTION {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, 0, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "ldc${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC_POST {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, offset{8}, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "ldc${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDC_PRE {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "ldc${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDMDA {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmda${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMLoad";
  string NAME = ?;
}
def LDMDA_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmda${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMLoad";
  string NAME = ?;
}
def LDMDB {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmdb${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMLoad";
  string NAME = ?;
}
def LDMDB_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmdb${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMLoad";
  string NAME = ?;
}
def LDMIA {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldm${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMLoad";
  string NAME = ?;
}
def LDMIA_RET {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand RegConstraint
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mBr;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs);
  string NAME = ?;
}
def LDMIA_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldm${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMLoad";
  string NAME = ?;
}
def LDMIB {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmib${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMLoad";
  string NAME = ?;
}
def LDMIB_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmib${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMLoad";
  string NAME = ?;
}
def LDRBT_POST {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$q);
  string AsmString = "ldrbt${q} $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LDRBT_POST_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 0, offset{12}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am2offset_imm:$offset, pred:$p);
  string AsmString = "ldrbt${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRBT_POST_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, offset{12}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, 0, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am2offset_reg:$offset, pred:$p);
  string AsmString = "ldrbt${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRB_POST_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 0, offset{12}, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am2offset_imm:$offset, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRB_POST_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, offset{12}, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, 0, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am2offset_reg:$offset, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRB_PRE_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 1, addr{12}, 1, 1, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addrmode_imm12_pre:$addr, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeLDRPreImm";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRB_PRE_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, addr{12}, 1, 1, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, 0, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins ldst_so_reg:$addr, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeLDRPreReg";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRBi12 {	// Instruction InstTemplate Encoding InstARM I AI2ldst
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 1, addr{12}, 1, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins addrmode_imm12:$addr, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi8 addrmode_imm12:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRBrs {	// Instruction InstTemplate Encoding InstARM I AI2ldst
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, shift{12}, 1, 0, 1, shift{16}, shift{15}, shift{14}, shift{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins ldst_so_reg:$shift, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $shift";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi8 ldst_so_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_si;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, 0, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRConstPool {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins const_pool_asm_imm:$immediate, pred:$q);
  string AsmString = "ldr${q} $Rt, $immediate";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LDRD {	// Instruction InstTemplate Encoding InstARM I AI3ld Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rt2);
  dag InOperandList = (ins addrmode3:$addr, pred:$p);
  string AsmString = "ldrd${p}	$Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_d_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRD_POST {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, offset{9}, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 1, 0, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am3offset:$offset, pred:$p);
  string AsmString = "ldrd${p}	$Rt, $Rt2, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_d_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRD_PRE {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb);
  dag InOperandList = (ins addrmode3_pre:$addr, pred:$p);
  string AsmString = "ldrd${p}	$Rt, $Rt2, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_d_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDREX {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq AIldrex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldrex${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDREXB {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq AIldrex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldrexb${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDREXD {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq AIldrex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRPairOp:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldrexd${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeDoubleRegLoad";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDREXH {	// Instruction InstTemplate Encoding InstARM I AIldr_ex_or_acq AIldrex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldrexh${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRH {	// Instruction InstTemplate Encoding InstARM I AI3ld
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addrmode3:$addr, pred:$p);
  string AsmString = "ldrh${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRHTi {	// Instruction InstTemplate Encoding InstARM I AI3ldstidxT
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 0, 1, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$base_wb);
  dag InOperandList = (ins addr_offset_none:$addr, postidx_imm8:$offset, pred:$p);
  string AsmString = "ldrht${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $base_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRHTr {	// Instruction InstTemplate Encoding InstARM I AI3ldstidxT
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, Rm{4}, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 1, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt, GPRnopc:$base_wb);
  dag InOperandList = (ins addr_offset_none:$addr, postidx_reg:$Rm, pred:$p);
  string AsmString = "ldrht${p}	$Rt, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $base_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeLDR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<5> Rm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRH_POST {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, offset{9}, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 0, 1, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am3offset:$offset, pred:$p);
  string AsmString = "ldrh${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRH_PRE {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addrmode3_pre:$addr, pred:$p);
  string AsmString = "ldrh${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRLIT_ga_abs {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins i32imm:$src);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, DontUseMovt];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LDRLIT_ga_pcrel {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins i32imm:$addr);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, DontUseMovtInPic];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoadiALU;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LDRLIT_ga_pcrel_ldr {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins i32imm:$addr);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, DontUseMovtInPic];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LDRSB {	// Instruction InstTemplate Encoding InstARM I AI3ld
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addrmode3:$addr, pred:$p);
  string AsmString = "ldrsb${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRSBTi {	// Instruction InstTemplate Encoding InstARM I AI3ldstidxT
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 1, 0, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$base_wb);
  dag InOperandList = (ins addr_offset_none:$addr, postidx_imm8:$offset, pred:$p);
  string AsmString = "ldrsbt${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $base_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRSBTr {	// Instruction InstTemplate Encoding InstARM I AI3ldstidxT
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, Rm{4}, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 1, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt, GPRnopc:$base_wb);
  dag InOperandList = (ins addr_offset_none:$addr, postidx_reg:$Rm, pred:$p);
  string AsmString = "ldrsbt${p}	$Rt, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $base_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeLDR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<5> Rm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRSB_POST {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, offset{9}, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 1, 0, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am3offset:$offset, pred:$p);
  string AsmString = "ldrsb${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRSB_PRE {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addrmode3_pre:$addr, pred:$p);
  string AsmString = "ldrsb${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRSH {	// Instruction InstTemplate Encoding InstARM I AI3ld
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addrmode3:$addr, pred:$p);
  string AsmString = "ldrsh${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRSHTi {	// Instruction InstTemplate Encoding InstARM I AI3ldstidxT
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 1, 1, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$base_wb);
  dag InOperandList = (ins addr_offset_none:$addr, postidx_imm8:$offset, pred:$p);
  string AsmString = "ldrsht${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $base_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRSHTr {	// Instruction InstTemplate Encoding InstARM I AI3ldstidxT
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, Rm{4}, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt, GPRnopc:$base_wb);
  dag InOperandList = (ins addr_offset_none:$addr, postidx_reg:$Rm, pred:$p);
  string AsmString = "ldrsht${p}	$Rt, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $base_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeLDR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<5> Rm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRSH_POST {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, offset{9}, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 1, 1, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am3offset:$offset, pred:$p);
  string AsmString = "ldrsh${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRSH_PRE {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addrmode3_pre:$addr, pred:$p);
  string AsmString = "ldrsh${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = LdMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRT_POST {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$q);
  string AsmString = "ldrt${q} $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LDRT_POST_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 0, offset{12}, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am2offset_imm:$offset, pred:$p);
  string AsmString = "ldrt${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDRT_POST_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, offset{12}, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, 0, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am2offset_reg:$offset, pred:$p);
  string AsmString = "ldrt${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDR_POST_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 0, offset{12}, 0, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am2offset_imm:$offset, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_iu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDR_POST_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, offset{12}, 0, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, 0, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$addr, am2offset_reg:$offset, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def LDR_PRE_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 1, addr{12}, 0, 1, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addrmode_imm12_pre:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_iu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeLDRPreImm";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDR_PRE_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, addr{12}, 0, 1, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, 0, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins ldst_so_reg:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeLDRPreReg";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRcp {	// Instruction InstTemplate Encoding InstARM I AI2ldst
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 1, addr{12}, 0, 0, 1, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addrmode_imm12:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRi12 {	// Instruction InstTemplate Encoding InstARM I AI2ldst
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 1, addr{12}, 0, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addrmode_imm12:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (load addrmode_imm12:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def LDRrs {	// Instruction InstTemplate Encoding InstARM I AI2ldst
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, shift{12}, 0, 0, 1, shift{16}, shift{15}, shift{14}, shift{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins ldst_so_reg:$shift, pred:$p);
  string AsmString = "ldr${p}	$Rt, $shift";
  list<dag> Pattern = [(set GPR:$Rt, (load ldst_so_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_si;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, 0, ?, ?, ?, ? };
  string NAME = ?;
}
def LEApcrel {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins i32imm:$label, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LEApcrelJT {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins i32imm:$label, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LIFETIME_END {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$id);
  string AsmString = "LIFETIME_END";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def LIFETIME_START {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$id);
  string AsmString = "LIFETIME_START";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def LOAD_STACK_GUARD {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs ptr_rc:$dst);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def LOCAL_ESCAPE {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 1;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def LR {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "lr";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [14];
  int CostPerUse = 1;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def LSLi {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s);
  string AsmString = "lsl${s}${p} $Rd, $Rm, $imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rm = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LSLr {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s);
  string AsmString = "lsl${s}${p} $Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LSRi {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s);
  string AsmString = "lsr${s}${p} $Rd, $Rm, $imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rm = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LSRr {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s);
  string AsmString = "lsr${s}${p} $Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def LdFrm {	// Format
  bits<6> Value = { 0, 0, 0, 1, 1, 0 };
  string NAME = ?;
}
def LdMiscFrm {	// Format
  bits<6> Value = { 0, 0, 1, 0, 0, 0 };
  string NAME = ?;
}
def LdStExFrm {	// Format
  bits<6> Value = { 0, 0, 1, 0, 1, 1 };
  string NAME = ?;
}
def LdStMulFrm {	// Format
  bits<6> Value = { 0, 0, 1, 0, 1, 0 };
  string NAME = ?;
}
def MCR {	// Instruction InstTemplate Encoding InstARM I ABI MovRCopro ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, 0, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2, pred:$p);
  string AsmString = "mcr${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2";
  list<dag> Pattern = [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "MCR";
  string NAME = ?;
}
def MCR2 {	// Instruction InstTemplate Encoding InstARM XI ABXI MovRCopro2 Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, 0, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2);
  string AsmString = "mcr2	$cop, $opc1, $Rt, $CRn, $CRm, $opc2";
  list<dag> Pattern = [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string NAME = ?;
}
def MCRR {	// Instruction InstTemplate Encoding InstARM I ABI MovRRCopro
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 0, 1, 0, 0, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm, pred:$p);
  string AsmString = "mcrr${p}	$cop, $opc1, $Rt, $Rt2, $CRm";
  list<dag> Pattern = [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2, imm:$CRm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def MCRR2 {	// Instruction InstTemplate Encoding InstARM XI ABXI Requires MovRRCopro2
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm);
  string AsmString = "mcrr2	$cop, $opc1, $Rt, $Rt2, $CRm";
  list<dag> Pattern = [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2, imm:$CRm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecoderForMRRC2AndMCRR2";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def MEMCPY {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$newdst, GPR:$newsrc);
  dag InOperandList = (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$newdst, GPR:$newsrc, (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$newdst = $dst, $newsrc = $src";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MLA {	// Instruction InstTemplate Encoding InstARM sI AsMul1I AsMul1I32 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 0, 1, s{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s);
  string AsmString = "mla${s}${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def MLAv5 {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s);
  string AsmString = "";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, NoV6];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s);
  string NAME = ?;
}
def MLS {	// Instruction InstTemplate Encoding InstARM I AMul1I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 1, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "mls${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def MOVCCi {	// Instruction InstTemplate PseudoInst ARMPseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$false, mod_imm:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVCCi16 {	// Instruction InstTemplate PseudoInst ARMPseudoInst RegConstraint Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVCCi32imm {	// Instruction InstTemplate PseudoInst ARMPseudoInst RegConstraint Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$false, i32imm:$src, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int Size = 8;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVix2;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVCCr {	// Instruction InstTemplate PseudoInst ARMPseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$false, GPR:$Rm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 1;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVCCsi {	// Instruction InstTemplate PseudoInst ARMPseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVCCsr {	// Instruction InstTemplate PseudoInst ARMPseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVPCLR {	// Instruction InstTemplate Encoding InstARM I AI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "mov${p}	pc, lr";
  list<dag> Pattern = [(ARMretflag)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, NoV4T];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrMiscFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  string NAME = ?;
}
def MOVPCRX {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$dst);
  string AsmString = "";
  list<dag> Pattern = [(brind GPR:$dst)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, NoV4T];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg);
  string NAME = ?;
}
def MOVTi16 {	// Instruction InstTemplate Encoding InstARM I AI1 UnaryDP Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 0, 1, 0, 0, imm{15}, imm{14}, imm{13}, imm{12}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$src, imm0_65535_expr:$imm, pred:$p);
  string AsmString = "movt${p}	$Rd, $imm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (or (and GPR:$src, 65535), lo16AllZero:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$src = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeArmMOVTWInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<16> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def MOVTi16_ga_pcrel {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$src, i32imm:$addr, pclabel:$id);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$src = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOV_ga_pcrel {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins i32imm:$addr);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, UseMovtInPic];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVix2addpc;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOV_ga_pcrel_ldr {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins i32imm:$addr);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, UseMovtInPic];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVix2ld;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVi {	// Instruction InstTemplate Encoding InstARM sI AsI1 UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 1, 0, 1, s{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "mov${s}${p}	$Rd, $imm";
  list<dag> Pattern = [(set GPR:$Rd, mod_imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def MOVi16 {	// Instruction InstTemplate Encoding InstARM I AI1 Requires UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 0, 0, 0, 0, imm{15}, imm{14}, imm{13}, imm{12}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins imm0_65535_expr:$imm, pred:$p);
  string AsmString = "movw${p}	$Rd, $imm";
  list<dag> Pattern = [(set GPR:$Rd, imm0_65535:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeArmMOVTWInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<16> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def MOVi16_ga_pcrel {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins i32imm:$addr, pclabel:$id);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVi32imm {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins i32imm:$src);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (arm_i32imm:src))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVix2;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVr {	// Instruction InstTemplate Encoding InstARM sI AsI1 UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 1, s{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "mov${s}${p}	$Rd, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def MOVr_TC {	// Instruction InstTemplate Encoding InstARM sI AsI1 UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 1, s{0}, ?, ?, ?, ?, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tcGPR:$Rd);
  dag InOperandList = (ins tcGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "mov${s}${p}	$Rd, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def MOVsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 1, s{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, src{11}, src{10}, src{9}, src{8}, src{7}, src{6}, src{5}, 0, src{3}, src{2}, src{1}, src{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins shift_so_reg_imm:$src, pred:$p, cc_out:$s);
  string AsmString = "mov${s}${p}	$Rd, $src";
  list<dag> Pattern = [(set GPR:$Rd, shift_so_reg_imm:$src)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> src = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def MOVsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 1, s{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, src{11}, src{10}, src{9}, src{8}, 0, src{6}, src{5}, 1, src{3}, src{2}, src{1}, src{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins shift_so_reg_reg:$src, pred:$p, cc_out:$s);
  string AsmString = "mov${s}${p}	$Rd, $src";
  list<dag> Pattern = [(set GPRnopc:$Rd, shift_so_reg_reg:$src)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> src = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def MOVsra_flag {	// Instruction InstTemplate PseudoInst UnaryDP Sched Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins GPR:$src);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (ARMsra_flag GPR:$src))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MOVsrl_flag {	// Instruction InstTemplate PseudoInst UnaryDP Sched Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins GPR:$src);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (ARMsrl_flag GPR:$src))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MRC {	// Instruction InstTemplate Encoding InstARM I ABI MovRCopro
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, 1, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRwithAPSR:$Rt);
  dag InOperandList = (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2, pred:$p);
  string AsmString = "mrc${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string NAME = ?;
}
def MRC2 {	// Instruction InstTemplate Encoding InstARM XI ABXI MovRCopro2 Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, 1, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRwithAPSR:$Rt);
  dag InOperandList = (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2);
  string AsmString = "mrc2	$cop, $opc1, $Rt, $CRn, $CRm, $opc2";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string NAME = ?;
}
def MRRC {	// Instruction InstTemplate Encoding InstARM I ABI MovRRCopro
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 0, 1, 0, 1, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt, GPRnopc:$Rt2);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm, pred:$p);
  string AsmString = "mrrc${p}	$cop, $opc1, $Rt, $Rt2, $CRm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def MRRC2 {	// Instruction InstTemplate Encoding InstARM XI ABXI Requires MovRRCopro2
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt, GPRnopc:$Rt2);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm);
  string AsmString = "mrrc2	$cop, $opc1, $Rt, $Rt2, $CRm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecoderForMRRC2AndMCRR2";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def MRS {	// Instruction InstTemplate Encoding InstARM I ABI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins pred:$p);
  string AsmString = "mrs${p}	$Rd, apsr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def MRSbanked {	// Instruction InstTemplate Encoding InstARM I ABI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, banked{5}, 0, 0, banked{3}, banked{2}, banked{1}, banked{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, banked{4}, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins banked_reg:$banked, pred:$p);
  string AsmString = "mrs${p}	$Rd, $banked";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasVirtualization];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<6> banked = { ?, ?, ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def MRSsys {	// Instruction InstTemplate Encoding InstARM I ABI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 0, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins pred:$p);
  string AsmString = "mrs${p}	$Rd, spsr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def MSR {	// Instruction InstTemplate Encoding InstARM I ABI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, mask{4}, 1, 0, mask{3}, mask{2}, mask{1}, mask{0}, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins msr_mask:$mask, GPR:$Rn, pred:$p);
  string AsmString = "msr${p}	$mask, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> mask = { ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def MSRMaskOperand {	// AsmOperandClass
  string Name = "MSRMask";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseMSRMaskOperand";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MSRbanked {	// Instruction InstTemplate Encoding InstARM I ABI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, banked{5}, 1, 0, banked{3}, banked{2}, banked{1}, banked{0}, 1, 1, 1, 1, 0, 0, 1, banked{4}, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins banked_reg:$banked, GPRnopc:$Rn, pred:$p);
  string AsmString = "msr${p}	$banked, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasVirtualization];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<6> banked = { ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def MSRi {	// Instruction InstTemplate Encoding InstARM I ABI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 0, mask{4}, 1, 0, mask{3}, mask{2}, mask{1}, mask{0}, 1, 1, 1, 1, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins msr_mask:$mask, mod_imm:$imm, pred:$p);
  string AsmString = "msr${p}	$mask, $imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> mask = { ?, ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def MUL {	// Instruction InstTemplate Encoding InstARM sI AsMul1I AsMul1I32 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 0, 0, s{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s);
  string AsmString = "mul${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL32;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def MULv5 {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s);
  string AsmString = "";
  list<dag> Pattern = [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, NoV6, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL32;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s);
  string NAME = ?;
}
def MVFR0 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "mvfr0";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def MVFR1 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "mvfr1";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def MVFR2 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "mvfr2";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def MVNCCi {	// Instruction InstTemplate PseudoInst ARMPseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$false, mod_imm:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def MVNi {	// Instruction InstTemplate Encoding InstARM sI AsI1 UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 1, 1, 1, s{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "mvn${s}${p}	$Rd, $imm";
  list<dag> Pattern = [(set GPR:$Rd, mod_imm_not:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMVNi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def MVNr {	// Instruction InstTemplate Encoding InstARM sI AsI1 UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 1, s{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "mvn${s}${p}	$Rd, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (not GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMVNr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def MVNsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 1, s{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "mvn${s}${p}	$Rd, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (not so_reg_imm:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMVNsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def MVNsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 UnaryDP Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 1, s{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "mvn${s}${p}	$Rd, $shift";
  list<dag> Pattern = [(set GPRnopc:$Rd, (not so_reg_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMVNsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def MemBarrierOptOperand {	// AsmOperandClass
  string Name = "MemBarrierOpt";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseMemBarrierOptOperand";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MemImm0_1020s4OffsetAsmOperand {	// AsmOperandClass
  string Name = "MemImm0_1020s4Offset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MemImm12OffsetAsmOperand {	// AsmOperandClass
  string Name = "MemImm12Offset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MemImm8OffsetAsmOperand {	// AsmOperandClass
  string Name = "MemImm8Offset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MemImm8s4OffsetAsmOperand {	// AsmOperandClass
  string Name = "MemImm8s4Offset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MemNegImm8OffsetAsmOperand {	// AsmOperandClass
  string Name = "MemNegImm8Offset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MemNoOffsetAsmOperand {	// AsmOperandClass
  string Name = "MemNoOffset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MemPosImm8OffsetAsmOperand {	// AsmOperandClass
  string Name = "MemPosImm8Offset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MemRegOffsetAsmOperand {	// AsmOperandClass
  string Name = "MemRegOffset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def MetadataVT {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 249;
  string NAME = ?;
}
def MiscFrm {	// Format
  bits<6> Value = { 0, 1, 1, 0, 1, 0 };
  string NAME = ?;
}
def ModImmAsmOperand {	// AsmOperandClass
  string Name = "ModImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseModImm";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ModImmNegAsmOperand {	// AsmOperandClass
  string Name = "ModImmNeg";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ModImmNotAsmOperand {	// AsmOperandClass
  string Name = "ModImmNot";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ModeSoftFloat {	// SubtargetFeature
  string Name = "soft-float";
  string Attribute = "UseSoftFloat";
  string Value = "true";
  string Desc = "Use software floating point features.";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ModeThumb {	// SubtargetFeature
  string Name = "thumb-mode";
  string Attribute = "InThumbMode";
  string Value = "true";
  string Desc = "Thumb mode";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def MulFrm {	// Format
  bits<6> Value = { 0, 0, 0, 0, 0, 1 };
  string NAME = ?;
}
def N1RegModImmFrm {	// Format
  bits<6> Value = { 0, 1, 1, 1, 1, 1 };
  string NAME = ?;
}
def N2RegFrm {	// Format
  bits<6> Value = { 1, 0, 0, 0, 0, 0 };
  string NAME = ?;
}
def N2RegVShLFrm {	// Format
  bits<6> Value = { 1, 0, 0, 0, 1, 1 };
  string NAME = ?;
}
def N2RegVShRFrm {	// Format
  bits<6> Value = { 1, 0, 0, 1, 0, 0 };
  string NAME = ?;
}
def N3RegCplxFrm {	// Format
  bits<6> Value = { 1, 0, 1, 0, 1, 1 };
  string NAME = ?;
}
def N3RegFrm {	// Format
  bits<6> Value = { 1, 0, 0, 1, 0, 1 };
  string NAME = ?;
}
def N3RegVShFrm {	// Format
  bits<6> Value = { 1, 0, 0, 1, 1, 0 };
  string NAME = ?;
}
def NDupFrm {	// Format
  bits<6> Value = { 0, 1, 1, 1, 0, 1 };
  string NAME = ?;
}
def NEONimmAllOnesV {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (NEONvmovImm (i32 timm));
  code PredicateCode = [{
  ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
  unsigned EltBits = 0;
  uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
  return (EltBits == 8 && EltVal == 0xff);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def NEONimmAllZerosV {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (NEONvmovImm (i32 timm));
  code PredicateCode = [{
  ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
  unsigned EltBits = 0;
  uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
  return (EltBits == 32 && EltVal == 0);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def NEONtrn {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VTRN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHUF2;
  string NAME = ?;
}
def NEONuzp {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VUZP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHUF2;
  string NAME = ?;
}
def NEONvbicImm {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VBICIMM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVORRIMM;
  string NAME = ?;
}
def NEONvbsl {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VBSL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_3883;
  string NAME = ?;
}
def NEONvceq {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCEQ";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMP;
  string NAME = ?;
}
def NEONvceqz {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCEQZ";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMPZ;
  string NAME = ?;
}
def NEONvcge {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCGE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMP;
  string NAME = ?;
}
def NEONvcgeu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCGEU";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMP;
  string NAME = ?;
}
def NEONvcgez {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCGEZ";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMPZ;
  string NAME = ?;
}
def NEONvcgt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCGT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMP;
  string NAME = ?;
}
def NEONvcgtu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCGTU";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMP;
  string NAME = ?;
}
def NEONvcgtz {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCGTZ";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMPZ;
  string NAME = ?;
}
def NEONvclez {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCLEZ";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMPZ;
  string NAME = ?;
}
def NEONvcltz {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VCLTZ";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMPZ;
  string NAME = ?;
}
def NEONvdup {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VDUP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_3884;
  string NAME = ?;
}
def NEONvduplane {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VDUPLANE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_3885;
  string NAME = ?;
}
def NEONvext {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VEXT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVEXT;
  string NAME = ?;
}
def NEONvgetlanes {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VGETLANEs";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVGETLN;
  string NAME = ?;
}
def NEONvgetlaneu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VGETLANEu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVGETLN;
  string NAME = ?;
}
def NEONvmovFPImm {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMOVFPIMM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVMOVIMM;
  string NAME = ?;
}
def NEONvmovImm {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMOVIMM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVMOVIMM;
  string NAME = ?;
}
def NEONvmulls {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMULLs";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVMULL;
  string NAME = ?;
}
def NEONvmullu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMULLu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVMULL;
  string NAME = ?;
}
def NEONvmvnImm {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMVNIMM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVMOVIMM;
  string NAME = ?;
}
def NEONvorrImm {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VORRIMM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVORRIMM;
  string NAME = ?;
}
def NEONvqrshrns {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VQRSHRNs";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHX;
  string NAME = ?;
}
def NEONvqrshrnsu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VQRSHRNsu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHX;
  string NAME = ?;
}
def NEONvqrshrnu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VQRSHRNu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHX;
  string NAME = ?;
}
def NEONvqshls {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VQSHLs";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSH;
  string NAME = ?;
}
def NEONvqshlsu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VQSHLsu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSH;
  string NAME = ?;
}
def NEONvqshlu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VQSHLu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSH;
  string NAME = ?;
}
def NEONvqshrns {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VQSHRNs";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHX;
  string NAME = ?;
}
def NEONvqshrnsu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VQSHRNsu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHX;
  string NAME = ?;
}
def NEONvqshrnu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VQSHRNu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHX;
  string NAME = ?;
}
def NEONvrev16 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VREV16";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHUF;
  string NAME = ?;
}
def NEONvrev32 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VREV32";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHUF;
  string NAME = ?;
}
def NEONvrev64 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VREV64";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHUF;
  string NAME = ?;
}
def NEONvrshrn {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VRSHRN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHX;
  string NAME = ?;
}
def NEONvrshrs {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VRSHRs";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSH;
  string NAME = ?;
}
def NEONvrshru {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VRSHRu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSH;
  string NAME = ?;
}
def NEONvshl {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VSHL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSH;
  string NAME = ?;
}
def NEONvshrn {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VSHRN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHX;
  string NAME = ?;
}
def NEONvshrs {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VSHRs";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSH;
  string NAME = ?;
}
def NEONvshru {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VSHRu";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSH;
  string NAME = ?;
}
def NEONvsli {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VSLI";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHINS;
  string NAME = ?;
}
def NEONvsri {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VSRI";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHINS;
  string NAME = ?;
}
def NEONvtbl1 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VTBL1";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVTBL1;
  string NAME = ?;
}
def NEONvtbl2 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VTBL2";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVTBL2;
  string NAME = ?;
}
def NEONvtst {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VTST";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVCMP;
  string NAME = ?;
}
def NEONzip {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VZIP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTARMVSHUF2;
  string NAME = ?;
}
def NGetLnFrm {	// Format
  bits<6> Value = { 0, 1, 1, 0, 1, 1 };
  string NAME = ?;
}
def NLdStFrm {	// Format
  bits<6> Value = { 0, 1, 1, 1, 1, 0 };
  string NAME = ?;
}
def NOOP_SDNodeXForm {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{}];
  string NAME = ?;
}
def NSetLnFrm {	// Format
  bits<6> Value = { 0, 1, 1, 1, 0, 0 };
  string NAME = ?;
}
def NVCVTFrm {	// Format
  bits<6> Value = { 1, 0, 0, 0, 0, 1 };
  string NAME = ?;
}
def NVDupLnFrm {	// Format
  bits<6> Value = { 1, 0, 0, 0, 1, 0 };
  string NAME = ?;
}
def NVExtFrm {	// Format
  bits<6> Value = { 1, 0, 0, 1, 1, 1 };
  string NAME = ?;
}
def NVMulSLFrm {	// Format
  bits<6> Value = { 1, 0, 1, 0, 0, 0 };
  string NAME = ?;
}
def NVTBLFrm {	// Format
  bits<6> Value = { 1, 0, 1, 0, 0, 1 };
  string NAME = ?;
}
def NeonDomain {	// Domain
  bits<3> Value = { 0, 1, 0 };
  string NAME = ?;
}
def NoBypass {	// Bypass
  string NAME = ?;
}
def NoHonorSignDependentRounding {	// Predicate
  string CondString = "!TM.Options.HonorSignDependentRoundingFPMath()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def NoItineraries {	// ProcessorItineraries
  list<FuncUnit> FU = [];
  list<Bypass> BP = [];
  list<InstrItinData> IID = [];
  string NAME = ?;
}
def NoItinerary {	// InstrItinClass
  string NAME = ?;
}
def NoReadAdvance {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def NoRegAltName {	// RegAltNameIndex
  string Namespace = "";
  string NAME = ?;
}
def NoSchedModel {	// SchedMachineModel
  int IssueWidth = -1;
  int MicroOpBufferSize = -1;
  int LoopMicroOpBufferSize = -1;
  int LoadLatency = -1;
  int HighLatency = -1;
  int MispredictPenalty = -1;
  ProcessorItineraries Itineraries = NoItineraries;
  bit PostRAScheduler = 0;
  bit CompleteModel = 0;
  bit FullInstRWOverlapCheck = 1;
  list<Predicate> UnsupportedFeatures = [];
  bit NoModel = 1;
  string NAME = ?;
}
def NoSchedPred {	// SchedPredicate
  SchedMachineModel SchedModel = ?;
  code Predicate = [{true}];
  string NAME = ?;
}
def NoV4T {	// Predicate
  string CondString = "!Subtarget->hasV4TOps()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def NoV6 {	// Predicate
  string CondString = "!Subtarget->hasV6Ops()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def NoV6K {	// Predicate
  string CondString = "!Subtarget->hasV6KOps()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def NoV6T2 {	// Predicate
  string CondString = "!Subtarget->hasV6T2Ops()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def NoVFP {	// Predicate
  string CondString = "!Subtarget->hasVFP2()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def NoWrite {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def ORRri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "orr${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, (or GPR:$Rn, mod_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ORRrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "orr${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (or GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def ORRrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "orr${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (or GPR:$Rn, so_reg_imm:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ORRrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "orr${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (or GPR:$Rn, so_reg_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def OtherVT {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 1;
  string NAME = ?;
}
def PATCHABLE_EVENT_CALL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins ptr_rc:$event, i8imm:$size);
  string AsmString = "# XRay Custom Event Log.";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def PATCHABLE_FUNCTION_ENTER {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "# XRay Function Enter.";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def PATCHABLE_FUNCTION_EXIT {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "# XRay Function Exit.";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def PATCHABLE_OP {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def PATCHABLE_RET {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins variable_ops);
  string AsmString = "# XRay Function Patchable RET.";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def PATCHABLE_TAIL_CALL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins variable_ops);
  string AsmString = "# XRay Tail Call Exit.";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def PATCHABLE_TYPED_EVENT_CALL {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i16imm:$type, ptr_rc:$event, i32imm:$size);
  string AsmString = "# XRay Typed Event Log.";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def PATCHPOINT {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, i32imm:$nargs, i32imm:$cc, variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def PC {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "pc";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [15];
  int CostPerUse = 1;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def PHI {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins variable_ops);
  string AsmString = "PHINODE";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def PICADD {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins GPR:$a, pclabel:$cp, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def PICLDR {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins addrmodepc:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (load addrmodepc:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def PICLDRB {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addrmodepc:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def PICLDRH {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addrmodepc:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def PICLDRSB {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addrmodepc:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def PICLDRSH {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins addrmodepc:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def PICSTR {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$src, addrmodepc:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(store GPR:$src, addrmodepc:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def PICSTRB {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$src, addrmodepc:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(truncstorei8 GPR:$src, addrmodepc:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def PICSTRH {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$src, addrmodepc:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(truncstorei16 GPR:$src, addrmodepc:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def PKHASRAsmOperand {	// AsmOperandClass
  string Name = "PKHASRImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parsePKHASRImm";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def PKHBT {	// Instruction InstTemplate Encoding InstARM I APKHI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{4}, sh{3}, sh{2}, sh{1}, sh{0}, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh, pred:$p);
  string AsmString = "pkhbt${p}	$Rd, $Rn, $Rm$sh";
  list<dag> Pattern = [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 65535), (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4294901760)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ArithMiscFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> sh = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def PKHLSLAsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "PKHLSLImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,31>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = "parsePKHLSLImm";
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,31]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def PKHTB {	// Instruction InstTemplate Encoding InstARM I APKHI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{4}, sh{3}, sh{2}, sh{1}, sh{0}, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh, pred:$p);
  string AsmString = "pkhtb${p}	$Rd, $Rn, $Rm$sh";
  list<dag> Pattern = [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 4294901760), (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 65535)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ArithMiscFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> sh = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def PLDWi12 {	// Instruction InstTemplate Encoding InstARM XI AXIM Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 1, addr{12}, 0, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, 1, 1, 1, 1, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode_imm12:$addr);
  string AsmString = "pldw	$addr";
  list<dag> Pattern = [(ARMPreload addrmode_imm12:$addr, (i32 0), (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV7, HasMP];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def PLDWrs {	// Instruction InstTemplate Encoding InstARM XI AXI Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 1, shift{12}, 0, 0, 1, shift{16}, shift{15}, shift{14}, shift{13}, 1, 1, 1, 1, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins ldst_so_reg:$shift);
  string AsmString = "pldw	$shift";
  list<dag> Pattern = [(ARMPreload ldst_so_reg:$shift, (i32 0), (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV7, HasMP];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<17> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def PLDi12 {	// Instruction InstTemplate Encoding InstARM XI AXIM Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 1, addr{12}, 1, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, 1, 1, 1, 1, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode_imm12:$addr);
  string AsmString = "pld	$addr";
  list<dag> Pattern = [(ARMPreload addrmode_imm12:$addr, (i32 1), (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def PLDrs {	// Instruction InstTemplate Encoding InstARM XI AXI Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 1, shift{12}, 1, 0, 1, shift{16}, shift{15}, shift{14}, shift{13}, 1, 1, 1, 1, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins ldst_so_reg:$shift);
  string AsmString = "pld	$shift";
  list<dag> Pattern = [(ARMPreload ldst_so_reg:$shift, (i32 1), (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<17> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def PLIi12 {	// Instruction InstTemplate Encoding InstARM XI AXIM Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, addr{12}, 1, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, 1, 1, 1, 1, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode_imm12:$addr);
  string AsmString = "pli	$addr";
  list<dag> Pattern = [(ARMPreload addrmode_imm12:$addr, (i32 1), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV7];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def PLIrs {	// Instruction InstTemplate Encoding InstARM XI AXI Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 0, shift{12}, 1, 0, 1, shift{16}, shift{15}, shift{14}, shift{13}, 1, 1, 1, 1, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins ldst_so_reg:$shift);
  string AsmString = "pli	$shift";
  list<dag> Pattern = [(ARMPreload ldst_so_reg:$shift, (i32 1), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV7];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<17> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def PostIdxImm8AsmOperand {	// AsmOperandClass
  string Name = "PostIdxImm8";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def PostIdxImm8s4AsmOperand {	// AsmOperandClass
  string Name = "PostIdxImm8s4";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def PostIdxRegAsmOperand {	// AsmOperandClass
  string Name = "PostIdxReg";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parsePostIdxReg";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def PostIdxRegShiftedAsmOperand {	// AsmOperandClass
  string Name = "PostIdxRegShifted";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parsePostIdxReg";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def PreV8 {	// Predicate AssemblerPredicate
  string CondString = "!Subtarget->hasV8Ops()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "!HasV8Ops";
  string PredicateName = "armv7 or earlier";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def ProcA12 {	// SubtargetFeature
  string Name = "a12";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA12";
  string Desc = "Cortex-A12 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA15 {	// SubtargetFeature
  string Name = "a15";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA15";
  string Desc = "Cortex-A15 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA17 {	// SubtargetFeature
  string Name = "a17";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA17";
  string Desc = "Cortex-A17 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA32 {	// SubtargetFeature
  string Name = "a32";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA32";
  string Desc = "Cortex-A32 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA35 {	// SubtargetFeature
  string Name = "a35";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA35";
  string Desc = "Cortex-A35 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA5 {	// SubtargetFeature
  string Name = "a5";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA5";
  string Desc = "Cortex-A5 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA53 {	// SubtargetFeature
  string Name = "a53";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA53";
  string Desc = "Cortex-A53 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA55 {	// SubtargetFeature
  string Name = "a55";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA55";
  string Desc = "Cortex-A55 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA57 {	// SubtargetFeature
  string Name = "a57";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA57";
  string Desc = "Cortex-A57 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA7 {	// SubtargetFeature
  string Name = "a7";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA7";
  string Desc = "Cortex-A7 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA72 {	// SubtargetFeature
  string Name = "a72";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA72";
  string Desc = "Cortex-A72 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA73 {	// SubtargetFeature
  string Name = "a73";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA73";
  string Desc = "Cortex-A73 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA75 {	// SubtargetFeature
  string Name = "a75";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA75";
  string Desc = "Cortex-A75 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA8 {	// SubtargetFeature
  string Name = "a8";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA8";
  string Desc = "Cortex-A8 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcA9 {	// SubtargetFeature
  string Name = "a9";
  string Attribute = "ARMProcFamily";
  string Value = "CortexA9";
  string Desc = "Cortex-A9 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcExynosM1 {	// SubtargetFeature
  string Name = "exynosm1";
  string Attribute = "ARMProcFamily";
  string Value = "ExynosM1";
  string Desc = "Samsung Exynos-Mx processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcIFlagsOperand {	// AsmOperandClass
  string Name = "ProcIFlags";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseProcIFlagsOperand";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ProcKrait {	// SubtargetFeature
  string Name = "krait";
  string Attribute = "ARMProcFamily";
  string Value = "Krait";
  string Desc = "Qualcomm Krait processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcKryo {	// SubtargetFeature
  string Name = "kryo";
  string Attribute = "ARMProcFamily";
  string Value = "Kryo";
  string Desc = "Qualcomm Kryo processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcM3 {	// SubtargetFeature
  string Name = "m3";
  string Attribute = "ARMProcFamily";
  string Value = "CortexM3";
  string Desc = "Cortex-M3 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcR4 {	// SubtargetFeature
  string Name = "r4";
  string Attribute = "ARMProcFamily";
  string Value = "CortexR4";
  string Desc = "Cortex-R4 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcR5 {	// SubtargetFeature
  string Name = "r5";
  string Attribute = "ARMProcFamily";
  string Value = "CortexR5";
  string Desc = "Cortex-R5 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcR52 {	// SubtargetFeature
  string Name = "r52";
  string Attribute = "ARMProcFamily";
  string Value = "CortexR52";
  string Desc = "Cortex-R52 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcR7 {	// SubtargetFeature
  string Name = "r7";
  string Attribute = "ARMProcFamily";
  string Value = "CortexR7";
  string Desc = "Cortex-R7 ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def ProcSwift {	// SubtargetFeature
  string Name = "swift";
  string Attribute = "ARMProcFamily";
  string Value = "Swift";
  string Desc = "Swift ARM processors";
  list<SubtargetFeature> Implies = [];
  string NAME = ?;
}
def Pseudo {	// Format
  bits<6> Value = { 0, 0, 0, 0, 0, 0 };
  string NAME = ?;
}
def Q0 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q0";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D0, D1];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q1 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q1";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D2, D3];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q10 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q10";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D20, D21];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q11 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q11";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D22, D23];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q12 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q12";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D24, D25];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q13 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q13";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D26, D27];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q14 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q14";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D28, D29];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q15 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q15";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D30, D31];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q2 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q2";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D4, D5];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q3 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q3";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D6, D7];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q4 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q4";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D8, D9];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q5 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q5";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D10, D11];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q6 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q6";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D12, D13];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q7 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q7";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D14, D15];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q8 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q8";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D16, D17];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def Q9 {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "q9";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [D18, D19];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def QADD {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIRevOpr
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, GPRnopc:$Rn, pred:$p);
  string AsmString = "qadd${p}	$Rd, $Rm, $Rn";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeQADDInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def QADD16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "qadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qadd16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def QADD8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "qadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qadd8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def QASX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "qasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qasx GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def QDADD {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIRevOpr
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, GPRnopc:$Rn, pred:$p);
  string AsmString = "qdadd${p}	$Rd, $Rm, $Rn";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rm), GPRnopc:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def QDSUB {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIRevOpr
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, GPRnopc:$Rn, pred:$p);
  string AsmString = "qdsub${p}	$Rd, $Rm, $Rn";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def QPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16];
  int Size = 0;
  int Alignment = 128;
  int CopyCost = 1;
  dag MemberList = (sequence "Q%u", 0, 15);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(rotl QPR, 8)];
  code AltOrderSelect = [{ return 1; }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [q0, q15]";
  string NAME = ?;
}
def QPR_8 {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64];
  int Size = 0;
  int Alignment = 128;
  int CopyCost = 1;
  dag MemberList = (trunc QPR, 4);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [q0, q3]";
  string NAME = ?;
}
def QPR_VFP2 {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64];
  int Size = 0;
  int Alignment = 128;
  int CopyCost = 1;
  dag MemberList = (trunc QPR, 8);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [q0, q7]";
  string NAME = ?;
}
def QQPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [v4i64];
  int Size = 0;
  int Alignment = 256;
  int CopyCost = 1;
  dag MemberList = (add Tuples2Q);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(rotl QQPR, 8)];
  code AltOrderSelect = [{ return 1; }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def QQQQPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [v8i64];
  int Size = 0;
  int Alignment = 256;
  int CopyCost = 1;
  dag MemberList = (add Tuples2QQ);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(rotl QQQQPR, 8)];
  code AltOrderSelect = [{ return 1; }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def QSAX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "qsax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qsax GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def QSUB {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIRevOpr
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, GPRnopc:$Rn, pred:$p);
  string AsmString = "qsub${p}	$Rd, $Rm, $Rn";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def QSUB16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "qsub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qsub16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def QSUB8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "qsub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_qsub8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def R0 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r0";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [0];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R1 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r1";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [1];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R10 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r10";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [10];
  int CostPerUse = 1;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R11 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r11";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [11];
  int CostPerUse = 1;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R12 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r12";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [12];
  int CostPerUse = 1;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R2 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r2";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [2];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R3 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r3";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [3];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R4 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r4";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [4];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R5 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r5";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [5];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R52ILDMAddr10Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 10}];
  string NAME = ?;
}
def R52ILDMAddr11Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 11}];
  string NAME = ?;
}
def R52ILDMAddr12Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 12}];
  string NAME = ?;
}
def R52ILDMAddr13Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 13}];
  string NAME = ?;
}
def R52ILDMAddr14Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 14}];
  string NAME = ?;
}
def R52ILDMAddr15Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 15}];
  string NAME = ?;
}
def R52ILDMAddr16Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 16}];
  string NAME = ?;
}
def R52ILDMAddr1Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 1}];
  string NAME = ?;
}
def R52ILDMAddr2Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 2}];
  string NAME = ?;
}
def R52ILDMAddr3Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 3}];
  string NAME = ?;
}
def R52ILDMAddr4Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 4}];
  string NAME = ?;
}
def R52ILDMAddr5Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 5}];
  string NAME = ?;
}
def R52ILDMAddr6Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 6}];
  string NAME = ?;
}
def R52ILDMAddr7Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 7}];
  string NAME = ?;
}
def R52ILDMAddr8Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 8}];
  string NAME = ?;
}
def R52ILDMAddr9Pred {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 9}];
  string NAME = ?;
}
def R52LMAddrPred1 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 1}];
  string NAME = ?;
}
def R52LMAddrPred10 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 10}];
  string NAME = ?;
}
def R52LMAddrPred11 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 11}];
  string NAME = ?;
}
def R52LMAddrPred12 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 12}];
  string NAME = ?;
}
def R52LMAddrPred13 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 13}];
  string NAME = ?;
}
def R52LMAddrPred14 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 14}];
  string NAME = ?;
}
def R52LMAddrPred15 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 15}];
  string NAME = ?;
}
def R52LMAddrPred16 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 16}];
  string NAME = ?;
}
def R52LMAddrPred2 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 2}];
  string NAME = ?;
}
def R52LMAddrPred3 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 3}];
  string NAME = ?;
}
def R52LMAddrPred4 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 4}];
  string NAME = ?;
}
def R52LMAddrPred5 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 5}];
  string NAME = ?;
}
def R52LMAddrPred6 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 6}];
  string NAME = ?;
}
def R52LMAddrPred7 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 7}];
  string NAME = ?;
}
def R52LMAddrPred8 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 8}];
  string NAME = ?;
}
def R52LMAddrPred9 {	// SchedPredicate
  SchedMachineModel SchedModel = CortexR52Model;
  code Predicate = [{MI->getNumOperands() == 9}];
  string NAME = ?;
}
def R52Read_EX1 {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def R52Read_EX2 {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def R52Read_F0 {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def R52Read_F1 {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def R52Read_F2 {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def R52Read_ISS {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def R52Read_WRI {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def R52ReserveLd10Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [10];
  int Latency = 0;
  int NumMicroOps = 10;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd11Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [11];
  int Latency = 0;
  int NumMicroOps = 11;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd12Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [12];
  int Latency = 0;
  int NumMicroOps = 12;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd13Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [13];
  int Latency = 0;
  int NumMicroOps = 13;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd14Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [14];
  int Latency = 0;
  int NumMicroOps = 14;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd15Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [15];
  int Latency = 0;
  int NumMicroOps = 15;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd16Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [16];
  int Latency = 0;
  int NumMicroOps = 16;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd17Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [17];
  int Latency = 0;
  int NumMicroOps = 17;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd18Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [18];
  int Latency = 0;
  int NumMicroOps = 18;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd19Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [19];
  int Latency = 0;
  int NumMicroOps = 19;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd1Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [1];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd20Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [20];
  int Latency = 0;
  int NumMicroOps = 20;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd21Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [21];
  int Latency = 0;
  int NumMicroOps = 21;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd22Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [22];
  int Latency = 0;
  int NumMicroOps = 22;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd23Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [23];
  int Latency = 0;
  int NumMicroOps = 23;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd24Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [24];
  int Latency = 0;
  int NumMicroOps = 24;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd25Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [25];
  int Latency = 0;
  int NumMicroOps = 25;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd26Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [26];
  int Latency = 0;
  int NumMicroOps = 26;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd27Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [27];
  int Latency = 0;
  int NumMicroOps = 27;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd28Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [28];
  int Latency = 0;
  int NumMicroOps = 28;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd29Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [29];
  int Latency = 0;
  int NumMicroOps = 29;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd2Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [2];
  int Latency = 0;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd30Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [30];
  int Latency = 0;
  int NumMicroOps = 30;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd31Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [31];
  int Latency = 0;
  int NumMicroOps = 31;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd32Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [32];
  int Latency = 0;
  int NumMicroOps = 32;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd3Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [3];
  int Latency = 0;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd4Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [4];
  int Latency = 0;
  int NumMicroOps = 4;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd5Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [5];
  int Latency = 0;
  int NumMicroOps = 5;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd6Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [6];
  int Latency = 0;
  int NumMicroOps = 6;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd7Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [7];
  int Latency = 0;
  int NumMicroOps = 7;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd8Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [8];
  int Latency = 0;
  int NumMicroOps = 8;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52ReserveLd9Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [9];
  int Latency = 0;
  int NumMicroOps = 9;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52UnitALU {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 2;
  ProcResourceKind Super = ?;
  int BufferSize = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def R52UnitB {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def R52UnitDiv {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def R52UnitFPALU {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 2;
  ProcResourceKind Super = ?;
  int BufferSize = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def R52UnitFPDIV {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def R52UnitFPMUL {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 2;
  ProcResourceKind Super = ?;
  int BufferSize = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def R52UnitLd {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def R52UnitMAC {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def R52Write2FPALU_F3 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPALU, R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52Write2FPALU_F4 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPALU, R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52Write2FPALU_F5 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPALU, R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52Write2FPMAC_F5 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPMUL, R52UnitFPMUL, R52UnitFPALU, R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52Write2FPMUL_F5 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPMUL, R52UnitFPMUL];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteALU_EX1 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteALU_EX2 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteALU_WRI {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteAdr {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteCC {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteDIV {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitDiv];
  list<int> ResourceCycles = [8];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteFPALU_F3 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteFPALU_F4 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteFPALU_F5 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteFPLd_F4 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteFPMAC_F5 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPMUL, R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteFPMUL_F5 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPMUL];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteFPST_F4 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2207, anonymous_2208, anonymous_2209, anonymous_2210, anonymous_2211, anonymous_2212, anonymous_2213, anonymous_2214, anonymous_2215, anonymous_2216, anonymous_2217, anonymous_2218, anonymous_2219, anonymous_2220, anonymous_2221, anonymous_2222];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM10Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM10CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM11Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM11CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM12Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM12CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM13Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 13;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM13CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 13;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM14Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 14;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM14CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 14;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM15Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM15CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM16Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 16;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM16CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 16;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM17Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 17;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM17CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 17;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM18Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 18;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM18CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 18;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM19Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 19;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM19CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 19;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM20Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 20;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM20CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 20;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM21Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 21;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM21CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 21;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM22Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 22;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM22CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 22;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM23Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 23;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM23CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 23;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM24Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 24;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM24CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 24;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM25Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 25;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM25CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 25;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM3Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM3CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM4Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM4CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM5Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM5CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM6Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM6CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM7Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM7CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM8Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM8CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM9Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDM9CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDMAddrNoWB {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteILDMAddrWB {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2223, anonymous_2224, anonymous_2225, anonymous_2226, anonymous_2227, anonymous_2228, anonymous_2229, anonymous_2230, anonymous_2231, anonymous_2232, anonymous_2233, anonymous_2234, anonymous_2235, anonymous_2236, anonymous_2237, anonymous_2238];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM1 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 1;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM10 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 10;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM11 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 11;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM12 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 12;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM13 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 13;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM14 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 14;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM15 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 15;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM16 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 16;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 2;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM3 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 3;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM4 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 4;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM5 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 5;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM6 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 6;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM7 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 7;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM8 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 8;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteISTM9 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [R52WriteIStIncAddr];
  int Repeat = 9;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteIStIncAddr {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM10Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM11Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM12Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM13Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 13;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM14Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 14;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM15Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM16Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 16;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM17Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 17;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM18Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 18;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM19Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 19;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM1Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM20Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 20;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM21Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 21;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM22Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 22;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM23Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 23;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM24Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 24;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM25Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 25;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM26Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 26;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM27Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 27;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM28Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 28;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM29Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 29;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM2Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM30Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 30;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM31Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 31;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM32Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 32;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM3Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM4Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM5Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM6Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM7Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM8Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLM9Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteLd {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteMAC {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitMAC];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteMACHi {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitMAC];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteNoRSRC_EX2 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteNoRSRC_WRI {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteST {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2278, anonymous_2279, anonymous_2280, anonymous_2281, anonymous_2282, anonymous_2283, anonymous_2284, anonymous_2285, anonymous_2286, anonymous_2287, anonymous_2288, anonymous_2289, anonymous_2290, anonymous_2291, anonymous_2292, anonymous_2293, anonymous_2294];
  bit Variadic = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM10 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [6];
  int Latency = 10;
  int NumMicroOps = 12;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM11 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [7];
  int Latency = 11;
  int NumMicroOps = 14;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM12 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [8];
  int Latency = 12;
  int NumMicroOps = 16;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM13 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [9];
  int Latency = 13;
  int NumMicroOps = 18;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM14 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [10];
  int Latency = 14;
  int NumMicroOps = 20;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM15 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [11];
  int Latency = 15;
  int NumMicroOps = 22;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM5 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [1];
  int Latency = 5;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM6 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [2];
  int Latency = 6;
  int NumMicroOps = 4;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM7 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [3];
  int Latency = 7;
  int NumMicroOps = 6;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM8 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [4];
  int Latency = 8;
  int NumMicroOps = 8;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteSTM9 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [5];
  int Latency = 9;
  int NumMicroOps = 10;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteVLDM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2261, anonymous_2262, anonymous_2263, anonymous_2264, anonymous_2265, anonymous_2266, anonymous_2267, anonymous_2268, anonymous_2269, anonymous_2270, anonymous_2271, anonymous_2272, anonymous_2273, anonymous_2274, anonymous_2275, anonymous_2276, anonymous_2277];
  bit Variadic = 1;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteVST1Mem {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [1];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteVST2Mem {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [2];
  int Latency = 6;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteVST3Mem {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [3];
  int Latency = 7;
  int NumMicroOps = 5;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteVST4Mem {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [4];
  int Latency = 8;
  int NumMicroOps = 7;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R52WriteVST5Mem {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [5];
  int Latency = 9;
  int NumMicroOps = 9;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def R6 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r6";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [6];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R7 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r7";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [7];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R8 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r8";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [8];
  int CostPerUse = 1;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def R9 {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "r9";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [9];
  int CostPerUse = 1;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def RBIT {	// Instruction InstTemplate Encoding InstARM I AMiscA1I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rm, pred:$p);
  string AsmString = "rbit${p}	$Rd, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (bitreverse GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ArithMiscFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def REG_SEQUENCE {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins unknown:$supersrc, variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def REV {	// Instruction InstTemplate Encoding InstARM I AMiscA1I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rm, pred:$p);
  string AsmString = "rev${p}	$Rd, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (bswap GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ArithMiscFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def REV16 {	// Instruction InstTemplate Encoding InstARM I AMiscA1I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rm, pred:$p);
  string AsmString = "rev16${p}	$Rd, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 5;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ArithMiscFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def REVSH {	// Instruction InstTemplate Encoding InstARM I AMiscA1I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rm, pred:$p);
  string AsmString = "revsh${p}	$Rd, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 5;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ArithMiscFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def RFEDA {	// Instruction InstTemplate Encoding InstARM XI RFEI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn);
  string AsmString = "rfeda	$Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def RFEDA_UPD {	// Instruction InstTemplate Encoding InstARM XI RFEI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn);
  string AsmString = "rfeda	$Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def RFEDB {	// Instruction InstTemplate Encoding InstARM XI RFEI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn);
  string AsmString = "rfedb	$Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def RFEDB_UPD {	// Instruction InstTemplate Encoding InstARM XI RFEI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn);
  string AsmString = "rfedb	$Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def RFEIA {	// Instruction InstTemplate Encoding InstARM XI RFEI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn);
  string AsmString = "rfeia	$Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def RFEIA_UPD {	// Instruction InstTemplate Encoding InstARM XI RFEI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn);
  string AsmString = "rfeia	$Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def RFEIB {	// Instruction InstTemplate Encoding InstARM XI RFEI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn);
  string AsmString = "rfeib	$Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def RFEIB_UPD {	// Instruction InstTemplate Encoding InstARM XI RFEI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn);
  string AsmString = "rfeib	$Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def RORi {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s);
  string AsmString = "ror${s}${p} $Rd, $Rm, $imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rm = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def RORr {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s);
  string AsmString = "ror${s}${p} $Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def RRX {	// Instruction InstTemplate PseudoInst UnaryDP Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rm);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, (ARMrrx GPR:$Rm))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 1;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def RRXi {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "rrx${s}${p} $Rd, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def RSBSri {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsubc mod_imm:$imm, GPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def RSBSrsi {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsubc so_reg_imm:$shift, GPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def RSBSrsr {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsubc so_reg_reg:$shift, GPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUSsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def RSBri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 0, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "rsb${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, (sub mod_imm:$imm, GPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def RSBrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "rsb${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def RSBrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "rsb${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (sub so_reg_imm:$shift, GPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def RSBrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "rsb${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (sub so_reg_reg:$shift, GPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def RSCri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 0, 1, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "rsc${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsube mod_imm:$imm, GPR:$Rn, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def RSCrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "rsc${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def RSCrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "rsc${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsube so_reg_imm:$shift, GPR:$Rn, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def RSCrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "rsc${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsube so_reg_reg:$shift, GPR:$Rn, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def ReadALU {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def ReadALUsr {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def ReadDefault {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def ReadFPMAC {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def ReadFPMUL {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def ReadMAC {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def ReadMUL {	// SchedReadWrite SchedRead
  string NAME = ?;
}
def RegListAsmOperand {	// AsmOperandClass
  string Name = "RegList";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Required {	// ReservationKind
  int Value = 0;
  string NAME = ?;
}
def Reserved {	// ReservationKind
  int Value = 1;
  string NAME = ?;
}
def RetCC_ARM_AAPCS {	// CallingConv
  list<CCAction> Actions = [anonymous_3086, anonymous_3087, anonymous_3020, anonymous_3023, anonymous_3092, anonymous_3031, anonymous_3093];
  bit Custom = 0;
  string NAME = ?;
}
def RetCC_ARM_AAPCS_Common {	// CallingConv
  list<CCAction> Actions = [anonymous_3017, anonymous_3033, anonymous_3043];
  bit Custom = 0;
  string NAME = ?;
}
def RetCC_ARM_AAPCS_VFP {	// CallingConv
  list<CCAction> Actions = [anonymous_3086, anonymous_3087, anonymous_3020, anonymous_3023, anonymous_3045, anonymous_3047, anonymous_3049, anonymous_3093];
  bit Custom = 0;
  string NAME = ?;
}
def RetCC_ARM_APCS {	// CallingConv
  list<CCAction> Actions = [anonymous_3017, anonymous_3031, anonymous_3020, anonymous_3023, anonymous_3025, anonymous_3027, anonymous_3041, anonymous_3033, anonymous_3043];
  bit Custom = 0;
  string NAME = ?;
}
def RetFastCC_ARM_APCS {	// CallingConv
  list<CCAction> Actions = [anonymous_3025, anonymous_3027, anonymous_3045, anonymous_3047, anonymous_3049, anonymous_3057];
  bit Custom = 0;
  string NAME = ?;
}
def RotImmAsmOperand {	// AsmOperandClass
  string Name = "RotImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseRotImm";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def S0 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s0";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S1 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s1";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S10 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s10";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S11 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s11";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S12 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s12";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S13 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s13";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S14 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s14";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S15 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s15";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S16 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s16";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S17 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s17";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S18 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s18";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S19 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s19";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S2 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s2";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S20 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s20";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S21 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s21";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S22 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s22";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S23 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s23";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S24 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s24";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S25 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s25";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S26 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s26";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S27 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s27";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S28 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s28";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S29 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s29";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S3 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s3";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S30 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s30";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S31 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s31";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S4 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s4";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S5 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s5";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S6 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s6";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S7 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s7";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S8 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s8";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def S9 {	// Register ARMFReg
  string Namespace = "ARM";
  string AsmName = "s9";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 0;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def SADD16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "sadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_sadd16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SADD8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "sadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_sadd8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SASX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "sasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_sasx GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SBCri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 0, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "sbc${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsube GPR:$Rn, mod_imm:$imm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SBCrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "sbc${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsube GPR:$Rn, GPR:$Rm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SBCrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "sbc${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsube GPR:$Rn, so_reg_imm:$shift, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SBCrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "sbc${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPRnopc:$Rd, CPSR, (ARMsube GPRnopc:$Rn, so_reg_reg:$shift, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SBFX {	// Instruction InstTemplate Encoding InstARM I Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 1, 0, 1, width{4}, width{3}, width{2}, width{1}, width{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, lsb{4}, lsb{3}, lsb{2}, lsb{1}, lsb{0}, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width, pred:$p);
  string AsmString = "sbfx${p}	$Rd, $Rn, $lsb, $width";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAsi;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<5> lsb = { ?, ?, ?, ?, ? };
  bits<5> width = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SDIV {	// Instruction InstTemplate Encoding InstARM I ADivA1I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 0, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "sdiv${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasDivideInARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iDIV;
  list<SchedReadWrite> SchedRW = [WriteDIV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ArithMiscFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SDNPAssociative {	// SDNodeProperty
  string NAME = ?;
}
def SDNPCommutative {	// SDNodeProperty
  string NAME = ?;
}
def SDNPHasChain {	// SDNodeProperty
  string NAME = ?;
}
def SDNPInGlue {	// SDNodeProperty
  string NAME = ?;
}
def SDNPMayLoad {	// SDNodeProperty
  string NAME = ?;
}
def SDNPMayStore {	// SDNodeProperty
  string NAME = ?;
}
def SDNPMemOperand {	// SDNodeProperty
  string NAME = ?;
}
def SDNPOptInGlue {	// SDNodeProperty
  string NAME = ?;
}
def SDNPOutGlue {	// SDNodeProperty
  string NAME = ?;
}
def SDNPSideEffect {	// SDNodeProperty
  string NAME = ?;
}
def SDNPVariadic {	// SDNodeProperty
  string NAME = ?;
}
def SDNPWantParent {	// SDNodeProperty
  string NAME = ?;
}
def SDNPWantRoot {	// SDNodeProperty
  string NAME = ?;
}
def SDTARMVCMP {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_849];
  string NAME = ?;
}
def SDTARMVCMPZ {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [];
  string NAME = ?;
}
def SDTARMVEXT {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_834, anonymous_835, anonymous_3099];
  string NAME = ?;
}
def SDTARMVGETLN {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_839, anonymous_3098];
  string NAME = ?;
}
def SDTARMVMOVIMM {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_3097];
  string NAME = ?;
}
def SDTARMVMULL {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_839, anonymous_849];
  string NAME = ?;
}
def SDTARMVORRIMM {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_834, anonymous_3098];
  string NAME = ?;
}
def SDTARMVSH {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_834, anonymous_3098];
  string NAME = ?;
}
def SDTARMVSHINS {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_834, anonymous_835, anonymous_3099];
  string NAME = ?;
}
def SDTARMVSHUF {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_834];
  string NAME = ?;
}
def SDTARMVSHUF2 {	// SDTypeProfile
  int NumResults = 2;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_834, anonymous_835, anonymous_837];
  string NAME = ?;
}
def SDTARMVSHX {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_839, anonymous_3098];
  string NAME = ?;
}
def SDTARMVTBL1 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_3886, anonymous_3887, anonymous_3888];
  string NAME = ?;
}
def SDTARMVTBL2 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_3886, anonymous_3887, anonymous_3888, anonymous_3889];
  string NAME = ?;
}
def SDTAtomic2 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_835, anonymous_830, anonymous_855];
  string NAME = ?;
}
def SDTAtomic3 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_835, anonymous_837, anonymous_830, anonymous_855];
  string NAME = ?;
}
def SDTAtomicFence {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_832];
  string NAME = ?;
}
def SDTAtomicLoad {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_855];
  string NAME = ?;
}
def SDTAtomicStore {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_832, anonymous_839];
  string NAME = ?;
}
def SDTBinaryArithWithFlags {	// SDTypeProfile
  int NumResults = 2;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_835, anonymous_837, anonymous_830, anonymous_3097];
  string NAME = ?;
}
def SDTBinaryArithWithFlagsInOut {	// SDTypeProfile
  int NumResults = 2;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_835, anonymous_837, anonymous_830, anonymous_3097, anonymous_3100];
  string NAME = ?;
}
def SDTBr {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_833];
  string NAME = ?;
}
def SDTBrCC {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 4;
  list<SDTypeConstraint> Constraints = [anonymous_833, anonymous_849, anonymous_850];
  string NAME = ?;
}
def SDTBrcond {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_854];
  string NAME = ?;
}
def SDTBrind {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_832];
  string NAME = ?;
}
def SDTCatchret {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_833, anonymous_854];
  string NAME = ?;
}
def SDTConvertOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 5;
  list<SDTypeConstraint> Constraints = [anonymous_844, anonymous_850, anonymous_861, anonymous_871];
  string NAME = ?;
}
def SDTExtInreg {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_830, anonymous_844, anonymous_845];
  string NAME = ?;
}
def SDTExtInvec {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_846, anonymous_839, anonymous_847, anonymous_840, anonymous_848];
  string NAME = ?;
}
def SDTFPBinOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_835, anonymous_831];
  string NAME = ?;
}
def SDTFPExtendOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_831, anonymous_843, anonymous_840, anonymous_841];
  string NAME = ?;
}
def SDTFPLeaf {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 0;
  list<SDTypeConstraint> Constraints = [anonymous_831];
  string NAME = ?;
}
def SDTFPRoundOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_831, anonymous_843, anonymous_842, anonymous_841];
  string NAME = ?;
}
def SDTFPSignOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_831, anonymous_838];
  string NAME = ?;
}
def SDTFPTernaryOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_835, anonymous_837, anonymous_831];
  string NAME = ?;
}
def SDTFPToIntOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_843, anonymous_841];
  string NAME = ?;
}
def SDTFPUnaryOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_831];
  string NAME = ?;
}
def SDTIStore {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_835, anonymous_832, anonymous_856];
  string NAME = ?;
}
def SDTIntBinHiLoOp {	// SDTypeProfile
  int NumResults = 2;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_835, anonymous_837, anonymous_830];
  string NAME = ?;
}
def SDTIntBinOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_835, anonymous_830];
  string NAME = ?;
}
def SDTIntExtendOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_839, anonymous_840, anonymous_841];
  string NAME = ?;
}
def SDTIntLeaf {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 0;
  list<SDTypeConstraint> Constraints = [anonymous_830];
  string NAME = ?;
}
def SDTIntSatNoShOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_836];
  string NAME = ?;
}
def SDTIntShiftOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_830, anonymous_836];
  string NAME = ?;
}
def SDTIntToFPOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_831, anonymous_839, anonymous_841];
  string NAME = ?;
}
def SDTIntTruncOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_839, anonymous_842, anonymous_841];
  string NAME = ?;
}
def SDTIntUnaryOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_830];
  string NAME = ?;
}
def SDTLoad {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_855];
  string NAME = ?;
}
def SDTMaskedGather {	// SDTypeProfile
  int NumResults = 2;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_847, anonymous_835, anonymous_860, anonymous_861, anonymous_862, anonymous_841];
  string NAME = ?;
}
def SDTMaskedLoad {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_855, anonymous_857, anonymous_837, anonymous_859];
  string NAME = ?;
}
def SDTMaskedScatter {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_847, anonymous_835, anonymous_841, anonymous_863, anonymous_856];
  string NAME = ?;
}
def SDTMaskedStore {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_832, anonymous_847, anonymous_857, anonymous_858];
  string NAME = ?;
}
def SDTMemBarrier {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 5;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_835, anonymous_837, anonymous_870, anonymous_830];
  string NAME = ?;
}
def SDTNone {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 0;
  list<SDTypeConstraint> Constraints = [];
  string NAME = ?;
}
def SDTOther {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 0;
  list<SDTypeConstraint> Constraints = [anonymous_833];
  string NAME = ?;
}
def SDTPrefetch {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 4;
  list<SDTypeConstraint> Constraints = [anonymous_832, anonymous_849, anonymous_860, anonymous_839];
  string NAME = ?;
}
def SDTPtrLeaf {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 0;
  list<SDTypeConstraint> Constraints = [anonymous_832];
  string NAME = ?;
}
def SDTSelect {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_839, anonymous_835, anonymous_851];
  string NAME = ?;
}
def SDTSelectCC {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 5;
  list<SDTypeConstraint> Constraints = [anonymous_849, anonymous_852, anonymous_837, anonymous_853];
  string NAME = ?;
}
def SDTSetCC {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_849, anonymous_850];
  string NAME = ?;
}
def SDTStore {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_855];
  string NAME = ?;
}
def SDTSubVecExtract {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_867, anonymous_836];
  string NAME = ?;
}
def SDTSubVecInsert {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_868, anonymous_834, anonymous_869];
  string NAME = ?;
}
def SDTUNDEF {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 0;
  list<SDTypeConstraint> Constraints = [];
  string NAME = ?;
}
def SDTUnaryOp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [];
  string NAME = ?;
}
def SDTVSelect {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_839, anonymous_835, anonymous_851, anonymous_841];
  string NAME = ?;
}
def SDTVecExtract {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_864, anonymous_865];
  string NAME = ?;
}
def SDTVecInsert {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_866, anonymous_834, anonymous_856];
  string NAME = ?;
}
def SDTVecShuffle {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_849];
  string NAME = ?;
}
def SDT_ARMAnd {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_3097, anonymous_3098];
  string NAME = ?;
}
def SDT_ARMBCC_i64 {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 6;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_3097, anonymous_3098, anonymous_3099, anonymous_3100, anonymous_853];
  string NAME = ?;
}
def SDT_ARMBFI {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_3097, anonymous_3098, anonymous_3099];
  string NAME = ?;
}
def SDT_ARMBr2JT {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_832, anonymous_3097, anonymous_3098];
  string NAME = ?;
}
def SDT_ARMBrJT {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_832, anonymous_3097];
  string NAME = ?;
}
def SDT_ARMBrcond {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_833, anonymous_3097];
  string NAME = ?;
}
def SDT_ARMCMov {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_835, anonymous_3099];
  string NAME = ?;
}
def SDT_ARMCallSeqEnd {	// SDTypeProfile SDCallSeqEnd
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_3097];
  string NAME = ?;
}
def SDT_ARMCallSeqStart {	// SDTypeProfile SDCallSeqStart
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_3097];
  string NAME = ?;
}
def SDT_ARMCmp {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834];
  string NAME = ?;
}
def SDT_ARMEH_SJLJ_Longjmp {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_832, anonymous_839];
  string NAME = ?;
}
def SDT_ARMEH_SJLJ_Setjmp {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_855, anonymous_836];
  string NAME = ?;
}
def SDT_ARMEH_SJLJ_SetupDispatch {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 0;
  list<SDTypeConstraint> Constraints = [];
  string NAME = ?;
}
def SDT_ARMFCmp {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_3098];
  string NAME = ?;
}
def SDT_ARMMEMBARRIER {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_830];
  string NAME = ?;
}
def SDT_ARMMEMCPY {	// SDTypeProfile
  int NumResults = 2;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_3097, anonymous_3098, anonymous_3099, anonymous_3100];
  string NAME = ?;
}
def SDT_ARMPICAdd {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_855, anonymous_3098];
  string NAME = ?;
}
def SDT_ARMPREFETCH {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_832, anonymous_849, anonymous_839];
  string NAME = ?;
}
def SDT_ARMSaveCallPC {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [];
  string NAME = ?;
}
def SDT_ARMStructByVal {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 4;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_3097, anonymous_3098, anonymous_3099];
  string NAME = ?;
}
def SDT_ARMTCRET {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_832];
  string NAME = ?;
}
def SDT_ARMThreadPointer {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 0;
  list<SDTypeConstraint> Constraints = [anonymous_832];
  string NAME = ?;
}
def SDT_ARMcall {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = -1;
  list<SDTypeConstraint> Constraints = [anonymous_832];
  string NAME = ?;
}
def SDT_CMPFP0 {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_831, anonymous_3097];
  string NAME = ?;
}
def SDT_LongMac {	// SDTypeProfile
  int NumResults = 2;
  int NumOperands = 4;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_834, anonymous_835, anonymous_837, anonymous_870, anonymous_3101];
  string NAME = ?;
}
def SDT_MulHSR {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_834, anonymous_835, anonymous_837];
  string NAME = ?;
}
def SDT_VMOVDRR {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_3712, anonymous_3097, anonymous_849];
  string NAME = ?;
}
def SDT_VMOVRRD {	// SDTypeProfile
  int NumResults = 2;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_834, anonymous_3713];
  string NAME = ?;
}
def SDT_VMOVSR {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_3714, anonymous_3097];
  string NAME = ?;
}
def SDT_VMOVhr {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_831, anonymous_3097];
  string NAME = ?;
}
def SDT_VMOVrh {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_3096, anonymous_843];
  string NAME = ?;
}
def SDT_WIN__DBZCHK {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_3096];
  string NAME = ?;
}
def SDT_assertext {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_830, anonymous_839, anonymous_881];
  string NAME = ?;
}
def SEL {	// Instruction InstTemplate Encoding InstARM I AI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "sel${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SETEND {	// Instruction InstTemplate Encoding InstARM XI AXI Requires Deprecated
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, end{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins setend_op:$end);
  string AsmString = "setend	$end";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  SubtargetFeature DeprecatedFeatureMask = HasV8Ops;
  bits<1> end = { ? };
  string NAME = ?;
}
def SETEQ {	// CondCode
  string NAME = ?;
}
def SETGE {	// CondCode
  string NAME = ?;
}
def SETGT {	// CondCode
  string NAME = ?;
}
def SETLE {	// CondCode
  string NAME = ?;
}
def SETLT {	// CondCode
  string NAME = ?;
}
def SETNE {	// CondCode
  string NAME = ?;
}
def SETO {	// CondCode
  string NAME = ?;
}
def SETOEQ {	// CondCode
  string NAME = ?;
}
def SETOGE {	// CondCode
  string NAME = ?;
}
def SETOGT {	// CondCode
  string NAME = ?;
}
def SETOLE {	// CondCode
  string NAME = ?;
}
def SETOLT {	// CondCode
  string NAME = ?;
}
def SETONE {	// CondCode
  string NAME = ?;
}
def SETPAN {	// Instruction InstTemplate Encoding InstARM InoP AInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, imm{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_1:$imm);
  string AsmString = "setpan	$imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV8, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> imm = { ? };
  string NAME = ?;
}
def SETUEQ {	// CondCode
  string NAME = ?;
}
def SETUGE {	// CondCode
  string NAME = ?;
}
def SETUGT {	// CondCode
  string NAME = ?;
}
def SETULE {	// CondCode
  string NAME = ?;
}
def SETULT {	// CondCode
  string NAME = ?;
}
def SETUNE {	// CondCode
  string NAME = ?;
}
def SETUO {	// CondCode
  string NAME = ?;
}
def SHA1C {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQInt3np Requires N3SHA3Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vn, QPR:$Vm);
  string AsmString = "sha1c.32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (null_frag (v4i32 QPR:$src), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHA1H {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntXnp Requires N2SHA
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "sha1h.32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (null_frag (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHA1M {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQInt3np Requires N3SHA3Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vn, QPR:$Vm);
  string AsmString = "sha1m.32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (null_frag (v4i32 QPR:$src), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHA1P {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQInt3np Requires N3SHA3Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vn, QPR:$Vm);
  string AsmString = "sha1p.32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (null_frag (v4i32 QPR:$src), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHA1SU0 {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQInt3np Requires N3SHA3Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vn, QPR:$Vm);
  string AsmString = "sha1su0.32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_sha1su0 (v4i32 QPR:$src), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHA1SU1 {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntX2np Requires N2SHA2Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vm);
  string AsmString = "sha1su1.32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_sha1su1 (v4i32 QPR:$src), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHA256H {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQInt3np Requires N3SHA3Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vn, QPR:$Vm);
  string AsmString = "sha256h.32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_sha256h (v4i32 QPR:$src), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHA256H2 {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQInt3np Requires N3SHA3Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vn, QPR:$Vm);
  string AsmString = "sha256h2.32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_sha256h2 (v4i32 QPR:$src), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHA256SU0 {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntX2np Requires N2SHA2Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vm);
  string AsmString = "sha256su0.32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_sha256su0 (v4i32 QPR:$src), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHA256SU1 {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQInt3np Requires N3SHA3Op
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src, QPR:$Vn, QPR:$Vm);
  string AsmString = "sha256su1.32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_sha256su1 (v4i32 QPR:$src), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "v8Crypto";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SHADD16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "shadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_shadd16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SHADD8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "shadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_shadd8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SHASX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "shasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_shasx GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SHSAX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "shsax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_shsax GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SHSUB16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "shsub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_shsub16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SHSUB8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "shsub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_shsub8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMC {	// Instruction InstTemplate Encoding InstARM I ABI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, opt{3}, opt{2}, opt{1}, opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_15:$opt, pred:$p);
  string AsmString = "smc${p}	$opt";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasTrustZone];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLABB {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI AMulxyIa Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smlabb${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16), (sext_inreg GPRnopc:$Rm, i16))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSMLAInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLABT {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI AMulxyIa Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smlabt${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16), (sra GPRnopc:$Rm, (i32 16)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSMLAInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLAD {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualIa Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smlad${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLADX {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualIa Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smladx${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLAL {	// Instruction InstTemplate Encoding InstARM sI AsMul1I AsMla1I64 RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 1, 1, s{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$RdLo, GPR:$RdHi);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s);
  string AsmString = "smlal${s}${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLALBB {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI64 RegConstraint Requires Sched SMLAL
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$RdLo, GPRnopc:$RdHi);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi, pred:$p);
  string AsmString = "smlalbb${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLALBT {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI64 RegConstraint Requires Sched SMLAL
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$RdLo, GPRnopc:$RdHi);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi, pred:$p);
  string AsmString = "smlalbt${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLALD {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualI64 RegConstraint Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$RdLo, GPRnopc:$RdHi);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi, pred:$p);
  string AsmString = "smlald${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLALDX {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualI64 RegConstraint Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$RdLo, GPRnopc:$RdHi);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi, pred:$p);
  string AsmString = "smlaldx${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLALTB {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI64 RegConstraint Requires Sched SMLAL
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$RdLo, GPRnopc:$RdHi);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi, pred:$p);
  string AsmString = "smlaltb${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLALTT {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI64 RegConstraint Requires Sched SMLAL
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$RdLo, GPRnopc:$RdHi);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi, pred:$p);
  string AsmString = "smlaltt${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLALv5 {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$RdLo, GPR:$RdHi);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, NoV6];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s);
  string NAME = ?;
}
def SMLATB {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI AMulxyIa Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smlatb${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), (sext_inreg GPRnopc:$Rm, i16))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSMLAInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLATT {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI AMulxyIa Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smlatt${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), (sra GPRnopc:$Rm, (i32 16)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSMLAInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLAWB {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI AMulxyIa Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smlawb${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSMLAInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLAWT {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI AMulxyIa Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smlawt${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSMLAInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLSD {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualIa Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smlsd${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLSDX {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualIa Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smlsdx${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLSLD {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualI64 RegConstraint Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$RdLo, GPRnopc:$RdHi);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi, pred:$p);
  string AsmString = "smlsld${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMLSLDX {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualI64 RegConstraint Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$RdLo, GPRnopc:$RdHi);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi, pred:$p);
  string AsmString = "smlsldx${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMMLA {	// Instruction InstTemplate Encoding InstARM I AMul2I AMul2Ia Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smmla${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMMLAR {	// Instruction InstTemplate Encoding InstARM I AMul2I AMul2Ia Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smmlar${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMMLS {	// Instruction InstTemplate Encoding InstARM I AMul2I AMul2Ia Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smmls${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMMLSR {	// Instruction InstTemplate Encoding InstARM I AMul2I AMul2Ia Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "smmlsr${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMMUL {	// Instruction InstTemplate Encoding InstARM I AMul2I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "smmul${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL32;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMMULR {	// Instruction InstTemplate Encoding InstARM I AMul2I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 1, 0, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "smmulr${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL32;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMUAD {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "smuad${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMUADX {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "smuadx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMULBB {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "smulbb${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), (sext_inreg GPR:$Rm, i16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMULBT {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "smulbt${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), (sra GPR:$Rm, (i32 16))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMULL {	// Instruction InstTemplate Encoding InstARM sI AsMul1I AsMul1I64 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 1, 0, s{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$RdLo, GPR:$RdHi);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "smull${s}${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$RdLo, GPR:$RdHi, (smullohi GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL64;
  list<SchedReadWrite> SchedRW = [WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMULLv5 {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$RdLo, GPR:$RdHi);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$RdLo, GPR:$RdHi, (smullohi GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, NoV6];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL64;
  list<SchedReadWrite> SchedRW = [WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL];
  string Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string NAME = ?;
}
def SMULTB {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "smultb${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), (sext_inreg GPR:$Rm, i16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMULTT {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "smultt${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), (sra GPR:$Rm, (i32 16))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMULWB {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "smulwb${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMULWT {	// Instruction InstTemplate Encoding InstARM I AMulxyIbase AMulxyI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ?, ?, ?, ?, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "smulwt${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMUSD {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "smusd${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SMUSDX {	// Instruction InstTemplate Encoding InstARM I AI Requires AMulDualIbase AMulDualI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "smusdx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def SP {	// Register ARMReg DwarfRegNum
  string Namespace = "ARM";
  string AsmName = "sp";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [13];
  int CostPerUse = 1;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1 };
  bit isArtificial = 0;
  string NAME = ?;
}
def SPACE {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins i32imm:$size, GPR:$Rn);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def SPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [f32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (sequence "S%u", 0, 31);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(add (decimate SPR, 2), SPR), (add (decimate SPR, 4), (decimate SPR, 2), (decimate (rotl SPR, 1), 4), (decimate (rotl SPR, 1), 2))];
  code AltOrderSelect = [{
    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
  }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [s0, s31]";
  string NAME = ?;
}
def SPRRegListAsmOperand {	// AsmOperandClass
  string Name = "SPRRegList";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a list of registers in range [s0, s31]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def SPR_8 {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [f32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (sequence "S%u", 0, 15);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [s0, s15]";
  string NAME = ?;
}
def SPSR {	// Register ARMReg
  string Namespace = "ARM";
  string AsmName = "spsr";
  list<string> AltNames = [];
  list<Register> Aliases = [];
  list<Register> SubRegs = [];
  list<SubRegIndex> SubRegIndices = [];
  list<RegAltNameIndex> RegAltNameIndices = [];
  list<int> DwarfNumbers = [];
  int CostPerUse = 0;
  bit CoveredBySubRegs = 1;
  bits<16> HWEncoding = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bit isArtificial = 0;
  string NAME = ?;
}
def SRSDA {	// Instruction InstTemplate Encoding InstARM XI SRSI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "srsda	sp, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SRSDA_UPD {	// Instruction InstTemplate Encoding InstARM XI SRSI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "srsda	sp!, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SRSDB {	// Instruction InstTemplate Encoding InstARM XI SRSI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "srsdb	sp, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SRSDB_UPD {	// Instruction InstTemplate Encoding InstARM XI SRSI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "srsdb	sp!, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SRSIA {	// Instruction InstTemplate Encoding InstARM XI SRSI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "srsia	sp, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SRSIA_UPD {	// Instruction InstTemplate Encoding InstARM XI SRSI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "srsia	sp!, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SRSIB {	// Instruction InstTemplate Encoding InstARM XI SRSI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "srsib	sp, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SRSIB_UPD {	// Instruction InstTemplate Encoding InstARM XI SRSI
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "srsib	sp!, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SSAT {	// Instruction InstTemplate Encoding InstARM I AI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 1, sat_imm{4}, sat_imm{3}, sat_imm{2}, sat_imm{1}, sat_imm{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{4}, sh{3}, sh{2}, sh{1}, sh{0}, sh{5}, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh, pred:$p);
  string AsmString = "ssat${p}	$Rd, $sat_imm, $Rn$sh";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = SatFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<5> sat_imm = { ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<8> sh = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SSAT16 {	// Instruction InstTemplate Encoding InstARM I AI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 1, 0, sat_imm{3}, sat_imm{2}, sat_imm{1}, sat_imm{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins imm1_16:$sat_imm, GPRnopc:$Rn, pred:$p);
  string AsmString = "ssat16${p}	$Rd, $sat_imm, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = SatFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> sat_imm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def SSAX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "ssax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_ssax GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SSUB16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "ssub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_ssub16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SSUB8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "ssub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_ssub8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SSubReg_f32_reg {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
  return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def STACKMAP {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def STATEPOINT {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs);
  dag InOperandList = (ins variable_ops);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def STC2L_OFFSET {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 1, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr);
  string AsmString = "stc2l	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC2L_OPTION {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option);
  string AsmString = "stc2l	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC2L_POST {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, offset{8}, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset);
  string AsmString = "stc2l	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC2L_PRE {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 1, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr);
  string AsmString = "stc2l	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC2_OFFSET {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 0, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr);
  string AsmString = "stc2	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC2_OPTION {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option);
  string AsmString = "stc2	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC2_POST {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, offset{8}, 0, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset);
  string AsmString = "stc2	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC2_PRE {	// Instruction InstTemplate Encoding InstARM InoP ACInoP Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 0, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr);
  string AsmString = "stc2	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STCL_OFFSET {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, 1, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "stcl${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STCL_OPTION {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "stcl${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STCL_POST {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, offset{8}, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "stcl${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STCL_PRE {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, 1, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "stcl${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC_OFFSET {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, 0, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "stc${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC_OPTION {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "stc${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC_POST {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, offset{8}, 0, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "stc${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STC_PRE {	// Instruction InstTemplate Encoding InstARM I ACI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, 0, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "stc${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STL {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel Requires AIstrrel
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stl${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STLB {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel Requires AIstrrel
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlb${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STLEX {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel Requires AIstlex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 0, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlex${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rd, (stlex_4 GPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STLEXB {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel Requires AIstlex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 0, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlexb${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rd, (stlex_1 GPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STLEXD {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel Requires AIstlex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 0, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPRPairOp:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlexd${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeDoubleRegStore";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STLEXH {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel Requires AIstlex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 0, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlexh${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rd, (stlex_2 GPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STLH {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel Requires AIstrrel
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlh${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STMDA {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmda${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMStore";
  string NAME = ?;
}
def STMDA_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmda${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMStore";
  string NAME = ?;
}
def STMDB {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmdb${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMStore";
  string NAME = ?;
}
def STMDB_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmdb${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMStore";
  string NAME = ?;
}
def STMIA {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stm${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMStore";
  string NAME = ?;
}
def STMIA_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stm${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMStore";
  string NAME = ?;
}
def STMIB {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmib${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMStore";
  string NAME = ?;
}
def STMIB_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4 ComplexDeprecationPredicate
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmib${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "ARMStore";
  string NAME = ?;
}
def STRBT_POST {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$q);
  string AsmString = "strbt${q} $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def STRBT_POST_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 0, offset{12}, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset, pred:$p);
  string AsmString = "strbt${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRBT_POST_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, offset{12}, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, 0, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset, pred:$p);
  string AsmString = "strbt${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRB_POST_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 0, offset{12}, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset, pred:$p);
  string AsmString = "strb${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_iu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRB_POST_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, offset{12}, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, 0, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset, pred:$p);
  string AsmString = "strb${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRB_PRE_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 1, addr{12}, 1, 1, 0, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addrmode_imm12_pre:$addr, pred:$p);
  string AsmString = "strb${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_iu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSTRPreImm";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STRB_PRE_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, addr{12}, 1, 1, 0, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, 0, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, ldst_so_reg:$addr, pred:$p);
  string AsmString = "strb${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSTRPreReg";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STRBi12 {	// Instruction InstTemplate Encoding InstARM I AI2ldst
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 1, addr{12}, 1, 0, 0, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rt, addrmode_imm12:$addr, pred:$p);
  string AsmString = "strb${p}	$Rt, $addr";
  list<dag> Pattern = [(truncstorei8 GPRnopc:$Rt, addrmode_imm12:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STRBi_preidx {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def STRBr_preidx {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def STRBrs {	// Instruction InstTemplate Encoding InstARM I AI2ldst
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, shift{12}, 1, 0, 0, shift{16}, shift{15}, shift{14}, shift{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rt, ldst_so_reg:$shift, pred:$p);
  string AsmString = "strb${p}	$Rt, $shift";
  list<dag> Pattern = [(truncstorei8 GPRnopc:$Rt, ldst_so_reg:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_si;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, 0, ?, ?, ?, ? };
  string NAME = ?;
}
def STRD {	// Instruction InstTemplate Encoding InstARM I AI3str Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr, pred:$p);
  string AsmString = "strd${p}	$Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_d_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = StMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRD_POST {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, offset{9}, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 1, 1, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, am3offset:$offset, pred:$p);
  string AsmString = "strd${p}	$Rt, $Rt2, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_d_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRD_PRE {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr, pred:$p);
  string AsmString = "strd${p}	$Rt, $Rt2, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_d_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = StMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STREX {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel AIstrex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "strex${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STREXB {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel AIstrex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "strexb${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STREXD {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel AIstrex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 0, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPRPairOp:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "strexd${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeDoubleRegStore";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STREXH {	// Instruction InstTemplate Encoding InstARM I AIstr_ex_or_rel AIstrex
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 1, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "strexh${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStExFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRH {	// Instruction InstTemplate Encoding InstARM I AI3str
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, addrmode3:$addr, pred:$p);
  string AsmString = "strh${p}	$Rt, $addr";
  list<dag> Pattern = [(truncstorei16 GPR:$Rt, addrmode3:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = StMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRHTi {	// Instruction InstTemplate Encoding InstARM I AI3ldstidxT
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 0, 1, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$base_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset, pred:$p);
  string AsmString = "strht${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $base_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STRHTr {	// Instruction InstTemplate Encoding InstARM I AI3ldstidxT
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, Rm{4}, 0, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 1, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$base_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm, pred:$p);
  string AsmString = "strht${p}	$Rt, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $base_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<5> Rm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STRH_POST {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, offset{8}, offset{9}, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{7}, offset{6}, offset{5}, offset{4}, 1, 0, 1, 1, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset, pred:$p);
  string AsmString = "strh${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, addr_offset_none:$addr, am3offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRH_PRE {	// Instruction InstTemplate Encoding InstARM I AI3ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, addr{8}, addr{13}, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, 1, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addrmode3_pre:$addr, pred:$p);
  string AsmString = "strh${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode3;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = StMiscFrm;
  bits<6> Form = { 0, 0, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STRH_preidx {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rn_wb, (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def STRT_POST {	// Instruction InstTemplate AsmPseudoInst Requires ARMAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, pred:$q);
  string AsmString = "strt${q} $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def STRT_POST_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 0, offset{12}, 0, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset, pred:$p);
  string AsmString = "strt${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STRT_POST_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, offset{12}, 0, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, 0, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset, pred:$p);
  string AsmString = "strt${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STR_POST_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 0, offset{12}, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset, pred:$p);
  string AsmString = "str${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_iu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STR_POST_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, offset{12}, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, offset{11}, offset{10}, offset{9}, offset{8}, offset{7}, offset{6}, offset{5}, 0, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset, pred:$p);
  string AsmString = "str${p}	$Rt, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeAddrMode2IdxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<14> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def STR_PRE_IMM {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 1, addr{12}, 0, 1, 0, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, addrmode_imm12_pre:$addr, pred:$p);
  string AsmString = "str${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_iu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSTRPreImm";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STR_PRE_REG {	// Instruction InstTemplate Encoding InstARM I AI2ldstidx
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, addr{12}, 0, 1, 0, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, 0, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, ldst_so_reg:$addr, pred:$p);
  string AsmString = "str${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSTRPreReg";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode2;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STRi12 {	// Instruction InstTemplate Encoding InstARM I AI2ldst
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 0, 1, addr{12}, 0, 0, 0, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, addrmode_imm12:$addr, pred:$p);
  string AsmString = "str${p}	$Rt, $addr";
  list<dag> Pattern = [(store GPR:$Rt, addrmode_imm12:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def STRi_preidx {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rn_wb, (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def STRr_preidx {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rn_wb);
  dag InOperandList = (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rn_wb, (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def STRrs {	// Instruction InstTemplate Encoding InstARM I AI2ldst
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, shift{12}, 0, 0, 0, shift{16}, shift{15}, shift{14}, shift{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, ldst_so_reg:$shift, pred:$p);
  string AsmString = "str${p}	$Rt, $shift";
  list<dag> Pattern = [(store GPR:$Rt, ldst_so_reg:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_si;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = StFrm;
  bits<6> Form = { 0, 0, 0, 1, 1, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, 0, ?, ?, ?, ? };
  string NAME = ?;
}
def SUBREG_TO_REG {	// Instruction StandardPseudoInstruction
  string Namespace = "TargetOpcode";
  dag OutOperandList = (outs unknown:$dst);
  dag InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 0;
  bit mayStore = 0;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 1;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  string NAME = ?;
}
def SUBS_PC_LR {	// Instruction InstTemplate PseudoInst ARMPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(ARMintretflag imm:$offset)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def SUBSri {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsubc GPR:$Rn, mod_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def SUBSrr {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsubc GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def SUBSrsi {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsubc GPR:$Rn, so_reg_imm:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def SUBSrsr {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$Rd, CPSR, (ARMsubc GPR:$Rn, so_reg_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUSsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def SUBri {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 0, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "sub${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPR:$Rd, (sub GPR:$Rn, mod_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SUBrr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "sub${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (sub GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def SUBrsi {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s);
  string AsmString = "sub${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (sub GPR:$Rn, so_reg_imm:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SUBrsr {	// Instruction InstTemplate Encoding InstARM sI AsI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s);
  string AsmString = "sub${s}${p}	$Rd, $Rn, $shift";
  list<dag> Pattern = [(set GPR:$Rd, (sub GPR:$Rn, so_reg_reg:$shift))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsr;
  list<SchedReadWrite> SchedRW = [WriteALUsr, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Rn = $Rd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SVC {	// Instruction InstTemplate Encoding InstARM I ABI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 1, svc{23}, svc{22}, svc{21}, svc{20}, svc{19}, svc{18}, svc{17}, svc{16}, svc{15}, svc{14}, svc{13}, svc{12}, svc{11}, svc{10}, svc{9}, svc{8}, svc{7}, svc{6}, svc{5}, svc{4}, svc{3}, svc{2}, svc{1}, svc{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm24b:$svc, pred:$p);
  string AsmString = "svc${p}	$svc";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = BrFrm;
  bits<6> Form = { 0, 0, 0, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<24> svc = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def SWP {	// Instruction InstTemplate Encoding InstARM I AI AIswp Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 1, 0, 0, 1, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins GPRnopc:$Rt2, addr_offset_none:$addr, pred:$p);
  string AsmString = "swp${p}	$Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSwap";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def SWPB {	// Instruction InstTemplate Encoding InstARM I AI AIswp Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 1, 0, 0, 1, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins GPRnopc:$Rt2, addr_offset_none:$addr, pred:$p);
  string AsmString = "swpb${p}	$Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, PreV8];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeSwap";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def SW_ALU0 {	// FuncUnit
  string NAME = ?;
}
def SW_ALU1 {	// FuncUnit
  string NAME = ?;
}
def SW_DIS0 {	// FuncUnit
  string NAME = ?;
}
def SW_DIS1 {	// FuncUnit
  string NAME = ?;
}
def SW_DIS2 {	// FuncUnit
  string NAME = ?;
}
def SW_FDIV {	// FuncUnit
  string NAME = ?;
}
def SW_IDIV {	// FuncUnit
  string NAME = ?;
}
def SW_LS {	// FuncUnit
  string NAME = ?;
}
def SXTAB {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_exta_rrot
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtab${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [(set GPRnopc:$Rd, (anonymous_3156 GPR:$Rn, (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAr;
  list<SchedReadWrite> SchedRW = [WriteALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def SXTAB16 {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_exta_rrot_np
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtab16${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAr;
  list<SchedReadWrite> SchedRW = [WriteALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def SXTAH {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_exta_rrot
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtah${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [(set GPRnopc:$Rd, (anonymous_3157 GPR:$Rn, (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAr;
  list<SchedReadWrite> SchedRW = [WriteALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def SXTB {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_ext_rrot
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtb${p}	$Rd, $Rm$rot";
  list<dag> Pattern = [(set GPRnopc:$Rd, (anonymous_3154 (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALUsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def SXTB16 {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_ext_rrot_np
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtb16${p}	$Rd, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALUsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def SXTH {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_ext_rrot
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxth${p}	$Rd, $Rm$rot";
  list<dag> Pattern = [(set GPRnopc:$Rd, (anonymous_3155 (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALUsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def SatFrm {	// Format
  bits<6> Value = { 0, 0, 1, 1, 0, 1 };
  string NAME = ?;
}
def SetEndAsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "SetEndImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,1>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = "parseSetEndImm";
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,1]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ShiftedImmAsmOperand {	// AsmOperandClass
  string Name = "RegShiftedImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ShiftedRegAsmOperand {	// AsmOperandClass
  string Name = "RegShiftedReg";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ShifterImmAsmOperand {	// AsmOperandClass
  string Name = "ShifterImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseShifterImm";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def StFrm {	// Format
  bits<6> Value = { 0, 0, 0, 1, 1, 1 };
  string NAME = ?;
}
def StMiscFrm {	// Format
  bits<6> Value = { 0, 0, 1, 0, 0, 1 };
  string NAME = ?;
}
def SubReg_i16_lane {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant(N->getZExtValue() & 3, SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def SubReg_i32_lane {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def SubReg_i8_lane {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant(N->getZExtValue() & 7, SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def Swift2P03P01FiveCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0, SwiftUnitP01];
  list<int> ResourceCycles = [2, 3];
  int Latency = 7;
  int NumMicroOps = 5;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftChooseShiftKindP01OneOrTwoCycle {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1865, anonymous_1852];
  bit Variadic = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftDiv {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0, SwiftUnitDiv];
  list<int> ResourceCycles = [1, 14];
  int Latency = 14;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftDiv17 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0, SwiftUnitDiv];
  list<int> ResourceCycles = [1, 15];
  int Latency = 17;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftDiv32 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0, SwiftUnitDiv];
  list<int> ResourceCycles = [1, 30];
  int Latency = 32;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftExt1xP0 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0];
  list<int> ResourceCycles = [1];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftExt2xP0 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0];
  list<int> ResourceCycles = [2];
  int Latency = 0;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftLMAddr10Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 10}];
  string NAME = ?;
}
def SwiftLMAddr11Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 11}];
  string NAME = ?;
}
def SwiftLMAddr12Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 12}];
  string NAME = ?;
}
def SwiftLMAddr13Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 13}];
  string NAME = ?;
}
def SwiftLMAddr14Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 14}];
  string NAME = ?;
}
def SwiftLMAddr15Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 15}];
  string NAME = ?;
}
def SwiftLMAddr16Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 16}];
  string NAME = ?;
}
def SwiftLMAddr1Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 1}];
  string NAME = ?;
}
def SwiftLMAddr2Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 2}];
  string NAME = ?;
}
def SwiftLMAddr3Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 3}];
  string NAME = ?;
}
def SwiftLMAddr4Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 4}];
  string NAME = ?;
}
def SwiftLMAddr5Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 5}];
  string NAME = ?;
}
def SwiftLMAddr6Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 6}];
  string NAME = ?;
}
def SwiftLMAddr7Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 7}];
  string NAME = ?;
}
def SwiftLMAddr8Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 8}];
  string NAME = ?;
}
def SwiftLMAddr9Pred {	// SchedPredicate
  SchedMachineModel SchedModel = SwiftModel;
  code Predicate = [{TII->getNumLDMAddresses(*MI) == 9}];
  string NAME = ?;
}
def SwiftModel {	// SchedMachineModel
  int IssueWidth = 3;
  int MicroOpBufferSize = 45;
  int LoopMicroOpBufferSize = -1;
  int LoadLatency = 3;
  int HighLatency = -1;
  int MispredictPenalty = 14;
  ProcessorItineraries Itineraries = NoItineraries;
  bit PostRAScheduler = 0;
  bit CompleteModel = 0;
  bit FullInstRWOverlapCheck = 0;
  list<Predicate> UnsupportedFeatures = [];
  bit NoModel = 0;
  string NAME = ?;
}
def SwiftP0P0P01FiveCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0, SwiftUnitP01];
  list<int> ResourceCycles = [2, 1];
  int Latency = 5;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftPredP0OneOrTwoCycle {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1873, anonymous_1874];
  bit Variadic = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftPredP0P01FourFiveCycle {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1883, anonymous_1884];
  bit Variadic = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftReadAdvanceALUsr {	// SchedReadWrite SchedRead SchedVariant SchedReadVariant
  list<SchedVar> Variants = [anonymous_1855, anonymous_1856];
  bit Variadic = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftReadAdvanceFourCyclesPred {	// SchedReadWrite SchedRead SchedVariant SchedReadVariant
  list<SchedVar> Variants = [anonymous_1886, anonymous_1887];
  bit Variadic = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftUnitDiv {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftUnitP0 {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = SwiftUnitP01;
  int BufferSize = -1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftUnitP01 {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 2;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftUnitP1 {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = SwiftUnitP01;
  int BufferSize = -1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftUnitP2 {	// ProcResourceKind ProcResourceUnits ProcResource
  ProcResourceKind Kind = EponymousProcResourceKind;
  int NumUnits = 1;
  ProcResourceKind Super = ?;
  int BufferSize = -1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm1 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [1];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm10 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [10];
  int Latency = 0;
  int NumMicroOps = 10;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm11 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [11];
  int Latency = 0;
  int NumMicroOps = 11;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm12 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [12];
  int Latency = 0;
  int NumMicroOps = 12;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm13 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [13];
  int Latency = 0;
  int NumMicroOps = 13;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm14 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [14];
  int Latency = 0;
  int NumMicroOps = 14;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm15 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [15];
  int Latency = 0;
  int NumMicroOps = 15;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm16 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [16];
  int Latency = 0;
  int NumMicroOps = 16;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm17 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [17];
  int Latency = 0;
  int NumMicroOps = 17;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm18 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [18];
  int Latency = 0;
  int NumMicroOps = 18;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm19 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [19];
  int Latency = 0;
  int NumMicroOps = 19;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm2 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [2];
  int Latency = 0;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm20 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [20];
  int Latency = 0;
  int NumMicroOps = 20;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm21 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [21];
  int Latency = 0;
  int NumMicroOps = 21;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm22 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [22];
  int Latency = 0;
  int NumMicroOps = 22;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm23 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [23];
  int Latency = 0;
  int NumMicroOps = 23;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm24 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [24];
  int Latency = 0;
  int NumMicroOps = 24;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm25 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [25];
  int Latency = 0;
  int NumMicroOps = 25;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm26 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [26];
  int Latency = 0;
  int NumMicroOps = 26;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm27 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [27];
  int Latency = 0;
  int NumMicroOps = 27;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm28 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [28];
  int Latency = 0;
  int NumMicroOps = 28;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm3 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [3];
  int Latency = 0;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm4 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [4];
  int Latency = 0;
  int NumMicroOps = 4;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm5 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [5];
  int Latency = 0;
  int NumMicroOps = 5;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm6 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [6];
  int Latency = 0;
  int NumMicroOps = 6;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm7 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [7];
  int Latency = 0;
  int NumMicroOps = 7;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm8 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [8];
  int Latency = 0;
  int NumMicroOps = 8;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftVLDMPerm9 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [9];
  int Latency = 0;
  int NumMicroOps = 9;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWaitP0For15Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0];
  list<int> ResourceCycles = [15];
  int Latency = 15;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWaitP1For15Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [15];
  int Latency = 15;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWaitP2For15Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [15];
  int Latency = 15;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrBackOne {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite1Cycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite1xP1TwoCycle {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP1TwoCycle];
  int Repeat = 1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite1xP2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP2];
  int Repeat = 1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite2xP1TwoCycle {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP1TwoCycle];
  int Repeat = 2;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite2xP2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP2];
  int Repeat = 2;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite2xP2FourCy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [2];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite3xP1TwoCycle {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP1TwoCycle];
  int Repeat = 3;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite3xP2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP2];
  int Repeat = 3;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite3xP2FourCy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [3];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite4xP1TwoCycle {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP1TwoCycle];
  int Repeat = 4;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite4xP2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP2];
  int Repeat = 4;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite5Cycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWrite6Cycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteALUSsr {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1853, anonymous_1852];
  bit Variadic = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteALUsi {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1849, anonymous_1850];
  bit Variadic = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteALUsr {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1851, anonymous_1852];
  bit Variadic = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLDMAddrNoWB {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLDMAddrWB {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP01, SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1914, anonymous_1915, anonymous_1916, anonymous_1917, anonymous_1918, anonymous_1919, anonymous_1920, anonymous_1921, anonymous_1922, anonymous_1923, anonymous_1924, anonymous_1925, anonymous_1926, anonymous_1927, anonymous_1928, anonymous_1929];
  bit Variadic = 1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM10Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM10CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 10;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM11Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM11CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM12Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM12CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM13Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 13;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM13CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 13;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM14Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 14;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM14CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 14;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM15Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM15CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 15;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM16Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 16;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM16CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 16;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM17Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 17;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM17CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 17;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM18Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 18;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM18CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 18;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM19Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 19;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM19CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 19;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM20Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 20;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM20CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 20;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM21Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 21;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM21CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 21;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM22Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 22;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM22CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 22;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM23Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 23;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM23CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 23;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM24Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 24;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM24CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 24;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM25Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 25;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM25CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 25;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM3Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM3CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM4Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM4CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM5Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM5CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM6Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM6CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM7Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM7CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM8Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM8CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM9Cy {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLM9CyNo {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 9;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteLdFour {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP01OneCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP01OneCycle2x {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP01OneCycle];
  int Repeat = 2;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP01OneCycle2x_load {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP01OneCycle, SwiftWriteP01OneCycle, SwiftWriteP2ThreeCycle];
  int Repeat = 1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP01OneCycle3x {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP01OneCycle];
  int Repeat = 3;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP01ThreeCycleTwoUops {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP01, SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP01TwoCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP0FourCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP0OneCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP0P01FiveCycleTwoUops {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0, SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP0P1FourCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0, SwiftUnitP1];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP0P1SixCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0, SwiftUnitP1];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP0SixCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP0ThreeCycleThreeUops {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0];
  list<int> ResourceCycles = [3];
  int Latency = 3;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP0TwoCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP0];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP0TwoCycleTwoUops {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP0OneCycle];
  int Repeat = 2;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP1EightCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP1FourCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP1SixCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP1TwelveCyc {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [];
  int Latency = 12;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP1TwoCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP2 {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP2FourCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP2P01FourCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2, SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP2P01P01FourCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2, SwiftUnitP01, SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP2P01ThreeCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2, SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP2P2P01ThreeCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2, SwiftUnitP2, SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP2P2ThreeCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2, SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteP2ThreeCycle {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_1937, anonymous_1938, anonymous_1939, anonymous_1940, anonymous_1941, anonymous_1942, anonymous_1943, anonymous_1944, anonymous_1945, anonymous_1946, anonymous_1947, anonymous_1948, anonymous_1949, anonymous_1950, anonymous_1951, anonymous_1952];
  bit Variadic = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM1 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM10 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 10;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM11 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 11;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM12 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 12;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM13 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 13;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM14 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 14;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM15 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 15;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM16 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 16;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM2 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 2;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM3 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 3;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM4 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 4;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM5 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 5;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM6 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 6;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM7 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 7;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM8 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 8;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteSTM9 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteStIncAddr];
  int Repeat = 9;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteStIncAddr {	// SchedReadWrite SchedWrite ProcWriteResources SchedWriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2, SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 2;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteVLDM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2007, anonymous_2008, anonymous_2009, anonymous_2010, anonymous_2011, anonymous_2012, anonymous_2013, anonymous_2014, anonymous_2015, anonymous_2016, anonymous_2017, anonymous_2018, anonymous_2019, anonymous_2020, anonymous_2021, anonymous_2022, anonymous_2023];
  bit Variadic = 1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def SwiftWriteVSTM {	// SchedReadWrite SchedWrite SchedVariant SchedWriteVariant
  list<SchedVar> Variants = [anonymous_2026, anonymous_2027, anonymous_2028, anonymous_2029, anonymous_2030, anonymous_2031, anonymous_2032, anonymous_2033, anonymous_2034, anonymous_2035, anonymous_2036, anonymous_2037, anonymous_2038, anonymous_2039, anonymous_2040, anonymous_2041, anonymous_2042];
  bit Variadic = 1;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def TAILJMPd {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins arm_br_target:$dst);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (Bcc arm_br_target:$dst, (ops 14, zero_reg));
  string NAME = ?;
}
def TAILJMPr {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Sched Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tcGPR:$dst);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV4T];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (BX GPR:$dst);
  string NAME = ?;
}
def TAILJMPr4 {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$dst);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, NoV4T];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg);
  string NAME = ?;
}
def TCRETURNdi {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$dst);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def TCRETURNri {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tcGPR:$dst);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def TEQri {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p);
  string AsmString = "teq${p}	$Rn, $imm";
  list<dag> Pattern = [(anonymous_3218 GPR:$Rn, mod_imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTi;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def TEQrr {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "teq${p}	$Rn, $Rm";
  list<dag> Pattern = [(anonymous_3218 GPR:$Rn, GPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTr;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def TEQrsi {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p);
  string AsmString = "teq${p}	$Rn, $shift";
  list<dag> Pattern = [(anonymous_3218 GPR:$Rn, so_reg_imm:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTsr;
  list<SchedReadWrite> SchedRW = [WriteCMPsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def TEQrsr {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p);
  string AsmString = "teq${p}	$Rn, $shift";
  list<dag> Pattern = [(anonymous_3218 GPRnopc:$Rn, so_reg_reg:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTsr;
  list<SchedReadWrite> SchedRW = [WriteCMPsr, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def TPsoft {	// Instruction InstTemplate PseudoInst ARMPseudoInst Sched Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = [(set R0, ARMthread_pointer)];
  list<Register> Uses = [SP];
  list<Register> Defs = [R0, R12, LR, CPSR];
  list<Predicate> Predicates = [IsARM, IsReadTPSoft];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def TRAP {	// Instruction InstTemplate Encoding InstARM XI AXI Requires
  field bits<32> Inst = { 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "trap";
  list<dag> Pattern = [(trap)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, DontUseNaClTrap];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def TRAPNaCl {	// Instruction InstTemplate Encoding InstARM XI AXI Requires
  field bits<32> Inst = { 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "trap";
  list<dag> Pattern = [(trap)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, UseNaClTrap];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def TSTri {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, imm{11}, imm{10}, imm{9}, imm{8}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, mod_imm:$imm, pred:$p);
  string AsmString = "tst${p}	$Rn, $imm";
  list<dag> Pattern = [(anonymous_3217 GPR:$Rn, mod_imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTi;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def TSTrr {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "tst${p}	$Rn, $Rm";
  list<dag> Pattern = [(anonymous_3217 GPR:$Rn, GPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTr;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeTSTInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def TSTrsi {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, shift{11}, shift{10}, shift{9}, shift{8}, shift{7}, shift{6}, shift{5}, 0, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, so_reg_imm:$shift, pred:$p);
  string AsmString = "tst${p}	$Rn, $shift";
  list<dag> Pattern = [(anonymous_3217 GPR:$Rn, so_reg_imm:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTsr;
  list<SchedReadWrite> SchedRW = [WriteCMPsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegImmFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def TSTrsr {	// Instruction InstTemplate Encoding InstARM I AI1 Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, shift{11}, shift{10}, shift{9}, shift{8}, 0, shift{6}, shift{5}, 1, shift{3}, shift{2}, shift{1}, shift{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p);
  string AsmString = "tst${p}	$Rn, $shift";
  list<dag> Pattern = [(anonymous_3217 GPRnopc:$Rn, so_reg_reg:$shift)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTsr;
  list<SchedReadWrite> SchedRW = [WriteCMPsr, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPSoRegRegFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> shift = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def Throws {	// IntrinsicProperty
  string NAME = ?;
}
def ThumbBranchTarget {	// AsmOperandClass
  string Name = "ThumbBranchTarget";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ThumbFrm {	// Format
  bits<6> Value = { 0, 1, 1, 0, 0, 1 };
  string NAME = ?;
}
def ThumbMemPC {	// AsmOperandClass
  string Name = "ThumbMemPC";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ThumbModImmNeg1_7AsmOperand {	// AsmOperandClass
  string Name = "ThumbModImmNeg1_7";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ThumbModImmNeg8_255AsmOperand {	// AsmOperandClass
  string Name = "ThumbModImmNeg8_255";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def ThumbSRImmAsmOperand {	// AsmOperandClass ImmAsmOperand
  string Name = "ImmThumbSR";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,32>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [1,32]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def Tuples2DSpc {	// RegisterTuples
  list<dag> SubRegs = [(shl DPR, 0), (shl DPR, 2)];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_2];
  string NAME = ?;
}
def Tuples2Q {	// RegisterTuples
  list<dag> SubRegs = [(shl QPR, 0), (shl QPR, 1)];
  list<SubRegIndex> SubRegIndices = [qsub_0, qsub_1];
  string NAME = ?;
}
def Tuples2QQ {	// RegisterTuples
  list<dag> SubRegs = [(shl QQPR, 0), (shl QQPR, 2)];
  list<SubRegIndex> SubRegIndices = [qqsub_0, qqsub_1];
  string NAME = ?;
}
def Tuples2R {	// RegisterTuples
  list<dag> SubRegs = [(add R0, R2, R4, R6, R8, R10, R12), (add R1, R3, R5, R7, R9, R11, SP)];
  list<SubRegIndex> SubRegIndices = [gsub_0, gsub_1];
  string NAME = ?;
}
def Tuples3D {	// RegisterTuples
  list<dag> SubRegs = [(shl DPR, 0), (shl DPR, 1), (shl DPR, 2)];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1, dsub_2];
  string NAME = ?;
}
def Tuples3DSpc {	// RegisterTuples
  list<dag> SubRegs = [(shl DPR, 0), (shl DPR, 2), (shl DPR, 4)];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_2, dsub_4];
  string NAME = ?;
}
def Tuples4DSpc {	// RegisterTuples
  list<dag> SubRegs = [(shl DPR, 0), (shl DPR, 2), (shl DPR, 4), (shl DPR, 6)];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_2, dsub_4, dsub_6];
  string NAME = ?;
}
def TuplesOE2D {	// RegisterTuples
  list<dag> SubRegs = [(decimate (shl DPR, 1), 2), (decimate (shl DPR, 2), 2)];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1];
  string NAME = ?;
}
def TuplesOE4D {	// RegisterTuples
  list<dag> SubRegs = [(decimate (shl DPR, 1), 2), (decimate (shl DPR, 2), 2), (decimate (shl DPR, 3), 2), (decimate (shl DPR, 4), 2)];
  list<SubRegIndex> SubRegIndices = [dsub_0, dsub_1, dsub_2, dsub_3];
  string NAME = ?;
}
def UADD16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uadd16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UADD8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uadd8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UASX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uasx GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UBFX {	// Instruction InstTemplate Encoding InstARM I Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 1, 1, 1, width{4}, width{3}, width{2}, width{1}, width{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, lsb{4}, lsb{3}, lsb{2}, lsb{1}, lsb{0}, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width, pred:$p);
  string AsmString = "ubfx${p}	$Rd, $Rn, $lsb, $width";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAsi;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<5> lsb = { ?, ?, ?, ?, ? };
  bits<5> width = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def UDF {	// Instruction InstTemplate Encoding InstARM InoP AInoP
  field bits<32> Inst = { 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, imm16{15}, imm16{14}, imm16{13}, imm16{12}, imm16{11}, imm16{10}, imm16{9}, imm16{8}, imm16{7}, imm16{6}, imm16{5}, imm16{4}, 1, 1, 1, 1, imm16{3}, imm16{2}, imm16{1}, imm16{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_65535:$imm16);
  string AsmString = "udf	$imm16";
  list<dag> Pattern = [(int_arm_undefined imm0_65535:$imm16)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<16> imm16 = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def UDIV {	// Instruction InstTemplate Encoding InstARM I ADivA1I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 0, 0, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "udiv${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasDivideInARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iDIV;
  list<SchedReadWrite> SchedRW = [WriteDIV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ArithMiscFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UHADD16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uhadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uhadd16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UHADD8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uhadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uhadd8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UHASX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uhasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uhasx GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UHSAX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uhsax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uhsax GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UHSUB16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uhsub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uhsub16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UHSUB8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uhsub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uhsub8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UMAAL {	// Instruction InstTemplate Encoding InstARM I AMul1I RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 0, 1, 0, 0, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$RdLo, GPR:$RdHi);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p);
  string AsmString = "umaal${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def UMLAL {	// Instruction InstTemplate Encoding InstARM sI AsMul1I AsMla1I64 RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 0, 1, s{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$RdLo, GPR:$RdHi);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s);
  string AsmString = "umlal${s}${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def UMLALv5 {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$RdLo, GPR:$RdHi);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, NoV6];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s);
  string NAME = ?;
}
def UMULL {	// Instruction InstTemplate Encoding InstARM sI AsMul1I AsMul1I64 Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 0, 0, 0, 1, 0, 0, s{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$RdLo, GPR:$RdHi);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "umull${s}${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$RdLo, GPR:$RdHi, (umullohi GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<1> s = { ? };
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def UMULLv5 {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$RdLo, GPR:$RdHi);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$RdLo, GPR:$RdHi, (umullohi GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, NoV6];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL64;
  list<SchedReadWrite> SchedRW = [WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL];
  string Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  string NAME = ?;
}
def UQADD16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uqadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uqadd16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UQADD8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uqadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uqadd8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UQASX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uqasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uqasx GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UQSAX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uqsax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uqsax GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UQSUB16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uqsub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uqsub16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UQSUB8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "uqsub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_uqsub8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def USAD8 {	// Instruction InstTemplate Encoding InstARM I AI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 1, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "usad8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def USADA8 {	// Instruction InstTemplate Encoding InstARM I AI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 1, 1, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p);
  string AsmString = "usada8${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = MulFrm;
  bits<6> Form = { 0, 0, 0, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def USAT {	// Instruction InstTemplate Encoding InstARM I AI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 1, sat_imm{4}, sat_imm{3}, sat_imm{2}, sat_imm{1}, sat_imm{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{4}, sh{3}, sh{2}, sh{1}, sh{0}, sh{5}, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh, pred:$p);
  string AsmString = "usat${p}	$Rd, $sat_imm, $Rn$sh";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = SatFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<5> sat_imm = { ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<8> sh = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def USAT16 {	// Instruction InstTemplate Encoding InstARM I AI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 1, 0, sat_imm{3}, sat_imm{2}, sat_imm{1}, sat_imm{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins imm0_15:$sat_imm, GPRnopc:$Rn, pred:$p);
  string AsmString = "usat16${p}	$Rd, $sat_imm, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = SatFrm;
  bits<6> Form = { 0, 0, 1, 1, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> sat_imm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def USAX {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "usax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_usax GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def USUB16 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "usub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_usub16 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def USUB8 {	// Instruction InstTemplate Encoding InstARM I AI Sched AAI AAIIntrinsic
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p);
  string AsmString = "usub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (int_arm_usub8 GPRnopc:$Rn, GPRnopc:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = DPFrm;
  bits<6> Form = { 0, 0, 0, 1, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def UXTAB {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_exta_rrot
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtab${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [(set GPRnopc:$Rd, (anonymous_3167 GPR:$Rn, (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAr;
  list<SchedReadWrite> SchedRW = [WriteALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def UXTAB16 {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_exta_rrot_np
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtab16${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAr;
  list<SchedReadWrite> SchedRW = [WriteALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def UXTAH {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_exta_rrot
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtah${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [(set GPRnopc:$Rd, (anonymous_3168 GPR:$Rn, (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAr;
  list<SchedReadWrite> SchedRW = [WriteALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def UXTB {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_ext_rrot
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtb${p}	$Rd, $Rm$rot";
  list<dag> Pattern = [(set GPRnopc:$Rd, (anonymous_3162 (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALUsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def UXTB16 {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_ext_rrot
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtb16${p}	$Rd, $Rm$rot";
  list<dag> Pattern = [(set GPRnopc:$Rd, (anonymous_3164 (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALUsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def UXTH {	// Instruction InstTemplate Encoding InstARM I AExtI Requires Sched AI_ext_rrot
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, rot{1}, rot{0}, 0, 0, 0, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxth${p}	$Rd, $Rm$rot";
  list<dag> Pattern = [(set GPRnopc:$Rd, (anonymous_3163 (rotr GPRnopc:$Rm, rot_imm:$rot)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM, HasV6];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALUsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ExtFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def UnsignedOffset_b8s2 {	// AsmOperandClass OperandUnsignedOffset_b8s2
  string Name = "UnsignedOffset_b8s2";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isUnsignedOffset<8, 2>";
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def UseFPVMLx {	// Predicate
  string CondString = "Subtarget->useFPVMLx()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def UseFusedMAC {	// Predicate
  string CondString = "(TM.Options.AllowFPOpFusion == FPOpFusion::Fast &&  Subtarget->hasVFP4()) && !Subtarget->isTargetDarwin()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def UseMovt {	// Predicate
  string CondString = "Subtarget->useMovt(*MF)";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 1;
  string NAME = ?;
}
def UseMovtInPic {	// Predicate
  string CondString = "Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 1;
  string NAME = ?;
}
def UseMulOps {	// Predicate
  string CondString = "Subtarget->useMulOps()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def UseNEONForFP {	// Predicate
  string CondString = "Subtarget->useNEONForSinglePrecisionFP()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def UseNaClTrap {	// Predicate AssemblerPredicate
  string CondString = "Subtarget->useNaClTrap()";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "FeatureNaClTrap";
  string PredicateName = "NaCl";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def UseNegativeImmediates {	// Predicate AssemblerPredicate
  string CondString = "false";
  bit AssemblerMatcherPredicate = 1;
  string AssemblerCondString = "!FeatureNoNegativeImmediates";
  string PredicateName = "NegativeImmediates";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def UseVMOVSR {	// Predicate
  string CondString = "Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP()";
  bit AssemblerMatcherPredicate = 0;
  string AssemblerCondString = "";
  string PredicateName = "";
  bit RecomputePerFunction = 0;
  string NAME = ?;
}
def V6_Pipe {	// FuncUnit
  string NAME = ?;
}
def VABALsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExtOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabal${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 QPR:$src1), (v2i64 (zext (v2i32 (int_arm_neon_vabds (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABALsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExtOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabal${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 QPR:$src1), (v4i32 (zext (v4i16 (int_arm_neon_vabds (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABALsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExtOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabal${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v8i16 QPR:$src1), (v8i16 (zext (v8i8 (int_arm_neon_vabds (v8i8 DPR:$Vn), (v8i8 DPR:$Vm)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABALuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExtOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabal${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 QPR:$src1), (v2i64 (zext (v2i32 (int_arm_neon_vabdu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABALuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExtOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabal${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 QPR:$src1), (v4i32 (zext (v4i16 (int_arm_neon_vabdu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABALuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExtOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabal${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v8i16 QPR:$src1), (v8i16 (zext (v8i8 (int_arm_neon_vabdu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (add QPR:$src1, (v16i8 (int_arm_neon_vabds (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (add DPR:$src1, (v2i32 (int_arm_neon_vabds (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (add DPR:$src1, (v4i16 (int_arm_neon_vabds (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (add QPR:$src1, (v4i32 (int_arm_neon_vabds (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (add QPR:$src1, (v8i16 (int_arm_neon_vabds (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (add DPR:$src1, (v8i8 (int_arm_neon_vabds (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (add QPR:$src1, (v16i8 (int_arm_neon_vabdu (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (add DPR:$src1, (v2i32 (int_arm_neon_vabdu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (add DPR:$src1, (v4i16 (int_arm_neon_vabdu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (add QPR:$src1, (v4i32 (int_arm_neon_vabdu (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (add QPR:$src1, (v8i16 (int_arm_neon_vabdu (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABAuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaba${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (add DPR:$src1, (v8i8 (int_arm_neon_vabdu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VABAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabdl${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (zext (v2i32 (int_arm_neon_vabds (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabdl${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (zext (v4i16 (int_arm_neon_vabds (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabdl${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (zext (v8i8 (int_arm_neon_vabds (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabdl${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (zext (v2i32 (int_arm_neon_vabdu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabdl${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (zext (v4i16 (int_arm_neon_vabdu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLIntExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabdl${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (zext (v8i8 (int_arm_neon_vabdu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vabds (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vabds (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vabds (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vabds (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vabds (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vabds (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VABDsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vabds (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VABDsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vabds (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VABDsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vabds (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VABDsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vabds (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vabdu (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABDuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vabdu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VABDuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vabdu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VABDuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vabdu (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VABDuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vabdu (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VABDuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vabd${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vabdu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 0, 0, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vabs${p}.f64	$Dd, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vabs${p}.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI ASuIn
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vabs${p}.f32	$Sd, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fabs SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fabs (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fabs (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABShd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fabs (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABShq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fabs (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (abs (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (abs (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (abs (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (abs (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (abs (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VABSv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vabs${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (abs (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VACGEfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vacge${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vacge (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VACGEfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vacge${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vacge (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VACGEhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vacge${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vacge (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VACGEhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vacge${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vacge (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VACGTfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vacgt${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vacgt (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VACGTfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vacgt${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vacgt (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VACGThd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vacgt${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vacgt (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VACGThq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vacgt${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vacgt (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Dd{4}, 1, 1, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vadd${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpALU64;
  list<SchedReadWrite> SchedRW = [WriteFPALU64];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Dn = $Dd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 1, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vadd${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fadd HPR:$Sn, HPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpALU16;
  list<SchedReadWrite> SchedRW = [WriteFPALU32];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Sn = $Sd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDHNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vaddhn${p}.i64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (null_frag (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDHNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vaddhn${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (null_frag (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDHNv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vaddhn${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (null_frag (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddl${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 (sext (v2i32 DPR:$Vn))), (v2i64 (sext (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddl${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 (sext (v4i16 DPR:$Vn))), (v4i32 (sext (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddl${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v8i16 (sext (v8i8 DPR:$Vn))), (v8i16 (sext (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddl${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 (zext (v2i32 DPR:$Vn))), (v2i64 (zext (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddl${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 (zext (v4i16 DPR:$Vn))), (v4i32 (zext (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddl${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v8i16 (zext (v8i8 DPR:$Vn))), (v8i16 (zext (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI ASbIn Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 1, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vadd${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpALU32;
  list<SchedReadWrite> SchedRW = [WriteFPALU32];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Sn = $Sd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDWsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddw${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 QPR:$Vn), (v2i64 (sext (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDWsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddw${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 QPR:$Vn), (v4i32 (sext (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDWsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddw${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v8i16 QPR:$Vn), (v8i16 (sext (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDWuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddw${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 QPR:$Vn), (v2i64 (zext (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDWuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddw${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 QPR:$Vn), (v4i32 (zext (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDWuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vaddw${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v8i16 QPR:$Vn), (v8i16 (zext (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fadd (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fadd (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fadd (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fadd (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (add (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VADDv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.i64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (add (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (add (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VADDv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.i64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (add (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VADDv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (add (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VADDv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (add (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VADDv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (add (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VADDv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vadd${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (add (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VANDd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX N3VDX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vand${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (and (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VANDq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX N3VQX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vand${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (and (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBICd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vbic${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (and DPR:$Vn, (vnotd DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBICiv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, SIMM{10}, SIMM{9}, 1, 0, 0, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmSplatI32:$SIMM, DPR:$src, pred:$p);
  string AsmString = "vbic${p}.i32	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBICiv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, SIMM{9}, 1, 0, 0, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmSplatI16:$SIMM, DPR:$src, pred:$p);
  string AsmString = "vbic${p}.i16	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBICiv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, SIMM{10}, SIMM{9}, 1, 0, 1, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmSplatI32:$SIMM, QPR:$src, pred:$p);
  string AsmString = "vbic${p}.i32	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBICiv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, SIMM{9}, 1, 0, 1, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmSplatI16:$SIMM, QPR:$src, pred:$p);
  string AsmString = "vbic${p}.i16	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBICq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vbic${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (and QPR:$Vn, (vnotq QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBIFd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vbif${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBIFq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vbif${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBITd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vbit${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBITq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vbit${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBSLd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vbsl${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VBSLq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vbsl${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCADDv2f32 {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8 BaseN3VCP8ComplexOdd
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{0}, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, complexrotateopodd:$rot);
  string AsmString = "vcadd.f32	$Vd, $Vn, $Vm, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<1> rot = { ? };
  string NAME = ?;
}
def VCADDv4f16 {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8 BaseN3VCP8ComplexOdd
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{0}, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, complexrotateopodd:$rot);
  string AsmString = "vcadd.f16	$Vd, $Vn, $Vm, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<1> rot = { ? };
  string NAME = ?;
}
def VCADDv4f32 {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8 BaseN3VCP8ComplexOdd
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{0}, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, complexrotateopodd:$rot);
  string AsmString = "vcadd.f32	$Vd, $Vn, $Vm, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<1> rot = { ? };
  string NAME = ?;
}
def VCADDv8f16 {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8 BaseN3VCP8ComplexOdd
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{0}, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, complexrotateopodd:$rot);
  string AsmString = "vcadd.f16	$Vd, $Vn, $Vm, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<1> rot = { ? };
  string NAME = ?;
}
def VCEQfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvceq (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvceq (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvceq (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvceq (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvceq (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvceq (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvceq (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvceq (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvceq (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvceq (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvceqz (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv2f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvceqz (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvceqz (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv4f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvceqz (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv4f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvceqz (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvceqz (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvceqz (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv8f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvceqz (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvceqz (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCEQzv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vceq${p}.i8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvceqz (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcge (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcge (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcge (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcge (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvcge (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcge (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcge (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcge (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcge (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvcge (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvcgeu (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcgeu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcgeu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcgeu (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcgeu (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvcgeu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvcgez (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv2f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcgez (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcgez (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv4f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcgez (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv4f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcgez (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcgez (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcgez (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv8f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcgez (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcgez (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGEzv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcge${p}.s8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvcgez (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcgt (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcgt (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGThd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcgt (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGThq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcgt (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvcgt (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcgt (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcgt (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcgt (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcgt (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvcgt (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvcgtu (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcgtu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcgtu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcgtu (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcgtu (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvcgtu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvcgtz (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv2f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcgtz (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcgtz (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv4f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcgtz (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv4f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcgtz (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcgtz (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcgtz (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv8f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcgtz (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcgtz (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCGTzv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcgt${p}.s8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvcgtz (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.s8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvclez (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv2f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvclez (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.s32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvclez (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv4f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvclez (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv4f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvclez (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.s16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvclez (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.s32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvclez (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv8f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvclez (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.s16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvclez (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLEzv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcle${p}.s8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvclez (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLSv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcls${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vcls (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLSv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcls${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcls (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLSv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcls${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcls (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLSv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcls${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcls (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLSv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcls${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcls (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLSv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcls${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vcls (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.s8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvcltz (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv2f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcltz (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.s32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvcltz (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv4f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcltz (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv4f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.f32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcltz (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.s16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvcltz (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.s32	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvcltz (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv8f16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.f16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcltz (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.s16	$Vd, $Vm, #0";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvcltz (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLTzv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vclt${p}.s8	$Vd, $Vm, #0";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvcltz (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLZv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vclz${p}.i8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (ctlz (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLZv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vclz${p}.i32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (ctlz (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLZv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vclz${p}.i16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (ctlz (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLZv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vclz${p}.i32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (ctlz (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLZv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vclz${p}.i16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (ctlz (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCLZv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vclz${p}.i8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (ctlz (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMLAv2f32 {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8 BaseN3VCP8ComplexTied
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{1}, rot{0}, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, complexrotateop:$rot);
  string AsmString = "vcmla.f32	$Vd, $Vn, $Vm, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def VCMLAv2f32_indexed {	// Instruction InstTemplate Encoding InstARM NeonInp N3VLaneCP8 BaseN3VCP8ComplexTiedLane64
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Vd{4}, rot{1}, rot{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, VectorIndex64:$lane, complexrotateop:$rot);
  string AsmString = "vcmla.f32	$Vd, $Vn, $Vm$lane, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeNEONComplexLane64Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VCMLAv4f16 {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8 BaseN3VCP8ComplexTied
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{1}, rot{0}, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, complexrotateop:$rot);
  string AsmString = "vcmla.f16	$Vd, $Vn, $Vm, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def VCMLAv4f16_indexed {	// Instruction InstTemplate Encoding InstARM NeonInp N3VLaneCP8 BaseN3VCP8ComplexTiedLane32
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Vd{4}, rot{1}, rot{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, complexrotateop:$rot);
  string AsmString = "vcmla.f16	$Vd, $Vn, $Vm$lane, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VCMLAv4f32 {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8 BaseN3VCP8ComplexTied
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{1}, rot{0}, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, complexrotateop:$rot);
  string AsmString = "vcmla.f32	$Vd, $Vn, $Vm, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def VCMLAv4f32_indexed {	// Instruction InstTemplate Encoding InstARM NeonInp N3VLaneCP8 BaseN3VCP8ComplexTiedLane64
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Vd{4}, rot{1}, rot{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR:$Vm, VectorIndex64:$lane, complexrotateop:$rot);
  string AsmString = "vcmla.f32	$Vd, $Vn, $Vm$lane, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeNEONComplexLane64Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VCMLAv8f16 {	// Instruction InstTemplate Encoding InstARM NeonInp N3VCP8 BaseN3VCP8ComplexTied
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, rot{1}, rot{0}, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, complexrotateop:$rot);
  string AsmString = "vcmla.f16	$Vd, $Vn, $Vm, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def VCMLAv8f16_indexed {	// Instruction InstTemplate Encoding InstARM NeonInp N3VLaneCP8 BaseN3VCP8ComplexTiedLane32
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Vd{4}, rot{1}, rot{0}, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, complexrotateop:$rot);
  string AsmString = "vcmla.f16	$Vd, $Vn, $Vm$lane, $rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_3a, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegCplxFrm;
  bits<6> Form = { 1, 0, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VCMPD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 1, 0, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins DPR:$Dd, DPR:$Dm, pred:$p);
  string AsmString = "vcmp${p}.f64	$Dd, $Dm";
  list<dag> Pattern = [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPED {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 1, 0, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins DPR:$Dd, DPR:$Dm, pred:$p);
  string AsmString = "vcmpe${p}.f64	$Dd, $Dm";
  list<dag> Pattern = [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm), (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPEH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins HPR:$Sd, HPR:$Sm, pred:$p);
  string AsmString = "vcmpe${p}.f16	$Sd, $Sm";
  list<dag> Pattern = [(arm_cmpfp HPR:$Sd, HPR:$Sm, (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPES {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins SPR:$Sd, SPR:$Sm, pred:$p);
  string AsmString = "vcmpe${p}.f32	$Sd, $Sm";
  list<dag> Pattern = [(arm_cmpfp SPR:$Sd, SPR:$Sm, (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPEZD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 1, 0, 1, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins DPR:$Dd, pred:$p);
  string AsmString = "vcmpe${p}.f64	$Dd, #0";
  list<dag> Pattern = [(arm_cmpfp0 (f64 DPR:$Dd), (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPEZH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins HPR:$Sd, pred:$p);
  string AsmString = "vcmpe${p}.f16	$Sd, #0";
  list<dag> Pattern = [(arm_cmpfp0 HPR:$Sd, (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPEZS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins SPR:$Sd, pred:$p);
  string AsmString = "vcmpe${p}.f32	$Sd, #0";
  list<dag> Pattern = [(arm_cmpfp0 SPR:$Sd, (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins HPR:$Sd, HPR:$Sm, pred:$p);
  string AsmString = "vcmp${p}.f16	$Sd, $Sm";
  list<dag> Pattern = [(arm_cmpfp HPR:$Sd, HPR:$Sm, (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins SPR:$Sd, SPR:$Sm, pred:$p);
  string AsmString = "vcmp${p}.f32	$Sd, $Sm";
  list<dag> Pattern = [(arm_cmpfp SPR:$Sd, SPR:$Sm, (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPZD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 1, 0, 1, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins DPR:$Dd, pred:$p);
  string AsmString = "vcmp${p}.f64	$Dd, #0";
  list<dag> Pattern = [(arm_cmpfp0 (f64 DPR:$Dd), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPZH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins HPR:$Sd, pred:$p);
  string AsmString = "vcmp${p}.f16	$Sd, #0";
  list<dag> Pattern = [(arm_cmpfp0 HPR:$Sd, (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCMPZS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins SPR:$Sd, pred:$p);
  string AsmString = "vcmp${p}.f32	$Sd, #0";
  list<dag> Pattern = [(arm_cmpfp0 SPR:$Sd, (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR_NZCV];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCMP32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCNTd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcnt${p}.8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (ctpop (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCNTq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcnt${p}.8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (ctpop (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VCNTiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTANSDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvta.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtas (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTANSDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvta.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtas (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTANSQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvta.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtas (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTANSQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvta.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtas (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTANUDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvta.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtau (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTANUDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvta.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtau (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTANUQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvta.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtau (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTANUQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvta.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtau (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTASD {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vcvta.s32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTASH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm);
  string AsmString = "vcvta.s32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTASS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vcvta.s32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTAUD {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vcvta.u32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTAUH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm);
  string AsmString = "vcvta.u32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTAUS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vcvta.u32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTAanonymous_3742 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (fround HPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTASH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTAanonymous_3743 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (fround HPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTAUH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTAanonymous_3744 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (fround SPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTASS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTAanonymous_3745 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (fround SPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTAUS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTAanonymous_3746 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (fround (f64 DPR:$a))));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTASD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTAanonymous_3747 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (fround (f64 DPR:$a))));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTAUD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTBDH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vcvtb${p}.f16.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTBHD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 0, 1, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtb${p}.f64.f16	$Dd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTBHS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtb${p}.f32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSH;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTBSH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtb${p}.f16.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHS;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTDS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 1, 1, 1, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.f64.f32	$Dd, $Sm";
  list<dag> Pattern = [(set DPR:$Dd, (fpextend SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDS;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMNSDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtm.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtms (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMNSDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtm.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtms (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMNSQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtm.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtms (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMNSQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtm.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtms (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMNUDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtm.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtmu (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMNUDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtm.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtmu (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMNUQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtm.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtmu (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMNUQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtm.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtmu (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMSD {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vcvtm.s32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMSH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm);
  string AsmString = "vcvtm.s32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMSS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vcvtm.s32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMUD {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vcvtm.u32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMUH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm);
  string AsmString = "vcvtm.u32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTMUS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vcvtm.u32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTManonymous_3742 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (ffloor HPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTMSH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTManonymous_3743 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (ffloor HPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTMUH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTManonymous_3744 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (ffloor SPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTMSS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTManonymous_3745 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (ffloor SPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTMUS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTManonymous_3746 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (ffloor (f64 DPR:$a))));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTMSD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTManonymous_3747 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (ffloor (f64 DPR:$a))));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTMUD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTNNSDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtn.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtns (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNNSDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtn.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtns (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNNSQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtn.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtns (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNNSQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtn.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtns (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNNUDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtn.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtnu (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNNUDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtn.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtnu (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNNUQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtn.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtnu (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNNUQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtn.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtnu (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNSD {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vcvtn.s32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNSH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm);
  string AsmString = "vcvtn.s32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNSS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vcvtn.s32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNUD {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vcvtn.u32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNUH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm);
  string AsmString = "vcvtn.u32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNUS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vcvtn.u32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTNanonymous_3742 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (null_frag HPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTNSH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTNanonymous_3743 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (null_frag HPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTNUH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTNanonymous_3744 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (null_frag SPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTNSS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTNanonymous_3745 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (null_frag SPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTNUS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTNanonymous_3746 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (null_frag (f64 DPR:$a))));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTNSD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTNanonymous_3747 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (null_frag (f64 DPR:$a))));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTNUD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTPNSDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtp.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtps (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPNSDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtp.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtps (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPNSQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtp.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtps (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPNSQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtp.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtps (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPNUDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtp.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtpu (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPNUDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vcvtp.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtpu (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPNUQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtp.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtpu (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPNUQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vcvtp.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtpu (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPSD {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vcvtp.s32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPSH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm);
  string AsmString = "vcvtp.s32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPSS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vcvtp.s32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPUD {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vcvtp.u32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPUH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm);
  string AsmString = "vcvtp.u32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPUS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vcvtp.u32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTPanonymous_3742 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (fceil HPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTPSH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTPanonymous_3743 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (fceil HPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTPUH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTPanonymous_3744 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (fceil SPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTPSS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTPanonymous_3745 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (fceil SPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTPUS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTPanonymous_3746 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_sint (fceil (f64 DPR:$a))));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTPSD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTPanonymous_3747 {	// Pattern Pat
  dag PatternToMatch = (i32 (fp_to_uint (fceil (f64 DPR:$a))));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTPUD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VCVTSD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vcvt${p}.f32.f64	$Sd, $Dm";
  list<dag> Pattern = [(set SPR:$Sd, (fpround DPR:$Dm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSD;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTTDH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vcvtt${p}.f16.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTTHD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 0, 1, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtt${p}.f64.f16	$Dd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTTHS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtt${p}.f32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSH;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTTSH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtt${p}.f16.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHS;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTf2h {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f16.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtfp2hf (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTf2sd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (fp_to_sint (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTf2sq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.s32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (fp_to_sint (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTf2ud {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (fp_to_uint (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTf2uq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.u32.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (fp_to_uint (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTf2xsd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.s32.f32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtfp2fxs (v2f32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTD";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTf2xsq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.s32.f32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtfp2fxs (v4f32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTQ";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTf2xud {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.u32.f32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vcvtfp2fxu (v2f32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTD";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTf2xuq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.u32.f32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vcvtfp2fxu (v4f32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTQ";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTh2f {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VLInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f32.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vcvthf2fp (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTh2sd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (fp_to_sint (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTh2sq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.s16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (fp_to_sint (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTh2ud {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (fp_to_uint (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTh2uq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.u16.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (fp_to_uint (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTh2xsd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.s16.f16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtfp2fxs (v4f16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTD";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTh2xsq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.s16.f16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtfp2fxs (v8f16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTQ";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTh2xud {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.u16.f16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vcvtfp2fxu (v4f16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTD";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTh2xuq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.u16.f16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vcvtfp2fxu (v8f16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTQ";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTs2fd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f32.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (sint_to_fp (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTs2fq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f32.s32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (sint_to_fp (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTs2hd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f16.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (sint_to_fp (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTs2hq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f16.s16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (sint_to_fp (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTu2fd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f32.u32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (uint_to_fp (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTu2fq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f32.u32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (uint_to_fp (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTu2hd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f16.u16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (uint_to_fp (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTu2hq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vcvt${p}.f16.u16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (uint_to_fp (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTxs2fd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.f32.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vcvtfxs2fp (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTD";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTxs2fq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.f32.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vcvtfxs2fp (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTQ";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTxs2hd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.f16.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vcvtfxs2fp (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTD";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTxs2hq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.f16.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vcvtfxs2fp (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTQ";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTxu2fd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.f32.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vcvtfxu2fp (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTD";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTxu2fq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.f32.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vcvtfxu2fp (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTQ";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTxu2hd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.f16.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vcvtfxu2fp (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTD";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VCVTxu2hq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VCvtQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, neon_vcvt_imm32:$SIMM, pred:$p);
  string AsmString = "vcvt${p}.f16.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vcvtfxu2fp (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVCVTQ";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVCVTFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VDIVD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 0, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vdiv${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpDIV64;
  list<SchedReadWrite> SchedRW = [WriteFPDIV64];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Dn = $Dd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VDIVH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vdiv${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fdiv HPR:$Sn, HPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpDIV16;
  list<SchedReadWrite> SchedRW = [WriteFPDIV32];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Sn = $Sd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VDIVS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vdiv${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpDIV32;
  list<SchedReadWrite> SchedRW = [WriteFPDIV32];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Sn = $Sd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VDUP16d {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVDup VDUPD
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 0, 0, 0, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, 0, 1, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$V);
  dag InOperandList = (ins GPR:$R, pred:$p);
  string AsmString = "vdup${p}.16	$V, $R";
  list<dag> Pattern = [(set DPR:$V, (v4i16 (NEONvdup (i32 GPR:$R))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVIS;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NDupFrm;
  bits<6> Form = { 0, 1, 1, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VDUP16q {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVDup VDUPQ
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 0, 1, 0, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, 0, 1, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$V);
  dag InOperandList = (ins GPR:$R, pred:$p);
  string AsmString = "vdup${p}.16	$V, $R";
  list<dag> Pattern = [(set QPR:$V, (v8i16 (NEONvdup (i32 GPR:$R))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVIS;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NDupFrm;
  bits<6> Form = { 0, 1, 1, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VDUP32d {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVDup VDUPD Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 0, 0, 0, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$V);
  dag InOperandList = (ins GPR:$R, pred:$p);
  string AsmString = "vdup${p}.32	$V, $R";
  list<dag> Pattern = [(set DPR:$V, (v2i32 (NEONvdup (i32 GPR:$R))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFastVDUP32];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVIS;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NDupFrm;
  bits<6> Form = { 0, 1, 1, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VDUP32q {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVDup VDUPQ
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 0, 1, 0, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$V);
  dag InOperandList = (ins GPR:$R, pred:$p);
  string AsmString = "vdup${p}.32	$V, $R";
  list<dag> Pattern = [(set QPR:$V, (v4i32 (NEONvdup (i32 GPR:$R))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVIS;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NDupFrm;
  bits<6> Form = { 0, 1, 1, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VDUP8d {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVDup VDUPD
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 0, 0, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$V);
  dag InOperandList = (ins GPR:$R, pred:$p);
  string AsmString = "vdup${p}.8	$V, $R";
  list<dag> Pattern = [(set DPR:$V, (v8i8 (NEONvdup (i32 GPR:$R))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVIS;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NDupFrm;
  bits<6> Form = { 0, 1, 1, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VDUP8q {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVDup VDUPQ
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 0, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$V);
  dag InOperandList = (ins GPR:$R, pred:$p);
  string AsmString = "vdup${p}.8	$V, $R";
  list<dag> Pattern = [(set QPR:$V, (v16i8 (NEONvdup (i32 GPR:$R))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVIS;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NDupFrm;
  bits<6> Form = { 0, 1, 1, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VDUPLN16d {	// Instruction InstTemplate Encoding InstARM NeonI NDataI NVDupLane VDUPLND
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, lane{1}, lane{0}, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vdup${p}.16	$Vd, $Vm$lane";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvduplane (v4i16 DPR:$Vm), imm:$lane)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVDupLnFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VDUPLN16q {	// Instruction InstTemplate Encoding InstARM NeonI NDataI NVDupLane VDUPLNQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, lane{1}, lane{0}, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vdup${p}.16	$Vd, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvduplane (v4i16 DPR:$Vm), VectorIndex32:$lane)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVDupLnFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VDUPLN32d {	// Instruction InstTemplate Encoding InstARM NeonI NDataI NVDupLane VDUPLND
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, lane{0}, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vdup${p}.32	$Vd, $Vm$lane";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvduplane (v2i32 DPR:$Vm), imm:$lane)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVDupLnFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<1> lane = { ? };
  string NAME = ?;
}
def VDUPLN32q {	// Instruction InstTemplate Encoding InstARM NeonI NDataI NVDupLane VDUPLNQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, lane{0}, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vdup${p}.32	$Vd, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvduplane (v2i32 DPR:$Vm), VectorIndex32:$lane)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVDupLnFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<1> lane = { ? };
  string NAME = ?;
}
def VDUPLN8d {	// Instruction InstTemplate Encoding InstARM NeonI NDataI NVDupLane VDUPLND
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, lane{2}, lane{1}, lane{0}, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, VectorIndex8:$lane, pred:$p);
  string AsmString = "vdup${p}.8	$Vd, $Vm$lane";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvduplane (v8i8 DPR:$Vm), imm:$lane)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVDupLnFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VDUPLN8q {	// Instruction InstTemplate Encoding InstARM NeonI NDataI NVDupLane VDUPLNQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, lane{2}, lane{1}, lane{0}, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, VectorIndex8:$lane, pred:$p);
  string AsmString = "vdup${p}.8	$Vd, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvduplane (v8i8 DPR:$Vm), VectorIndex32:$lane)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVDupLnFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VEORd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX N3VDX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "veor${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (xor (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VEORq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX N3VQX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "veor${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (xor (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VEXTd16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V VEXTd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, index{1}, index{0}, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, imm0_3:$index, pred:$p);
  string AsmString = "vext${p}.16	$Vd, $Vn, $Vm, $index";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvext (v4i16 DPR:$Vn), (v4i16 DPR:$Vm), imm:$index)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VEXTD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVExtFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<3> index = { ?, ?, ? };
  string NAME = ?;
}
def VEXTd32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V VEXTd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, index{0}, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, imm0_1:$index, pred:$p);
  string AsmString = "vext${p}.32	$Vd, $Vn, $Vm, $index";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvext (v2i32 DPR:$Vn), (v2i32 DPR:$Vm), imm:$index)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VEXTD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVExtFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<3> index = { ?, ?, ? };
  string NAME = ?;
}
def VEXTd8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V VEXTd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, index{2}, index{1}, index{0}, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, imm0_7:$index, pred:$p);
  string AsmString = "vext${p}.8	$Vd, $Vn, $Vm, $index";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvext (v8i8 DPR:$Vn), (v8i8 DPR:$Vm), imm:$index)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VEXTD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVExtFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<3> index = { ?, ?, ? };
  string NAME = ?;
}
def VEXTq16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V VEXTq
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, index{2}, index{1}, index{0}, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, imm0_15:$index, pred:$p);
  string AsmString = "vext${p}.16	$Vd, $Vn, $Vm, $index";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvext (v8i16 QPR:$Vn), (v8i16 QPR:$Vm), imm:$index)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VEXTQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVExtFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<4> index = { ?, ?, ?, ? };
  string NAME = ?;
}
def VEXTq32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V VEXTq
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, index{1}, index{0}, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, imm0_15:$index, pred:$p);
  string AsmString = "vext${p}.32	$Vd, $Vn, $Vm, $index";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvext (v4i32 QPR:$Vn), (v4i32 QPR:$Vm), imm:$index)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VEXTQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVExtFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<4> index = { ?, ?, ?, ? };
  string NAME = ?;
}
def VEXTq64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V VEXTq
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, index{0}, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, imm0_15:$index, pred:$p);
  string AsmString = "vext${p}.64	$Vd, $Vn, $Vm, $index";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvext (v2i64 QPR:$Vn), (v2i64 QPR:$Vm), imm:$index)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VEXTQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVExtFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<4> index = { ?, ?, ?, ? };
  string NAME = ?;
}
def VEXTq8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V VEXTq
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, index{3}, index{2}, index{1}, index{0}, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, imm0_15:$index, pred:$p);
  string AsmString = "vext${p}.8	$Vd, $Vn, $Vm, $index";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvext (v16i8 QPR:$Vn), (v16i8 QPR:$Vm), imm:$index)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VEXTQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVExtFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<4> index = { ?, ?, ?, ? };
  string NAME = ?;
}
def VFMAD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vfma${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), (f64 DPR:$Ddin)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC64;
  list<SchedReadWrite> SchedRW = [WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Ddin = $Dd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMAH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vfma${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fadd_mlx (fmul_su HPR:$Sn, HPR:$Sm), HPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC16;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMAS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI ASbIn RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vfma${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP4, DontUseNEONForFP, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC32;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMAfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vfma${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fadd_mlx DPR:$src1, (v2f32 (fmul_su DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasVFP4, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMAfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vfma${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fadd_mlx QPR:$src1, (v4f32 (fmul_su QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasVFP4, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMAhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vfma${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fadd DPR:$src1, (v4f16 (fmul DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMAhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vfma${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fadd QPR:$src1, (v8f16 (fmul QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMSD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vfms${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn, DPR:$Dm)), (f64 DPR:$Ddin)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC64;
  list<SchedReadWrite> SchedRW = [WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Ddin = $Dd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMSH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vfms${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fadd_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)), HPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC16;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMSS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI ASbIn RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vfms${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), SPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP4, DontUseNEONForFP, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC32;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMSfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vfms${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fsub_mlx DPR:$src1, (v2f32 (fmul_su DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasVFP4, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMSfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vfms${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fsub_mlx QPR:$src1, (v4f32 (fmul_su QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasVFP4, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMShd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vfms${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fsub DPR:$src1, (v4f16 (fmul DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFMShq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vfms${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fsub QPR:$src1, (v8f16 (fmul QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFNMAD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 0, 1, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vfnma${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fsub_mlx (fneg (fmul_su DPR:$Dn, DPR:$Dm)), (f64 DPR:$Ddin)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC64;
  list<SchedReadWrite> SchedRW = [WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Ddin = $Dd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFNMAH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vfnma${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fsub_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)), HPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC16;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFNMAS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vfnma${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), SPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP4, DontUseNEONForFP, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC32;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFNMSD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 0, 1, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vfnms${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), (f64 DPR:$Ddin)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC64;
  list<SchedReadWrite> SchedRW = [WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Ddin = $Dd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFNMSH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vfnms${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fsub_mlx (fmul_su HPR:$Sn, HPR:$Sm), HPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC16;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFNMSS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vfnms${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP4, DontUseNEONForFP, UseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpFMAC32;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VFPBinaryFrm {	// Format
  bits<6> Value = { 0, 1, 0, 0, 0, 0 };
  string NAME = ?;
}
def VFPConv1Frm {	// Format
  bits<6> Value = { 0, 1, 0, 0, 0, 1 };
  string NAME = ?;
}
def VFPConv2Frm {	// Format
  bits<6> Value = { 0, 1, 0, 0, 1, 0 };
  string NAME = ?;
}
def VFPConv3Frm {	// Format
  bits<6> Value = { 0, 1, 0, 0, 1, 1 };
  string NAME = ?;
}
def VFPConv4Frm {	// Format
  bits<6> Value = { 0, 1, 0, 1, 0, 0 };
  string NAME = ?;
}
def VFPConv5Frm {	// Format
  bits<6> Value = { 0, 1, 0, 1, 0, 1 };
  string NAME = ?;
}
def VFPDomain {	// Domain
  bits<3> Value = { 0, 0, 1 };
  string NAME = ?;
}
def VFPLdStFrm {	// Format
  bits<6> Value = { 0, 1, 0, 1, 1, 0 };
  string NAME = ?;
}
def VFPLdStMulFrm {	// Format
  bits<6> Value = { 0, 1, 0, 1, 1, 1 };
  string NAME = ?;
}
def VFPMiscFrm {	// Format
  bits<6> Value = { 0, 1, 1, 0, 0, 0 };
  string NAME = ?;
}
def VFPNeonA8Domain {	// Domain
  bits<3> Value = { 1, 0, 1 };
  string NAME = ?;
}
def VFPNeonDomain {	// Domain
  bits<3> Value = { 0, 1, 1 };
  string NAME = ?;
}
def VFPUnaryFrm {	// Format
  bits<6> Value = { 0, 0, 1, 1, 1, 1 };
  string NAME = ?;
}
def VGETLNi32 {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVGetLane Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 0, lane{0}, 1, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$R);
  dag InOperandList = (ins DPR:$V, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmov${p}.32	$R, $V$lane";
  list<dag> Pattern = [(set GPR:$R, (extractelt (v2i32 DPR:$V), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasFastVGETLNi32];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVSI;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NGetLnFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VGETLNs16 {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVGetLane
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 0, lane{1}, 1, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, lane{0}, 1, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$R);
  dag InOperandList = (ins DPR:$V, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmov${p}.s16	$R, $V$lane";
  list<dag> Pattern = [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVSI;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NGetLnFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VGETLNs8 {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVGetLane
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 1, lane{2}, 1, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, lane{1}, lane{0}, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$R);
  dag InOperandList = (ins DPR:$V, VectorIndex8:$lane, pred:$p);
  string AsmString = "vmov${p}.s8	$R, $V$lane";
  list<dag> Pattern = [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVSI;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NGetLnFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VGETLNu16 {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVGetLane
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 0, lane{1}, 1, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, lane{0}, 1, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$R);
  dag InOperandList = (ins DPR:$V, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmov${p}.u16	$R, $V$lane";
  list<dag> Pattern = [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVSI;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NGetLnFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VGETLNu8 {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVGetLane
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, lane{2}, 1, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, lane{1}, lane{0}, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$R);
  dag InOperandList = (ins DPR:$V, VectorIndex8:$lane, pred:$p);
  string AsmString = "vmov${p}.u8	$R, $V$lane";
  list<dag> Pattern = [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVSI;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NGetLnFrm;
  bits<6> Form = { 0, 1, 1, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VHADDsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vhadds (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VHADDsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vhadds (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHADDsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vhadds (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHADDsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vhadds (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHADDsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vhadds (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHADDsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vhadds (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VHADDuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vhaddu (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VHADDuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vhaddu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHADDuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vhaddu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHADDuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vhaddu (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHADDuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vhaddu (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHADDuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhadd${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vhaddu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VHSUBsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vhsubs (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VHSUBsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vhsubs (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHSUBsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vhsubs (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHSUBsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vhsubs (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHSUBsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vhsubs (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHSUBsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vhsubs (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VHSUBuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vhsubu (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VHSUBuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vhsubu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHSUBuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vhsubu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHSUBuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vhsubu (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHSUBuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vhsubu (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VHSUBuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vhsub${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vhsubu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VINSH {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vins.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VJCVT {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IsD_Encode Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vjcvt${p}.s32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasV8_3a];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDI;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1DUPd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [(set VecListOneDAllLanes:$Vd, (v4i16 (NEONvdup (i32 (extloadi16 addrmode6dupalign16:$Rn)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1DUPd16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1DUPd16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1DUPd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [(set VecListOneDAllLanes:$Vd, (v2i32 (NEONvdup (i32 (load addrmode6dupalign32:$Rn)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1DUPd32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 1, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1DUPd32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 1, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1DUPd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalignNone:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [(set VecListOneDAllLanes:$Vd, (v8i8 (NEONvdup (i32 (extloadi8 addrmode6dupalignNone:$Rn)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1DUPd8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalignNone:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1DUPd8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneDAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalignNone:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1DUPq16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD1QDUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [(set VecListDPairAllLanes:$Vd, (v8i16 (NEONvdup (i32 (extloadi16 addrmode6dupalign16:$Rn)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1DUPq16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, 1, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1DUPq16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 1, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1DUPq32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD1QDUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 1, 0, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [(set VecListDPairAllLanes:$Vd, (v4i32 (NEONvdup (i32 (load addrmode6dupalign32:$Rn)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1DUPq32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 1, 0, 1, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1DUPq32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 1, 0, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1DUPq8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD1QDUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalignNone:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [(set VecListDPairAllLanes:$Vd, (v16i8 (NEONvdup (i32 (extloadi8 addrmode6dupalignNone:$Rn)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1DUPq8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, 1, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalignNone:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1DUPq8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, 0, 0, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalignNone:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1dupu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1LNd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD1LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, lane{1}, lane{0}, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "vld1${p}.16	\{$Vd[$lane]\}, $Rn";
  list<dag> Pattern = [(set DPR:$Vd, (vector_insert (v4i16 DPR:$src), (i32 (extloadi16 addrmode6:$Rn)), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1ln;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD1LNd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD1LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, lane{1}, lane{0}, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "vld1${p}.16	\{$Vd[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $Vd, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD1LNd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD1LN32
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, lane{0}, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "vld1${p}.32	\{$Vd[$lane]\}, $Rn";
  list<dag> Pattern = [(set DPR:$Vd, (vector_insert (v2i32 DPR:$src), (i32 (load addrmode6oneL32:$Rn)), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD1LNd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD1LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, lane{0}, 0, Rn{4}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "vld1${p}.32	\{$Vd[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $Vd, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD1LNd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD1LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, lane{2}, lane{1}, lane{0}, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "vld1${p}.8	\{$Vd[$lane]\}, $Rn";
  list<dag> Pattern = [(set DPR:$Vd, (vector_insert (v8i8 DPR:$src), (i32 (extloadi8 addrmode6:$Rn)), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1ln;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD1LNd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD1LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, lane{2}, lane{1}, lane{0}, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "vld1${p}.8	\{$Vd[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $Vd, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD1LNdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, pred:$p);
  string AsmString = "vld1${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vld1${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld1${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, pred:$p);
  string AsmString = "vld1${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vld1${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld1${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNq16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNPseudo Sched VLD1QLNPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set QPR:$dst, (vector_insert (v8i16 QPR:$src), (i32 (extloadi16 addrmode6:$addr)), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNq16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNq32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNPseudo Sched VLD1QLNPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set QPR:$dst, (vector_insert (v4i32 QPR:$src), (i32 (load addrmode6:$addr)), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNq32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNq8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNPseudo Sched VLD1QLNPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set QPR:$dst, (vector_insert (v16i8 QPR:$src), (i32 (extloadi8 addrmode6:$addr)), imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1LNq8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1d16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d16Q {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D4
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d16Qwb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d16Qwb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d16T {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d16Twb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d16Twb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d32Q {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D4
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d32Qwb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d32Qwb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d32T {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d32Twb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d32Twb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d64 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d64Q {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D4
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d64QPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1d64QPseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1d64QPseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBregisterPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1d64Qwb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d64Qwb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d64T {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d64TPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1d64TPseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1d64TPseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBregisterPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD1d64Twb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d64Twb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d64wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d64wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d8Q {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D4
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d8Qwb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d8Qwb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d8T {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1D3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1d8Twb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d8Twb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListThreeD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1d8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1d8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListOneD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1q16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1q16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1q16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1q32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1q32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1q32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1q64 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1q64wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1q64wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.64	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD1q8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD1Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD1q8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD1q8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2DUPd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2DUPd16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 1, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2DUPd16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2DUPd16x2 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 1, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpacedAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2DUPd16x2wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 1, 1, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpacedAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2DUPd16x2wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 1, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpacedAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign32:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2DUPd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2DUPd32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 1, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2DUPd32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 1, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2DUPd32x2 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 1, 0, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpacedAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2DUPd32x2wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 1, 0, 1, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpacedAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2DUPd32x2wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 1, 0, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpacedAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2DUPd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2DUPd8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2DUPd8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2DUPd8x2 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 0, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpacedAllLanes:$Vd);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2DUPd8x2wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 0, 1, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpacedAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2DUPd8x2wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, 0, 0, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpacedAllLanes:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign16:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2LNd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, lane{1}, lane{0}, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src1 = $Vd, $src2 = $dst2";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNd16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNd16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, lane{1}, lane{0}, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, lane{0}, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src1 = $Vd, $src2 = $dst2";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNd32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNd32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, lane{0}, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, lane{2}, lane{1}, lane{0}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.8	\{$Vd[$lane], $dst2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src1 = $Vd, $src2 = $dst2";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNd8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNd8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, lane{2}, lane{1}, lane{0}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.8	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vld2${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld2${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, pred:$p);
  string AsmString = "vld2${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vld2${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld2${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, pred:$p);
  string AsmString = "vld2${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNq16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, lane{1}, lane{0}, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src1 = $Vd, $src2 = $dst2";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNq16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNq16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNq16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, lane{1}, lane{0}, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNq32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, lane{0}, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src1 = $Vd, $src2 = $dst2";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNq32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2ln;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNq32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD1];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNq32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, lane{0}, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD2LNqAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vld2${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNqAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld2${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNqWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vld2${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNqWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld2${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNqWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2LNqWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2b16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpaced:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2b16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpaced:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2b16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpaced:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2b32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpaced:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2b32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpaced:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2b32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpaced:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2b8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpaced:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2b8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpaced:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2b8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPairSpaced:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2d16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2d16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2d16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2d32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2d32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2d32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2d8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2d8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2d8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2u;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2q16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2q16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2q16PseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2q16PseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBregisterPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2q16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2q16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2q32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2q32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2q32PseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2q32PseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBregisterPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2q32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2q32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD2q8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD2q8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2q8PseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2q8PseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBregisterPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD2q8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VLD2q8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs VecListFourD:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "vld2${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD2x2u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3DUPd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3DUPd16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPd16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3DUPd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3DUPd32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPd32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 1, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3DUPd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3DUPd8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPd8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3DUPdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPq16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3DUPq16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3DUPq32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3DUPq32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 1, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3DUPq8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3DUPq8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6dupalign64:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3DUPqAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPqAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPqAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPqWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPqWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPqWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPqWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPqWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3DUPqWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, lane{1}, lane{0}, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNd16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNd16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, lane{1}, lane{0}, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, lane{0}, 0, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNd32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNd32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, lane{0}, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, lane{2}, lane{1}, lane{0}, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNd8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNd8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, lane{2}, lane{1}, lane{0}, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNq16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, lane{1}, lane{0}, 1, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNq16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNq16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNq16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, lane{1}, lane{0}, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNq32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, lane{0}, 1, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNq32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNq32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNq32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, lane{0}, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD3LNqAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNqAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNqWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNqWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNqWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3LNqWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3d16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3d16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3d16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3d16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3d32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3d32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3d32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3d32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3d8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3d8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3d8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3d8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3dAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3dAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3dAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3dWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3dWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3dWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3dWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3dWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3dWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3q16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3q16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3q16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3q16oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3q16oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3q32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3q32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3q32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3q32oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3q32oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3q8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD3q8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3q8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD3q8oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3q8oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD3u;
  list<SchedReadWrite> SchedRW = [WriteVLD3];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3qAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3qAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3qAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3qWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3qWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3qWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3qWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3qWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD3qWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld3${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD4DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4DUPd16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPd16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6dup:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4DUPd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD4DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 1, Rn{5}, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4DUPd32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPd32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 1, Rn{5}, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6dup:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4DUPd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD4DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4DUPd8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPd8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6dup:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4DUPdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPq16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD4DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 1, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4DUPq16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 1, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6dup:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4DUPq32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD4DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 1, Rn{5}, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4DUPq32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 1, Rn{5}, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6dup:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4DUPq8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VLD4DUP
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 0, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6dup:$Rn, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dup;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4DUPq8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DUPWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 0, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6dup:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4dupu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4DupInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4DUPqAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPqAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPqAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPqWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPqWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPqWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPqWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPqWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4DUPqWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, lane{1}, lane{0}, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNd16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNd16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, lane{1}, lane{0}, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, lane{0}, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNd32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNd32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, lane{0}, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, lane{2}, lane{1}, lane{0}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNd8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNd8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, lane{2}, lane{1}, lane{0}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNq16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, lane{1}, lane{0}, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNq16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNq16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNq16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, lane{1}, lane{0}, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNq32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VLD4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, lane{0}, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNq32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4ln;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNq32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = [WriteVLD2];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNq32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VLD4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, lane{0}, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLD4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VLD4LNqAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNqAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNqWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNqWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNqWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4LNqWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4d16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4d16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4d16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4d16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4d32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4d32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4d32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4d32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4d8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4d8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4d8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4d8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4dAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4dAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4dAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4dWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4dWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4dWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4dWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4dWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4dWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4q16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4q16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4q16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4q16oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4q16oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4q32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4q32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4q32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4q32oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4q32oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4q8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4);
  dag InOperandList = (ins addrmode6:$Rn, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VLD4q8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4q8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VLD4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, pred:$p);
  string AsmString = "vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VLD4q8oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4q8oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VLDQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QQQQPR:$dst, GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD4u;
  list<SchedReadWrite> SchedRW = [WriteVLD4];
  string Constraints = "$addr.addr = $wb, $src = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4qAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4qAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4qAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4qWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4qWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4qWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4qWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4qWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLD4qWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vld4${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLDMDDB_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXDI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, 0, regs{12}, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "vldmdb${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLDMDIA {	// Instruction InstTemplate Encoding InstARM VFPXI AXDI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, regs{12}, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "vldmia${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLDMDIA_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXDI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, regs{12}, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "vldmia${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLDMQIA {	// Instruction InstTemplate Encoding InstARM PseudoVFPLdStM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPair:$dst);
  dag InOperandList = (ins GPR:$Rn, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set DPair:$dst, (v2f64 (word_alignedload GPR:$Rn)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VLDMSDB_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXSI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, 0, regs{8}, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{12}, regs{11}, regs{10}, regs{9}, 1, 0, 1, 0, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops);
  string AsmString = "vldmdb${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLDMSIA {	// Instruction InstTemplate Encoding InstARM VFPXI AXSI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, regs{8}, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{12}, regs{11}, regs{10}, regs{9}, 1, 0, 1, 0, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops);
  string AsmString = "vldmia${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLDMSIA_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXSI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, regs{8}, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{12}, regs{11}, regs{10}, regs{9}, 1, 0, 1, 0, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops);
  string AsmString = "vldmia${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLDRD {	// Instruction InstTemplate Encoding InstARM VFPI ADI5
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, Dd{4}, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins addrmode5:$addr, pred:$p);
  string AsmString = "vldr${p}	$Dd, $addr";
  list<dag> Pattern = [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode5;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLDRH {	// Instruction InstTemplate Encoding InstARM VFPI AHI5 Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, Sd{0}, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins addrmode5fp16:$addr, pred:$p);
  string AsmString = "vldr${p}.16	$Sd, $addr";
  list<dag> Pattern = [(set HPR:$Sd, (alignedload16 addrmode5fp16:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode5FP16;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLDRS {	// Instruction InstTemplate Encoding InstARM VFPI ASI5
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, Sd{0}, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins addrmode5:$addr, pred:$p);
  string AsmString = "vldr${p}	$Sd, $addr";
  list<dag> Pattern = [(set SPR:$Sd, (alignedload32 addrmode5:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode5;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLLDM {	// Instruction InstTemplate Encoding InstARM VFPXI AXSI4 Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, pred:$p);
  string AsmString = "vlldm${p}	$Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8MMainline, Has8MSecExt];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VLSTM {	// Instruction InstTemplate Encoding InstARM VFPXI AXSI4 Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, pred:$p);
  string AsmString = "vlstm${p}	$Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8MMainline, Has8MSecExt];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXNMD {	// Instruction InstTemplate Encoding InstARM VFPXI ADbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Dd{4}, 0, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm);
  string AsmString = "vmaxnm.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (f64 (fmaxnum (f64 DPR:$Dn), (f64 DPR:$Dm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXNMH {	// Instruction InstTemplate Encoding InstARM VFPXI AHbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm);
  string AsmString = "vmaxnm.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fmaxnum HPR:$Sn, HPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXNMNDf {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm);
  string AsmString = "vmaxnm.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fmaxnum (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXNMNDh {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm);
  string AsmString = "vmaxnm.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fmaxnum (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXNMNQf {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm);
  string AsmString = "vmaxnm.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fmaxnum (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXNMNQh {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm);
  string AsmString = "vmaxnm.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fmaxnum (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXNMS {	// Instruction InstTemplate Encoding InstARM VFPXI ASbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm);
  string AsmString = "vmaxnm.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fmaxnum SPR:$Sn, SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fmaxnan (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fmaxnan (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fmaxnan (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fmaxnan (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (smax (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (smax (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMAXsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (smax (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMAXsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (smax (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMAXsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (smax (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMAXsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (smax (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (umax (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMAXuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (umax (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMAXuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (umax (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMAXuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (umax (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMAXuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (umax (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMAXuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmax${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (umax (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINNMD {	// Instruction InstTemplate Encoding InstARM VFPXI ADbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Dd{4}, 0, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm);
  string AsmString = "vminnm.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (f64 (fminnum (f64 DPR:$Dn), (f64 DPR:$Dm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINNMH {	// Instruction InstTemplate Encoding InstARM VFPXI AHbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm);
  string AsmString = "vminnm.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fminnum HPR:$Sn, HPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINNMNDf {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm);
  string AsmString = "vminnm.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fminnum (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINNMNDh {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm);
  string AsmString = "vminnm.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fminnum (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINNMNQf {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm);
  string AsmString = "vminnm.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fminnum (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINNMNQh {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm);
  string AsmString = "vminnm.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fminnum (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINNMS {	// Instruction InstTemplate Encoding InstARM VFPXI ASbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm);
  string AsmString = "vminnm.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fminnum SPR:$Sn, SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fminnan (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fminnan (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fminnan (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fminnan (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (smin (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (smin (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMINsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (smin (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMINsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (smin (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMINsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (smin (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMINsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (smin (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (umin (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMINuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (umin (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMINuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (umin (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMINuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (umin (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMINuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (umin (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VMINuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmin${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (umin (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Dd{4}, 0, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vmla${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), (f64 DPR:$Ddin)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC64;
  list<SchedReadWrite> SchedRW = [WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Ddin = $Dd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI RegConstraint Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vmla${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fadd_mlx (fmul_su HPR:$Sn, HPR:$Sm), HPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLALslsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VLMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmlal${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 QPR:$src1), (v2i64 (NEONvmulls (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLALslsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VLMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmlal${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 QPR:$src1), (v4i32 (NEONvmulls (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLALsluv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VLMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmlal${p}.u32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 QPR:$src1), (v2i64 (NEONvmullu (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLALsluv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VLMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmlal${p}.u16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 QPR:$src1), (v4i32 (NEONvmullu (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLALsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlal${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 QPR:$src1), (v2i64 (NEONvmulls (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLALsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlal${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 QPR:$src1), (v4i32 (NEONvmulls (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLALsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlal${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v8i16 QPR:$src1), (v8i16 (NEONvmulls (v8i8 DPR:$Vn), (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLALuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlal${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v2i64 QPR:$src1), (v2i64 (NEONvmullu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLALuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlal${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v4i32 QPR:$src1), (v4i32 (NEONvmullu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLALuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlal${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (add (v8i16 QPR:$src1), (v8i16 (NEONvmullu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI ASbIn RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vmla${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC32;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fadd_mlx DPR:$src1, (v2f32 (fmul_su DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fadd_mlx QPR:$src1, (v4f32 (fmul_su QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fadd_mlx DPR:$src1, (v4f16 (fmul_su DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fadd_mlx QPR:$src1, (v8f16 (fmul_su QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAslfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDMulOpSL Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmla${p}.f32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2f32 DPR:$Vd), (v2f32 (fadd_mlx (v2f32 DPR:$src1), (v2f32 (fmul_su DPR:$Vn, (v2f32 (NEONvduplane (v2f32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLAslfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQMulOpSL Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmla${p}.f32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4f32 QPR:$Vd), (v4f32 (fadd_mlx (v4f32 QPR:$src1), (v4f32 (fmul_su QPR:$Vn, (v4f32 (NEONvduplane (v2f32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLAslhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDMulOpSL16 Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmla${p}.f16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4f16 DPR:$Vd), (v4f16 (fadd (v4f16 DPR:$src1), (v4f16 (fmul DPR:$Vn, (v4f16 (NEONvduplane (v4f16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFPVMLx];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLAslhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQMulOpSL16 Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmla${p}.f16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8f16 QPR:$Vd), (v8f16 (fadd (v8f16 QPR:$src1), (v8f16 (fmul QPR:$Vn, (v8f16 (NEONvduplane (v4f16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFPVMLx];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLAslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmla${p}.i32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i32 DPR:$Vd), (v2i32 (add (v2i32 DPR:$src1), (v2i32 (mul DPR:$Vn, (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLAslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmla${p}.i16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i16 DPR:$Vd), (v4i16 (add (v4i16 DPR:$src1), (v4i16 (mul DPR:$Vn, (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLAslv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmla${p}.i32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (add (v4i32 QPR:$src1), (v4i32 (mul QPR:$Vn, (v4i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLAslv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmla${p}.i16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8i16 QPR:$Vd), (v8i16 (add (v8i16 QPR:$src1), (v8i16 (mul QPR:$Vn, (v8i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLAv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (add QPR:$src1, (v16i8 (mul QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (add DPR:$src1, (v2i32 (mul DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (add DPR:$src1, (v4i16 (mul DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (add QPR:$src1, (v4i32 (mul QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (add QPR:$src1, (v8i16 (mul QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLAv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmla${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (add DPR:$src1, (v8i8 (mul DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Dd{4}, 0, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vmls${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn, DPR:$Dm)), (f64 DPR:$Ddin)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC64;
  list<SchedReadWrite> SchedRW = [WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Ddin = $Dd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI RegConstraint Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vmls${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fadd_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)), HPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSLslsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VLMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmlsl${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v2i64 QPR:$src1), (v2i64 (NEONvmulls (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLSLslsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VLMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmlsl${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v4i32 QPR:$src1), (v4i32 (NEONvmulls (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLSLsluv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VLMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmlsl${p}.u32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v2i64 QPR:$src1), (v2i64 (NEONvmullu (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLSLsluv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VLMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmlsl${p}.u16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v4i32 QPR:$src1), (v4i32 (NEONvmullu (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLSLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlsl${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v2i64 QPR:$src1), (v2i64 (NEONvmulls (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlsl${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v4i32 QPR:$src1), (v4i32 (NEONvmulls (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlsl${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v8i16 QPR:$src1), (v8i16 (NEONvmulls (v8i8 DPR:$Vn), (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlsl${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v2i64 QPR:$src1), (v2i64 (NEONvmullu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlsl${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v4i32 QPR:$src1), (v4i32 (NEONvmullu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmlsl${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v8i16 QPR:$src1), (v8i16 (NEONvmullu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI ASbIn RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vmls${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), SPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC32;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fsub_mlx DPR:$src1, (v2f32 (fmul_su DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fsub_mlx QPR:$src1, (v4f32 (fmul_su QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLShd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fsub DPR:$src1, (v4f16 (fmul DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLShq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fsub QPR:$src1, (v8f16 (fmul QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSslfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDMulOpSL Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmls${p}.f32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2f32 DPR:$Vd), (v2f32 (fsub_mlx (v2f32 DPR:$src1), (v2f32 (fmul_su DPR:$Vn, (v2f32 (NEONvduplane (v2f32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLSslfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQMulOpSL Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmls${p}.f32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4f32 QPR:$Vd), (v4f32 (fsub_mlx (v4f32 QPR:$src1), (v4f32 (fmul_su QPR:$Vn, (v4f32 (NEONvduplane (v2f32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLSslhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDMulOpSL16 Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmls${p}.f16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4f16 DPR:$Vd), (v4f16 (fsub (v4f16 DPR:$src1), (v4f16 (fmul DPR:$Vn, (v4f16 (NEONvduplane (v4f16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFPVMLx];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLSslhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQMulOpSL16 Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmls${p}.f16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8f16 QPR:$Vd), (v8f16 (fsub (v8f16 QPR:$src1), (v8f16 (fmul QPR:$Vn, (v8f16 (NEONvduplane (v4f16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16, UseFPVMLx];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLSslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmls${p}.i32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i32 DPR:$Vd), (v2i32 (sub (v2i32 DPR:$src1), (v2i32 (mul DPR:$Vn, (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLSslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmls${p}.i16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i16 DPR:$Vd), (v4i16 (sub (v4i16 DPR:$src1), (v4i16 (mul DPR:$Vn, (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLSslv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmls${p}.i32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (sub (v4i32 QPR:$src1), (v4i32 (mul QPR:$Vn, (v4i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMLSslv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmls${p}.i16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8i16 QPR:$Vd), (v8i16 (sub (v8i16 QPR:$src1), (v8i16 (mul QPR:$Vn, (v8i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMLSv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (sub QPR:$src1, (v16i8 (mul QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (sub DPR:$src1, (v2i32 (mul DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (sub DPR:$src1, (v4i16 (mul DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (sub QPR:$src1, (v4i32 (mul QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (sub QPR:$src1, (v8i16 (mul QPR:$Vn, QPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMLSv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDMulOp
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmls${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (sub DPR:$src1, (v8i8 (mul DPR:$Vn, DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 0, 0, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vmov${p}.f64	$Dd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVD0 {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 NEONimmAllZerosV))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasZCZ];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 50;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg));
  string NAME = ?;
}
def VMOVDRR {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI AVConv5I Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 0, 1, 0, 0, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 1, 0, 0, Dm{4}, 1, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dm);
  dag InOperandList = (ins GPR:$Rt, GPR:$Rt2, pred:$p);
  string AsmString = "vmov${p}	$Dm, $Rt, $Rt2";
  list<dag> Pattern = [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 1;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMOVID;
  list<SchedReadWrite> SchedRW = [WriteFPMOV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv5Frm;
  bits<6> Form = { 0, 1, 0, 1, 0, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVDcc {	// Instruction InstTemplate PseudoInst RegConstraint Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set (f64 DPR:$Dd), (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Dn = $Dd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VMOVH {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vmovx.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVHR {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI AVConv4I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 0, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 0, 1, Sn{0}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sn);
  dag InOperandList = (ins GPR:$Rt, pred:$p);
  string AsmString = "vmov${p}.f16	$Sn, $Rt";
  list<dag> Pattern = [(set HPR:$Sn, (arm_vmovhr GPR:$Rt))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMOVIS;
  list<SchedReadWrite> SchedRW = [WriteFPMOV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv4Frm;
  bits<6> Form = { 0, 1, 0, 1, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vmovl${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (sext (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vmovl${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (sext (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vmovl${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (sext (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vmovl${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (zext (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vmovl${p}.u16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (zext (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vmovl${p}.u8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (zext (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vmovn${p}.i64	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (trunc (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVN;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vmovn${p}.i32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (trunc (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVN;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVNv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vmovn${p}.i16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (trunc (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVN;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVQ0 {	// Instruction InstTemplate PseudoInst ARMPseudoInst PseudoInstExpansion ARMPseudoExpand Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasZCZ];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 50;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg));
  string NAME = ?;
}
def VMOVRH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI AVConv2I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 0, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 0, 1, Sn{0}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins HPR:$Sn, pred:$p);
  string AsmString = "vmov${p}.f16	$Rt, $Sn";
  list<dag> Pattern = [(set GPR:$Rt, (arm_vmovrh HPR:$Sn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMOVSI;
  list<SchedReadWrite> SchedRW = [WriteFPMOV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv2Frm;
  bits<6> Form = { 0, 1, 0, 0, 1, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVRRD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI AVConv3I Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 0, 1, 0, 1, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 1, 0, 0, Dm{4}, 1, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rt2);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vmov${p}	$Rt, $Rt2, $Dm";
  list<dag> Pattern = [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 1;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMOVDI;
  list<SchedReadWrite> SchedRW = [WriteFPMOV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv3Frm;
  bits<6> Form = { 0, 1, 0, 0, 1, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVRRS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI AVConv3I Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 0, 1, 0, 1, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, src1{0}, 1, src1{4}, src1{3}, src1{2}, src1{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rt2);
  dag InOperandList = (ins SPR:$src1, SPR:$src2, pred:$p);
  string AsmString = "vmov${p}	$Rt, $Rt2, $src1, $src2";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMOVDI;
  list<SchedReadWrite> SchedRW = [WriteFPMOV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeVMOVRRS";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv3Frm;
  bits<6> Form = { 0, 1, 0, 0, 1, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> src1 = { ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVRS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI AVConv2I Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 0, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, Sn{0}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins SPR:$Sn, pred:$p);
  string AsmString = "vmov${p}	$Rt, $Sn";
  list<dag> Pattern = [(set GPR:$Rt, (bitconvert SPR:$Sn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMOVSI;
  list<SchedReadWrite> SchedRW = [WriteFPMOV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv2Frm;
  bits<6> Form = { 0, 1, 0, 0, 1, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vmov${p}.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVSR {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI AVConv4I Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 0, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, Sn{0}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sn);
  dag InOperandList = (ins GPR:$Rt, pred:$p);
  string AsmString = "vmov${p}	$Sn, $Rt";
  list<dag> Pattern = [(set SPR:$Sn, (bitconvert GPR:$Rt))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, UseVMOVSR];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMOVIS;
  list<SchedReadWrite> SchedRW = [WriteFPMOV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv4Frm;
  bits<6> Form = { 0, 1, 0, 1, 0, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVSRR {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConvXI AVConv5I Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 0, 1, 0, 0, src2{3}, src2{2}, src2{1}, src2{0}, src1{3}, src1{2}, src1{1}, src1{0}, 1, 0, 1, 0, 0, 0, dst1{0}, 1, dst1{4}, dst1{3}, dst1{2}, dst1{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst1, SPR:$dst2);
  dag InOperandList = (ins GPR:$src1, GPR:$src2, pred:$p);
  string AsmString = "vmov${p}	$dst1, $dst2, $src1, $src2";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMOVID;
  list<SchedReadWrite> SchedRW = [WriteFPMOV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeVMOVSRR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv5Frm;
  bits<6> Form = { 0, 1, 0, 1, 0, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> dst1 = { ?, ?, ?, ?, ? };
  bits<4> src1 = { ?, ?, ?, ? };
  bits<4> src2 = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVScc {	// Instruction InstTemplate PseudoInst RegConstraint Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set (f32 SPR:$Sd), (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Sn = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VMOVv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 1, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmSplatI8:$SIMM, pred:$p);
  string AsmString = "vmov${p}.i8	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 0, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmSplatI64:$SIMM, pred:$p);
  string AsmString = "vmov${p}.i64	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVv2f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 0, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmVMOVF32:$SIMM, pred:$p);
  string AsmString = "vmov${p}.f32	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, SIMM{11}, SIMM{10}, SIMM{9}, SIMM{8}, 0, 0, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmVMOVI32:$SIMM, pred:$p);
  string AsmString = "vmov${p}.i32	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 1, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmSplatI64:$SIMM, pred:$p);
  string AsmString = "vmov${p}.i64	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVv4f32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 1, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmVMOVF32:$SIMM, pred:$p);
  string AsmString = "vmov${p}.f32	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, SIMM{9}, 0, 0, 0, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmSplatI16:$SIMM, pred:$p);
  string AsmString = "vmov${p}.i16	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, SIMM{11}, SIMM{10}, SIMM{9}, SIMM{8}, 0, 1, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmVMOVI32:$SIMM, pred:$p);
  string AsmString = "vmov${p}.i32	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, SIMM{9}, 0, 0, 1, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmSplatI16:$SIMM, pred:$p);
  string AsmString = "vmov${p}.i16	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMOVv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, 0, 0, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmSplatI8:$SIMM, pred:$p);
  string AsmString = "vmov${p}.i8	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMRS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovFromVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins pred:$p);
  string AsmString = "vmrs${p}	$Rt, fpscr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (int_arm_get_fpscr))];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMRS_FPEXC {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovFromVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins pred:$p);
  string AsmString = "vmrs${p}	$Rt, fpexc";
  list<dag> Pattern = [];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMRS_FPINST {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovFromVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins pred:$p);
  string AsmString = "vmrs${p}	$Rt, fpinst";
  list<dag> Pattern = [];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMRS_FPINST2 {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovFromVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins pred:$p);
  string AsmString = "vmrs${p}	$Rt, fpinst2";
  list<dag> Pattern = [];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMRS_FPSID {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovFromVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins pred:$p);
  string AsmString = "vmrs${p}	$Rt, fpsid";
  list<dag> Pattern = [];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMRS_MVFR0 {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovFromVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins pred:$p);
  string AsmString = "vmrs${p}	$Rt, mvfr0";
  list<dag> Pattern = [];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMRS_MVFR1 {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovFromVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins pred:$p);
  string AsmString = "vmrs${p}	$Rt, mvfr1";
  list<dag> Pattern = [];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMRS_MVFR2 {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovFromVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins pred:$p);
  string AsmString = "vmrs${p}	$Rt, mvfr2";
  list<dag> Pattern = [];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMSR {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovToVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, src{3}, src{2}, src{1}, src{0}, 1, 0, 1, 0, 0, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$src, pred:$p);
  string AsmString = "vmsr${p}	fpscr, $src";
  list<dag> Pattern = [(int_arm_set_fpscr GPRnopc:$src)];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> src = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMSR_FPEXC {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovToVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, src{3}, src{2}, src{1}, src{0}, 1, 0, 1, 0, 0, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$src, pred:$p);
  string AsmString = "vmsr${p}	fpexc, $src";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> src = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMSR_FPINST {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovToVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 0, 1, 0, 0, 1, src{3}, src{2}, src{1}, src{0}, 1, 0, 1, 0, 0, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$src, pred:$p);
  string AsmString = "vmsr${p}	fpinst, $src";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> src = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMSR_FPINST2 {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovToVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 0, 1, 0, 1, 0, src{3}, src{2}, src{1}, src{0}, 1, 0, 1, 0, 0, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$src, pred:$p);
  string AsmString = "vmsr${p}	fpinst2, $src";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> src = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMSR_FPSID {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI MovToVFP
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, src{3}, src{2}, src{1}, src{0}, 1, 0, 1, 0, 0, ?, ?, 1, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$src, pred:$p);
  string AsmString = "vmsr${p}	fpsid, $src";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [FPSCR];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSTAT;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "DecodeForVMRSandVMSR";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPMiscFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> src = { ?, ?, ?, ? };
  string NAME = ?;
}
def VMULD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Dd{4}, 1, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vmul${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMUL64;
  list<SchedReadWrite> SchedRW = [WriteFPMUL64, ReadFPMUL, ReadFPMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Dn = $Dd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vmul${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fmul HPR:$Sn, HPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMUL16;
  list<SchedReadWrite> SchedRW = [WriteFPMUL32, ReadFPMUL, ReadFPMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Sn = $Sd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULLp64 {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp N3VLIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm);
  string AsmString = "vmull.p64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vmullp (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasCrypto];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULLp8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmull${p}.p8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vmullp (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULLslsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VLSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmull${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvmulls (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMULLslsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VLSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmull${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvmulls (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMULLsluv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VLSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmull${p}.u32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvmullu (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMULLsluv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VLSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmull${p}.u16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvmullu (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMULLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmull${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvmulls (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmull${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvmulls (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmull${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvmulls (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmull${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvmullu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmull${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvmullu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmull${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvmullu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI ASbIn Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vmul${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMUL32;
  list<SchedReadWrite> SchedRW = [WriteFPMUL32, ReadFPMUL, ReadFPMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Sn = $Sd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fmul (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMULD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fmul (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMULQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fmul (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMULD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fmul (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VFMULQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULpd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.p8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vmulp (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULpq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.p8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vmulp (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULslfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmul${p}.f32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2f32 DPR:$Vd), (v2f32 (fmul (v2f32 DPR:$Vn), (v2f32 (NEONvduplane (v2f32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMULslfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmul${p}.f32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4f32 QPR:$Vd), (v4f32 (fmul (v4f32 QPR:$Vn), (v4f32 (NEONvduplane (v2f32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMULslhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDSL16 Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmul${p}.f16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4f16 DPR:$Vd), (v4f16 (fmul (v4f16 DPR:$Vn), (v4f16 (NEONvduplane (v4f16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMULslhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQSL16 Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmul${p}.f16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8f16 QPR:$Vd), (v8f16 (fmul (v8f16 QPR:$Vn), (v8f16 (NEONvduplane (v4f16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMULslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmul${p}.i32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i32 DPR:$Vd), (v2i32 (mul (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMULslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmul${p}.i16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i16 DPR:$Vd), (v4i16 (mul (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMULslv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmul${p}.i32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (mul (v4i32 QPR:$Vn), (v4i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VMULslv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmul${p}.i16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8i16 QPR:$Vd), (v8i16 (mul (v8i16 QPR:$Vn), (v8i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VMULv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (mul (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (mul (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (mul (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (mul (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (mul (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMULv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vmul${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (mul (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMVNd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N2VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vmvn${p}	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMVNq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N2VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vmvn${p}	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMVNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, SIMM{11}, SIMM{10}, SIMM{9}, SIMM{8}, 0, 0, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmVMOVI32:$SIMM, pred:$p);
  string AsmString = "vmvn${p}.i32	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMVNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, SIMM{9}, 0, 0, 0, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmSplatI16:$SIMM, pred:$p);
  string AsmString = "vmvn${p}.i16	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMVNv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, SIMM{11}, SIMM{10}, SIMM{9}, SIMM{8}, 0, 1, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmVMOVI32:$SIMM, pred:$p);
  string AsmString = "vmvn${p}.i32	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VMVNv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, SIMM{9}, 0, 0, 1, 1, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmSplatI16:$SIMM, pred:$p);
  string AsmString = "vmvn${p}.i16	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 0, 0, 1, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vneg${p}.f64	$Dd, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sm, pred:$p);
  string AsmString = "vneg${p}.f16	$Sd, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fneg HPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI ASuIn
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vneg${p}.f32	$Sd, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fneg SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpUNA32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGf32q {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fneg DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fneg QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGs16d {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VNEGD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (vnegd DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGs16q {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VNEGQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (vnegq QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGs32d {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VNEGD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (vnegd DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGs32q {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VNEGQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (vnegq QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGs8d {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VNEGD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (vnegd DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNEGs8q {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VNEGQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vneg${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (vnegq QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNMLAD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Dd{4}, 0, 1, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vnmla${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fsub_mlx (fneg (fmul_su DPR:$Dn, DPR:$Dm)), (f64 DPR:$Ddin)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC64;
  list<SchedReadWrite> SchedRW = [WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Ddin = $Dd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNMLAH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI RegConstraint Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vnmla${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fsub_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)), HPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNMLAS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vnmla${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), SPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC32;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNMLSD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Dd{4}, 0, 1, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vnmls${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), (f64 DPR:$Ddin)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC64;
  list<SchedReadWrite> SchedRW = [WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Ddin = $Dd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNMLSH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI RegConstraint Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vnmls${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fsub_mlx (fmul_su HPR:$Sn, HPR:$Sm), HPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNMLSS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI RegConstraint Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vnmls${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMAC32;
  list<SchedReadWrite> SchedRW = [WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL];
  string Constraints = "$Sdin = $Sd";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNMULD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Dd{4}, 1, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vnmul${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMUL64;
  list<SchedReadWrite> SchedRW = [WriteFPMUL64, ReadFPMUL, ReadFPMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNMULH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vnmul${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fneg (fmul HPR:$Sn, HPR:$Sm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMUL16;
  list<SchedReadWrite> SchedRW = [WriteFPMUL32, ReadFPMUL, ReadFPMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VNMULS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vnmul${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpMUL32;
  list<SchedReadWrite> SchedRW = [WriteFPMUL32, ReadFPMUL, ReadFPMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VORNd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vorn${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (or DPR:$Vn, (vnotd DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VORNq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vorn${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (or QPR:$Vn, (vnotq QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VORRd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX N3VDX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vorr${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (or (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VORRiv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, SIMM{10}, SIMM{9}, 1, 0, 0, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmSplatI32:$SIMM, DPR:$src, pred:$p);
  string AsmString = "vorr${p}.i32	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VORRiv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, SIMM{9}, 1, 0, 0, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins nImmSplatI16:$SIMM, DPR:$src, pred:$p);
  string AsmString = "vorr${p}.i16	$Vd, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VORRiv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, SIMM{10}, SIMM{9}, 1, 0, 1, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmSplatI32:$SIMM, QPR:$src, pred:$p);
  string AsmString = "vorr${p}.i32	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VORRiv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, SIMM{9}, 1, 0, 1, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmSplatI16:$SIMM, QPR:$src, pred:$p);
  string AsmString = "vorr${p}.i16	$Vd, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVImm;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeNEONModImmInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N1RegModImmFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<13> SIMM = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VORRq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N3VX N3VQX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vorr${p}	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (or (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vpadals (v8i16 QPR:$src1), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vpadals (v1i64 DPR:$src1), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vpadals (v2i32 DPR:$src1), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vpadals (v2i64 QPR:$src1), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vpadals (v4i32 QPR:$src1), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vpadals (v4i16 DPR:$src1), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.u8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vpadalu (v8i16 QPR:$src1), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vpadalu (v1i64 DPR:$src1), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.u16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vpadalu (v2i32 DPR:$src1), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vpadalu (v2i64 QPR:$src1), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.u16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vpadalu (v4i32 QPR:$src1), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADALuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, pred:$p);
  string AsmString = "vpadal${p}.u8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vpadalu (v4i16 DPR:$src1), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vpaddls (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vpaddls (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vpaddls (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vpaddls (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vpaddls (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vpaddls (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.u8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vpaddlu (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vpaddlu (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.u16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vpaddlu (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vpaddlu (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.u16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vpaddlu (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDLuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDPLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vpaddl${p}.u8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vpaddlu (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDf {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpadd${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vpadd (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDh {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpadd${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vpadd (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDi16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpadd${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vpadd (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDi32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpadd${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vpadd (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPADDi8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpadd${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vpadd (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMAXf {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmax${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vpmaxs (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMAXh {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmax${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vpmaxs (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMAXs16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmax${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vpmaxs (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMAXs32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmax${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vpmaxs (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMAXs8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmax${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vpmaxs (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMAXu16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmax${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vpmaxu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMAXu32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmax${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vpmaxu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMAXu8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmax${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vpmaxu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMINf {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmin${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vpmins (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMINh {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmin${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vpmins (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMINs16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmin${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vpmins (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMINs32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmin${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vpmins (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMINs8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmin${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vpmins (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMINu16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmin${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vpminu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMINu32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmin${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vpminu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VPMINu8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vpmin${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vpminu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQABSv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqabs${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqabs (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQABSv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vqabs${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqabs (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQABSv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vqabs${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqabs (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQABSv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqabs${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqabs (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQABSv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqabs${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqabs (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQABSv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vqabs${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqabs (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQADDsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqadds (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.s64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vqadds (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQADDsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqadds (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.s64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vqadds (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQADDsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqadds (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqadds (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqadds (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqadds (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqaddu (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.u64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vqaddu (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQADDuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqaddu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.u64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vqaddu (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQADDuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqaddu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqaddu (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqaddu (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQADDuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqadd${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqaddu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQDMLALslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VLInt3SL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqdmlal${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i64 QPR:$Vd), (v2i64 (null_frag (v2i64 QPR:$src1), (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQDMLALslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VLInt3SL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqdmlal${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (null_frag (v4i32 QPR:$src1), (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQDMLALv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqdmlal${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (null_frag (v2i64 QPR:$src1), (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQDMLALv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqdmlal${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (null_frag (v4i32 QPR:$src1), (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQDMLSLslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VLInt3SL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqdmlsl${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i64 QPR:$Vd), (v2i64 (null_frag (v2i64 QPR:$src1), (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQDMLSLslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VLInt3SL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqdmlsl${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (null_frag (v4i32 QPR:$src1), (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQDMLSLv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqdmlsl${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (null_frag (v2i64 QPR:$src1), (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQDMLSLv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqdmlsl${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (null_frag (v4i32 QPR:$src1), (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQDMULHslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDIntSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqdmulh${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i32 DPR:$Vd), (v2i32 (int_arm_neon_vqdmulh (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQDMULHslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDIntSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqdmulh${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i16 DPR:$Vd), (v4i16 (int_arm_neon_vqdmulh (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQDMULHslv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQIntSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqdmulh${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$Vn), (v4i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQDMULHslv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQIntSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqdmulh${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8i16 QPR:$Vd), (v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$Vn), (v8i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQDMULHv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqdmulh${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqdmulh (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQDMULHv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqdmulh${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqdmulh (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQDMULHv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqdmulh${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQDMULHv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqdmulh${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQDMULLslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VLIntSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqdmull${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i64 QPR:$Vd), (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQDMULLslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VLIntSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqdmull${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQDMULLv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqdmull${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQDMULLv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqdmull${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQMOVNsuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqmovun${p}.s64	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqmovnsu (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQMOVNsuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqmovun${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqmovnsu (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQMOVNsuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqmovun${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqmovnsu (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQMOVNsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqmovn${p}.s64	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqmovns (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQMOVNsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqmovn${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqmovns (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQMOVNsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqmovn${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqmovns (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQMOVNuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqmovn${p}.u64	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqmovnu (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQMOVNuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqmovn${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqmovnu (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQMOVNuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqmovn${p}.u16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqmovnu (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQNEGv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqneg${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqneg (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQNEGv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vqneg${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqneg (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQNEGv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vqneg${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqneg (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQNEGv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqneg${p}.s32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqneg (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQNEGv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vqneg${p}.s16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqneg (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQNEGv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vqneg${p}.s8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqneg (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VQUNAiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMLAHslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqrdmlah${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i32 DPR:$Vd), (v2i32 (null_frag (v2i32 DPR:$src1), (v2i32 (mul DPR:$Vn, (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQRDMLAHslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqrdmlah${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i16 DPR:$Vd), (v4i16 (null_frag (v4i16 DPR:$src1), (v4i16 (mul DPR:$Vn, (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQRDMLAHslv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqrdmlah${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (null_frag (v4i32 QPR:$src1), (v4i32 (mul QPR:$Vn, (v4i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQRDMLAHslv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 0, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqrdmlah${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8i16 QPR:$Vd), (v8i16 (null_frag (v8i16 QPR:$src1), (v8i16 (mul QPR:$Vn, (v8i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQRDMLAHv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqrdmlah${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (null_frag (v2i32 DPR:$src1), (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMLAHv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqrdmlah${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (null_frag (v4i16 DPR:$src1), (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMLAHv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqrdmlah${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (null_frag (v4i32 QPR:$src1), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMLAHv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqrdmlah${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (null_frag (v8i16 QPR:$src1), (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMLSHslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqrdmlsh${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i32 DPR:$Vd), (v2i32 (null_frag (v2i32 DPR:$src1), (v2i32 (mul DPR:$Vn, (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQRDMLSHslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqrdmlsh${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i16 DPR:$Vd), (v4i16 (null_frag (v4i16 DPR:$src1), (v4i16 (mul DPR:$Vn, (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQRDMLSHslv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQMulOpSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqrdmlsh${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (null_frag (v4i32 QPR:$src1), (v4i32 (mul QPR:$Vn, (v4i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQRDMLSHslv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQMulOpSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqrdmlsh${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8i16 QPR:$Vd), (v8i16 (null_frag (v8i16 QPR:$src1), (v8i16 (mul QPR:$Vn, (v8i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQRDMLSHv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqrdmlsh${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (null_frag (v2i32 DPR:$src1), (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMLSHv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqrdmlsh${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (null_frag (v4i16 DPR:$src1), (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMLSHv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqrdmlsh${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (null_frag (v4i32 QPR:$src1), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMLSHv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqrdmlsh${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (null_frag (v8i16 QPR:$src1), (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMACi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMULHslv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VDIntSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqrdmulh${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v2i32 DPR:$Vd), (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQRDMULHslv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VDIntSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqrdmulh${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i16 DPR:$Vd), (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQRDMULHslv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane32 N3VQIntSL
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, pred:$p);
  string AsmString = "vqrdmulh${p}.s32	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v4i32 QPR:$Vd), (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn), (v4i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VQRDMULHslv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3VLane16 N3VQIntSL16
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, lane{1}, 0, lane{0}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane, pred:$p);
  string AsmString = "vqrdmulh${p}.s16	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [(set (v8i16 QPR:$Vd), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn), (v8i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVMulSLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<2> lane = { ?, ? };
  string NAME = ?;
}
def VQRDMULHv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqrdmulh${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMULHv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqrdmulh${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMULHv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqrdmulh${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi32Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRDMULHv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqrdmulh${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMULi16Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHLsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.s8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqrshifts (v16i8 QPR:$Vm), (v16i8 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.s64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vqrshifts (v1i64 DPR:$Vm), (v1i64 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHLsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.s32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqrshifts (v2i32 DPR:$Vm), (v2i32 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.s64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vqrshifts (v2i64 QPR:$Vm), (v2i64 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHLsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.s16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqrshifts (v4i16 DPR:$Vm), (v4i16 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.s32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqrshifts (v4i32 QPR:$Vm), (v4i32 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.s16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqrshifts (v8i16 QPR:$Vm), (v8i16 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.s8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqrshifts (v8i8 DPR:$Vm), (v8i8 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.u8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqrshiftu (v16i8 QPR:$Vm), (v16i8 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.u64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vqrshiftu (v1i64 DPR:$Vm), (v1i64 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHLuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.u32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqrshiftu (v2i32 DPR:$Vm), (v2i32 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.u64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vqrshiftu (v2i64 QPR:$Vm), (v2i64 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHLuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.u16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqrshiftu (v4i16 DPR:$Vm), (v4i16 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.u32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqrshiftu (v4i32 QPR:$Vm), (v4i32 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.u16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqrshiftu (v8i16 QPR:$Vm), (v8i16 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHLuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqrshl${p}.u8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqrshiftu (v8i8 DPR:$Vm), (v8i8 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQRSHRNsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vqrshrn${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvqrshrns (v2i64 QPR:$Vm), (i32 shr_imm32:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHRNsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vqrshrn${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvqrshrns (v4i32 QPR:$Vm), (i32 shr_imm16:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHRNsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vqrshrn${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvqrshrns (v8i16 QPR:$Vm), (i32 shr_imm8:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHRNuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vqrshrn${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvqrshrnu (v2i64 QPR:$Vm), (i32 shr_imm32:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHRNuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vqrshrn${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvqrshrnu (v4i32 QPR:$Vm), (i32 shr_imm16:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHRNuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vqrshrn${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvqrshrnu (v8i16 QPR:$Vm), (i32 shr_imm8:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHRUNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vqrshrun${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvqrshrnsu (v2i64 QPR:$Vm), (i32 shr_imm32:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHRUNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vqrshrun${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvqrshrnsu (v4i32 QPR:$Vm), (i32 shr_imm16:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQRSHRUNv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vqrshrun${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvqrshrnsu (v8i16 QPR:$Vm), (i32 shr_imm8:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsiv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvqshls (v16i8 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsiv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvqshls (v1i64 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsiv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvqshls (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsiv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvqshls (v2i64 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsiv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvqshls (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsiv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvqshls (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsiv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvqshls (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsiv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvqshls (v8i8 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshlu${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvqshlsu (v16i8 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshlu${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvqshlsu (v1i64 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshlu${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvqshlsu (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshlu${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvqshlsu (v2i64 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshlu${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvqshlsu (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshlu${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvqshlsu (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshlu${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvqshlsu (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshlu${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvqshlsu (v8i8 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.s8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqshifts (v16i8 QPR:$Vm), (v16i8 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.s64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vqshifts (v1i64 DPR:$Vm), (v1i64 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.s32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqshifts (v2i32 DPR:$Vm), (v2i32 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.s64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vqshifts (v2i64 QPR:$Vm), (v2i64 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.s16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqshifts (v4i16 DPR:$Vm), (v4i16 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.s32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqshifts (v4i32 QPR:$Vm), (v4i32 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.s16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqshifts (v8i16 QPR:$Vm), (v8i16 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.s8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqshifts (v8i8 DPR:$Vm), (v8i8 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLuiv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvqshlu (v16i8 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuiv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvqshlu (v1i64 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuiv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvqshlu (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuiv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvqshlu (v2i64 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuiv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvqshlu (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuiv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvqshlu (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuiv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvqshlu (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuiv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vqshl${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvqshlu (v8i8 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.u8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqshiftu (v16i8 QPR:$Vm), (v16i8 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.u64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vqshiftu (v1i64 DPR:$Vm), (v1i64 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.u32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqshiftu (v2i32 DPR:$Vm), (v2i32 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.u64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vqshiftu (v2i64 QPR:$Vm), (v2i64 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHLuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.u16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqshiftu (v4i16 DPR:$Vm), (v4i16 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.u32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqshiftu (v4i32 QPR:$Vm), (v4i32 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.u16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqshiftu (v8i16 QPR:$Vm), (v8i16 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHLuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vqshl${p}.u8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqshiftu (v8i8 DPR:$Vm), (v8i8 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VQSHRNsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vqshrn${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvqshrns (v2i64 QPR:$Vm), (i32 shr_imm32:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHRNsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vqshrn${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvqshrns (v4i32 QPR:$Vm), (i32 shr_imm16:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHRNsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vqshrn${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvqshrns (v8i16 QPR:$Vm), (i32 shr_imm8:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHRNuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vqshrn${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvqshrnu (v2i64 QPR:$Vm), (i32 shr_imm32:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHRNuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vqshrn${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvqshrnu (v4i32 QPR:$Vm), (i32 shr_imm16:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHRNuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vqshrn${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvqshrnu (v8i16 QPR:$Vm), (i32 shr_imm8:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHRUNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vqshrun${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvqshrnsu (v2i64 QPR:$Vm), (i32 shr_imm32:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHRUNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vqshrun${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvqshrnsu (v4i32 QPR:$Vm), (i32 shr_imm16:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSHRUNv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vqshrun${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvqshrnsu (v8i16 QPR:$Vm), (i32 shr_imm8:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSUBsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqsubs (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.s64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vqsubs (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSUBsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqsubs (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.s64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSUBsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqsubs (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqsubs (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqsubs (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vqsubu (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.u64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vqsubu (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSUBuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vqsubu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.u64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vqsubu (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VQSUBuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vqsubu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vqsubu (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vqsubu (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VQSUBuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vqsub${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vqsubu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSD::op24 = ?;
  bit N3VInt_QHSD::op23 = ?;
  bits<4> N3VInt_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSD::op4 = ?;
  Format N3VInt_QHSD::f = ?;
  InstrItinClass N3VInt_QHSD::itinD16 = ?;
  InstrItinClass N3VInt_QHSD::itinD32 = ?;
  InstrItinClass N3VInt_QHSD::itinQ16 = ?;
  InstrItinClass N3VInt_QHSD::itinQ32 = ?;
  string N3VInt_QHSD::OpcodeStr = ?;
  string N3VInt_QHSD::Dt = ?;
  SDPatternOperator N3VInt_QHSD::IntOp = ?;
  bit N3VInt_QHSD::Commutable = 0;
  string NAME = ?;
}
def VRADDHNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vraddhn${p}.i64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vraddhn (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRADDHNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vraddhn${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vraddhn (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRADDHNv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vraddhn${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vraddhn (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPEd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrecpe${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vrecpe (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPEfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrecpe${p}.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrecpe (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPEfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrecpe${p}.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrecpe (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPEhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrecpe${p}.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrecpe (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPEhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrecpe${p}.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrecpe (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPEq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrecpe${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vrecpe (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPSfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrecps${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrecps (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VRECSD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPSfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrecps${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrecps (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VRECSQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPShd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrecps${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrecps (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VRECSD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRECPShq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrecps${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrecps (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VRECSQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV16d8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV16D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrev16${p}.8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvrev16 (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV16q8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV16Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrev16${p}.8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvrev16 (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV32d16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV32D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrev32${p}.16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvrev32 (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV32d8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV32D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrev32${p}.8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvrev32 (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV32q16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV32Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrev32${p}.16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvrev32 (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV32q8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV32Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrev32${p}.8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvrev32 (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV64d16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV64D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrev64${p}.16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvrev64 (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV64d32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV64D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrev64${p}.32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvrev64 (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV64d8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV64D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrev64${p}.8	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvrev64 (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV64q16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV64Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrev64${p}.16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvrev64 (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV64q32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV64Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrev64${p}.32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvrev64 (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VREV64q8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V VREV64Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 0, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrev64${p}.8	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvrev64 (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRHADDsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vrhadds (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRHADDsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vrhadds (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VRHADDsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vrhadds (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VRHADDsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vrhadds (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VRHADDsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vrhadds (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VRHADDsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vrhadds (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRHADDuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vrhaddu (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRHADDuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vrhaddu (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VRHADDuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vrhaddu (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VRHADDuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vrhaddu (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VRHADDuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vrhaddu (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHS::op24 = ?;
  bit N3VInt_QHS::op23 = ?;
  bits<4> N3VInt_QHS::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHS::op4 = ?;
  Format N3VInt_QHS::f = ?;
  InstrItinClass N3VInt_QHS::itinD16 = ?;
  InstrItinClass N3VInt_QHS::itinD32 = ?;
  InstrItinClass N3VInt_QHS::itinQ16 = ?;
  InstrItinClass N3VInt_QHS::itinQ32 = ?;
  string N3VInt_QHS::OpcodeStr = ?;
  string N3VInt_QHS::Dt = ?;
  SDPatternOperator N3VInt_QHS::IntOp = ?;
  bit N3VInt_QHS::Commutable = 0;
  string NAME = ?;
}
def VRHADDuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrhadd${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vrhaddu (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTAD {	// Instruction InstTemplate Encoding InstARM VFPXI ADuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 1, 0, 0, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vrinta.f64	$Dd, $Dm";
  list<dag> Pattern = [(set (f64 DPR:$Dd), (fround (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTAH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vrinta.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTANDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrinta.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrinta (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTANDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrinta.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrinta (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTANQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrinta.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrinta (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTANQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrinta.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrinta (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTANanonymous_4129 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrinta.f32.f32	$Dd, $Dm";
  dag ResultInst = (VRINTANDf DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTANanonymous_4130 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrinta.f32.f32	$Qd, $Qm";
  dag ResultInst = (VRINTANQf QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTANanonymous_4131 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrinta.f16.f16	$Dd, $Dm";
  dag ResultInst = (VRINTANDh DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTANanonymous_4132 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrinta.f16.f16	$Qd, $Qm";
  dag ResultInst = (VRINTANQh QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTAS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vrinta.f32	$Sd, $Sm";
  list<dag> Pattern = [(set (f32 SPR:$Sd), (fround (f32 SPR:$Sm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTAanonymous_3751 {	// InstAlias Requires
  string AsmString = "vrinta.f32.f32	$Sd, $Sm";
  dag ResultInst = (VRINTAS SPR:$Sd, SPR:$Sm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTAanonymous_3752 {	// InstAlias Requires
  string AsmString = "vrinta.f64.f64	$Dd, $Dm";
  dag ResultInst = (VRINTAD DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTMD {	// Instruction InstTemplate Encoding InstARM VFPXI ADuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 1, 0, 1, 1, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vrintm.f64	$Dd, $Dm";
  list<dag> Pattern = [(set (f64 DPR:$Dd), (ffloor (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTMH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vrintm.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTMNDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintm.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrintm (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTMNDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintm.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrintm (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTMNQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintm.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrintm (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTMNQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintm.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrintm (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTMNanonymous_4129 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintm.f32.f32	$Dd, $Dm";
  dag ResultInst = (VRINTMNDf DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTMNanonymous_4130 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintm.f32.f32	$Qd, $Qm";
  dag ResultInst = (VRINTMNQf QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTMNanonymous_4131 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintm.f16.f16	$Dd, $Dm";
  dag ResultInst = (VRINTMNDh DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTMNanonymous_4132 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintm.f16.f16	$Qd, $Qm";
  dag ResultInst = (VRINTMNQh QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTMS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vrintm.f32	$Sd, $Sm";
  list<dag> Pattern = [(set (f32 SPR:$Sd), (ffloor (f32 SPR:$Sm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTManonymous_3751 {	// InstAlias Requires
  string AsmString = "vrintm.f32.f32	$Sd, $Sm";
  dag ResultInst = (VRINTMS SPR:$Sd, SPR:$Sm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTManonymous_3752 {	// InstAlias Requires
  string AsmString = "vrintm.f64.f64	$Dd, $Dm";
  dag ResultInst = (VRINTMD DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTND {	// Instruction InstTemplate Encoding InstARM VFPXI ADuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 1, 0, 0, 1, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vrintn.f64	$Dd, $Dm";
  list<dag> Pattern = [(set (f64 DPR:$Dd), (int_arm_neon_vrintn (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTNH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vrintn.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTNNDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintn.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrintn (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTNNDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintn.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrintn (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTNNQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintn.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrintn (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTNNQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintn.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrintn (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTNNanonymous_4129 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintn.f32.f32	$Dd, $Dm";
  dag ResultInst = (VRINTNNDf DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTNNanonymous_4130 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintn.f32.f32	$Qd, $Qm";
  dag ResultInst = (VRINTNNQf QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTNNanonymous_4131 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintn.f16.f16	$Dd, $Dm";
  dag ResultInst = (VRINTNNDh DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTNNanonymous_4132 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintn.f16.f16	$Qd, $Qm";
  dag ResultInst = (VRINTNNQh QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTNS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vrintn.f32	$Sd, $Sm";
  list<dag> Pattern = [(set (f32 SPR:$Sd), (int_arm_neon_vrintn (f32 SPR:$Sm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTNanonymous_3751 {	// InstAlias Requires
  string AsmString = "vrintn.f32.f32	$Sd, $Sm";
  dag ResultInst = (VRINTNS SPR:$Sd, SPR:$Sm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTNanonymous_3752 {	// InstAlias Requires
  string AsmString = "vrintn.f64.f64	$Dd, $Dm";
  dag ResultInst = (VRINTND DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTPD {	// Instruction InstTemplate Encoding InstARM VFPXI ADuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 1, 0, 1, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm);
  string AsmString = "vrintp.f64	$Dd, $Dm";
  list<dag> Pattern = [(set (f64 DPR:$Dd), (fceil (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTPH {	// Instruction InstTemplate Encoding InstARM VFPXI AHuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vrintp.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTPNDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintp.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrintp (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTPNDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintp.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrintp (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTPNQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintp.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrintp (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTPNQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintp.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrintp (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTPNanonymous_4129 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintp.f32.f32	$Dd, $Dm";
  dag ResultInst = (VRINTPNDf DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTPNanonymous_4130 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintp.f32.f32	$Qd, $Qm";
  dag ResultInst = (VRINTPNQf QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTPNanonymous_4131 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintp.f16.f16	$Dd, $Dm";
  dag ResultInst = (VRINTPNDh DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTPNanonymous_4132 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintp.f16.f16	$Qd, $Qm";
  dag ResultInst = (VRINTPNQh QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTPS {	// Instruction InstTemplate Encoding InstARM VFPXI ASuInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm);
  string AsmString = "vrintp.f32	$Sd, $Sm";
  list<dag> Pattern = [(set (f32 SPR:$Sd), (fceil (f32 SPR:$Sm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTPanonymous_3751 {	// InstAlias Requires
  string AsmString = "vrintp.f32.f32	$Sd, $Sm";
  dag ResultInst = (VRINTPS SPR:$Sd, SPR:$Sm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTPanonymous_3752 {	// InstAlias Requires
  string AsmString = "vrintp.f64.f64	$Dd, $Dm";
  dag ResultInst = (VRINTPD DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTRD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 1, 1, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vrintr${p}.f64	$Dd, $Dm";
  list<dag> Pattern = [(set (f64 DPR:$Dd), (fnearbyint (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTRH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vrintr${p}.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTRS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vrintr${p}.f32	$Sd, $Sm";
  list<dag> Pattern = [(set (f32 SPR:$Sd), (fnearbyint (f32 SPR:$Sm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTRanonymous_3748 {	// InstAlias Requires
  string AsmString = "vrintr$p.f16.f16	$Sd, $Sm";
  dag ResultInst = (VRINTRH SPR:$Sd, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTRanonymous_3749 {	// InstAlias Requires
  string AsmString = "vrintr$p.f32.f32	$Sd, $Sm";
  dag ResultInst = (VRINTRS SPR:$Sd, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTRanonymous_3750 {	// InstAlias Requires
  string AsmString = "vrintr$p.f64.f64	$Dd, $Dm";
  dag ResultInst = (VRINTRD DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTXD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 1, 1, 1, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vrintx${p}.f64	$Dd, $Dm";
  list<dag> Pattern = [(set (f64 DPR:$Dd), (frint (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTXH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vrintx${p}.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTXNDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintx.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrintx (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTXNDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintx.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrintx (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTXNQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintx.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrintx (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTXNQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintx.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrintx (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTXNanonymous_4129 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintx.f32.f32	$Dd, $Dm";
  dag ResultInst = (VRINTXNDf DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTXNanonymous_4130 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintx.f32.f32	$Qd, $Qm";
  dag ResultInst = (VRINTXNQf QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTXNanonymous_4131 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintx.f16.f16	$Dd, $Dm";
  dag ResultInst = (VRINTXNDh DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTXNanonymous_4132 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintx.f16.f16	$Qd, $Qm";
  dag ResultInst = (VRINTXNQh QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTXS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 1, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vrintx${p}.f32	$Sd, $Sm";
  list<dag> Pattern = [(set (f32 SPR:$Sd), (frint (f32 SPR:$Sm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTXanonymous_3748 {	// InstAlias Requires
  string AsmString = "vrintx$p.f16.f16	$Sd, $Sm";
  dag ResultInst = (VRINTXH SPR:$Sd, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTXanonymous_3749 {	// InstAlias Requires
  string AsmString = "vrintx$p.f32.f32	$Sd, $Sm";
  dag ResultInst = (VRINTXS SPR:$Sd, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTXanonymous_3750 {	// InstAlias Requires
  string AsmString = "vrintx$p.f64.f64	$Dd, $Dm";
  dag ResultInst = (VRINTXD DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTZD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 1, 1, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vrintz${p}.f64	$Dd, $Dm";
  list<dag> Pattern = [(set (f64 DPR:$Dd), (ftrunc (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTZH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vrintz${p}.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTZNDf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintz.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrintz (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTZNDh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VDIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm);
  string AsmString = "vrintz.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrintz (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTZNQf {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintz.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrintz (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTZNQh {	// Instruction InstTemplate Encoding InstARM NeonInp N2Vnp N2VQIntnp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm);
  string AsmString = "vrintz.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrintz (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasV8, HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "v8NEON";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2V8PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTZNanonymous_4129 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintz.f32.f32	$Dd, $Dm";
  dag ResultInst = (VRINTZNDf DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTZNanonymous_4130 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintz.f32.f32	$Qd, $Qm";
  dag ResultInst = (VRINTZNQf QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTZNanonymous_4131 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintz.f16.f16	$Dd, $Dm";
  dag ResultInst = (VRINTZNDh DPR:$Dd, DPR:$Dm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTZNanonymous_4132 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vrintz.f16.f16	$Qd, $Qm";
  dag ResultInst = (VRINTZNQh QPR:$Qd, QPR:$Qm);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTZS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 1, 1, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vrintz${p}.f32	$Sd, $Sm";
  list<dag> Pattern = [(set (f32 SPR:$Sd), (ftrunc (f32 SPR:$Sm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRINTZanonymous_3748 {	// InstAlias Requires
  string AsmString = "vrintz$p.f16.f16	$Sd, $Sm";
  dag ResultInst = (VRINTZH SPR:$Sd, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTZanonymous_3749 {	// InstAlias Requires
  string AsmString = "vrintz$p.f32.f32	$Sd, $Sm";
  dag ResultInst = (VRINTZS SPR:$Sd, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRINTZanonymous_3750 {	// InstAlias Requires
  string AsmString = "vrintz$p.f64.f64	$Dd, $Dm";
  dag ResultInst = (VRINTZD DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def VRSHLsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.s8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vrshifts (v16i8 QPR:$Vm), (v16i8 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.s64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vrshifts (v1i64 DPR:$Vm), (v1i64 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHLsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.s32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vrshifts (v2i32 DPR:$Vm), (v2i32 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.s64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vrshifts (v2i64 QPR:$Vm), (v2i64 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHLsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.s16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vrshifts (v4i16 DPR:$Vm), (v4i16 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.s32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vrshifts (v4i32 QPR:$Vm), (v4i32 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.s16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vrshifts (v8i16 QPR:$Vm), (v8i16 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.s8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vrshifts (v8i8 DPR:$Vm), (v8i8 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.u8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vrshiftu (v16i8 QPR:$Vm), (v16i8 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.u64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vrshiftu (v1i64 DPR:$Vm), (v1i64 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHLuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.u32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vrshiftu (v2i32 DPR:$Vm), (v2i32 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.u64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vrshiftu (v2i64 QPR:$Vm), (v2i64 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHLuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.u16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vrshiftu (v4i16 DPR:$Vm), (v4i16 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.u32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vrshiftu (v4i32 QPR:$Vm), (v4i32 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.u16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vrshiftu (v8i16 QPR:$Vm), (v8i16 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHLuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vrshl${p}.u8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vrshiftu (v8i8 DPR:$Vm), (v8i8 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VRSHRNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vrshrn${p}.i64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvrshrn (v2i64 QPR:$Vm), (i32 shr_imm32:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vrshrn${p}.i32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvrshrn (v4i32 QPR:$Vm), (i32 shr_imm16:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRNv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vrshrn${p}.i16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvrshrn (v8i16 QPR:$Vm), (i32 shr_imm8:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvrshrs (v16i8 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvrshrs (v1i64 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvrshrs (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvrshrs (v2i64 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvrshrs (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvrshrs (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvrshrs (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvrshrs (v8i8 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvrshru (v16i8 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvrshru (v1i64 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvrshru (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvrshru (v2i64 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvrshru (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvrshru (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvrshru (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSHRuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vrshr${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvrshru (v8i8 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTEd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrsqrte${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vrsqrte (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTEfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrsqrte${p}.f32	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrsqrte (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTEfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrsqrte${p}.f32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrsqrte (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTEhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, pred:$p);
  string AsmString = "vrsqrte${p}.f16	$Vd, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrsqrte (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTEhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrsqrte${p}.f16	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrsqrte (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTEq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 1, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, pred:$p);
  string AsmString = "vrsqrte${p}.u32	$Vd, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vrsqrte (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VUNAQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTSfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrsqrts${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (int_arm_neon_vrsqrts (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VRECSD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTSfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrsqrts${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (int_arm_neon_vrsqrts (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VRECSQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTShd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vrsqrts${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (int_arm_neon_vrsqrts (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VRECSD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSQRTShq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQInt Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrsqrts${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (int_arm_neon_vrsqrts (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VRECSQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (add QPR:$src1, (v16i8 (NEONvrshrs QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (add DPR:$src1, (v1i64 (NEONvrshrs DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (add DPR:$src1, (v2i32 (NEONvrshrs DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (add QPR:$src1, (v2i64 (NEONvrshrs QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (add DPR:$src1, (v4i16 (NEONvrshrs DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (add QPR:$src1, (v4i32 (NEONvrshrs QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (add QPR:$src1, (v8i16 (NEONvrshrs QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (add DPR:$src1, (v8i8 (NEONvrshrs DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (add QPR:$src1, (v16i8 (NEONvrshru QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (add DPR:$src1, (v1i64 (NEONvrshru DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (add DPR:$src1, (v2i32 (NEONvrshru DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (add QPR:$src1, (v2i64 (NEONvrshru QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (add DPR:$src1, (v4i16 (NEONvrshru DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (add QPR:$src1, (v4i32 (NEONvrshru QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (add QPR:$src1, (v8i16 (NEONvrshru QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSRAuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vrsra${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (add DPR:$src1, (v8i8 (NEONvrshru DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSUBHNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrsubhn${p}.i64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vrsubhn (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSUBHNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrsubhn${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vrsubhn (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VRSUBHNv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vrsubhn${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vrsubhn (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSDOTD {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp VDOT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$Vd, DPR:$Vn, DPR:$Vm);
  string AsmString = "vsdot.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set (v2i32 DPR:$dst), (int_arm_neon_sdot (v2i32 DPR:$Vd), (v8i8 DPR:$Vn), (v8i8 DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDotProd];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VDOTPROD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$dst = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSDOTDI {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$Vd, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane);
  string AsmString = "vsdot.s8	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDotProd];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VDOTPROD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$dst = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VSDOTDIanonymous_3962 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (int_arm_neon_sdot (v2i32 DPR:$Vd), (v8i8 DPR:$Vn), (v8i8 (bitconvert (v2i32 (NEONvduplane (v2i32 DPR:$Vm), VectorIndex32:$lane))))));
  list<dag> ResultInstrs = [(VSDOTDI DPR:$Vd, DPR:$Vn, (v2i32 DPR_VFP2:$Vm), VectorIndex32:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VSDOTQ {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp VDOT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins QPR:$Vd, QPR:$Vn, QPR:$Vm);
  string AsmString = "vsdot.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set (v4i32 QPR:$dst), (int_arm_neon_sdot (v4i32 QPR:$Vd), (v16i8 QPR:$Vn), (v16i8 QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDotProd];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VDOTPROD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$dst = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSDOTQI {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, lane, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins QPR:$Vd, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane);
  string AsmString = "vsdot.s8	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDotProd];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VDOTPROD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$dst = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VSDOTQIanonymous_3962 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_sdot (v4i32 QPR:$Vd), (v16i8 QPR:$Vn), (v16i8 (bitconvert (v4i32 (NEONvduplane (v4i32 QPR:$Vm), VectorIndex32:$lane))))));
  list<dag> ResultInstrs = [(VSDOTQI QPR:$Vd, QPR:$Vn, (EXTRACT_SUBREG QPR:$Vm, dsub_0), VectorIndex32:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VSELEQD {	// Instruction InstTemplate Encoding InstARM VFPXI ADbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Dd{4}, 0, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm);
  string AsmString = "vseleq.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), 0))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELEQH {	// Instruction InstTemplate Encoding InstARM VFPXI AHbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm);
  string AsmString = "vseleq.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (ARMcmov HPR:$Sm, HPR:$Sn, 0))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELEQS {	// Instruction InstTemplate Encoding InstARM VFPXI ASbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Sd{0}, 0, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm);
  string AsmString = "vseleq.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, 0))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELGED {	// Instruction InstTemplate Encoding InstARM VFPXI ADbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Dd{4}, 1, 0, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm);
  string AsmString = "vselge.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), 10))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELGEH {	// Instruction InstTemplate Encoding InstARM VFPXI AHbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm);
  string AsmString = "vselge.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (ARMcmov HPR:$Sm, HPR:$Sn, 10))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELGES {	// Instruction InstTemplate Encoding InstARM VFPXI ASbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Sd{0}, 1, 0, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm);
  string AsmString = "vselge.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, 10))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELGTD {	// Instruction InstTemplate Encoding InstARM VFPXI ADbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Dd{4}, 1, 1, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm);
  string AsmString = "vselgt.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), 12))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELGTH {	// Instruction InstTemplate Encoding InstARM VFPXI AHbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Sd{0}, 1, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm);
  string AsmString = "vselgt.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (ARMcmov HPR:$Sm, HPR:$Sn, 12))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELGTS {	// Instruction InstTemplate Encoding InstARM VFPXI ASbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Sd{0}, 1, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm);
  string AsmString = "vselgt.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, 12))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELVSD {	// Instruction InstTemplate Encoding InstARM VFPXI ADbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Dd{4}, 0, 1, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 0, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm);
  string AsmString = "vselvs.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), 6))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELVSH {	// Instruction InstTemplate Encoding InstARM VFPXI AHbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm);
  string AsmString = "vselvs.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (ARMcmov HPR:$Sm, HPR:$Sn, 6))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSELVSS {	// Instruction InstTemplate Encoding InstARM VFPXI ASbInp Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Sd{0}, 0, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 0, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm);
  string AsmString = "vselvs.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, 6))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFPARMv8];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 4;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSETLNi16 {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVSetLane
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 0, lane{1}, 0, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, lane{0}, 1, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$V);
  dag InOperandList = (ins DPR:$src1, GPR:$R, VectorIndex16:$lane, pred:$p);
  string AsmString = "vmov${p}.16	$V$lane, $R";
  list<dag> Pattern = [(set DPR:$V, (vector_insert (v4i16 DPR:$src1), GPR:$R, imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVISL;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $V";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NSetLnFrm;
  bits<6> Form = { 0, 1, 1, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VSETLNi32 {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVSetLane Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 0, lane{0}, 0, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, 0, 0, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$V);
  dag InOperandList = (ins DPR:$src1, GPR:$R, VectorIndex32:$lane, pred:$p);
  string AsmString = "vmov${p}.32	$V$lane, $R";
  list<dag> Pattern = [(set DPR:$V, (insertelt (v2i32 DPR:$src1), GPR:$R, imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 1;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVISL;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $V";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NSetLnFrm;
  bits<6> Form = { 0, 1, 1, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VSETLNi8 {	// Instruction InstTemplate Encoding InstARM NVLaneOp NVSetLane
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, 1, lane{2}, 0, V{3}, V{2}, V{1}, V{0}, R{3}, R{2}, R{1}, R{0}, 1, 0, 1, 1, V{4}, lane{1}, lane{0}, 1, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$V);
  dag InOperandList = (ins DPR:$src1, GPR:$R, VectorIndex8:$lane, pred:$p);
  string AsmString = "vmov${p}.8	$V$lane, $R";
  list<dag> Pattern = [(set DPR:$V, (vector_insert (v8i8 DPR:$src1), GPR:$R, imm:$lane))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONDup";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VMOVISL;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $V";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DupPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NSetLnFrm;
  bits<6> Form = { 0, 1, 1, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> V = { ?, ?, ?, ?, ? };
  bits<4> R = { ?, ?, ?, ? };
  bits<4> p = { ?, ?, ?, ? };
  bits<4> lane = { ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLLi16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh N2VLShMax
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, imm16:$SIMM, pred:$p);
  string AsmString = "vshll${p}.i16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (null_frag (v4i16 DPR:$Vm), imm16:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVSHLMaxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLLi32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh N2VLShMax
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, imm32:$SIMM, pred:$p);
  string AsmString = "vshll${p}.i32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (null_frag (v2i32 DPR:$Vm), imm32:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVSHLMaxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLLi8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh N2VLShMax
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, imm8:$SIMM, pred:$p);
  string AsmString = "vshll${p}.i8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (null_frag (v8i8 DPR:$Vm), imm8:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeVSHLMaxInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, imm1_31:$SIMM, pred:$p);
  string AsmString = "vshll${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (anonymous_4001 (v2i32 DPR:$Vm), imm1_31:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, imm1_15:$SIMM, pred:$p);
  string AsmString = "vshll${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (anonymous_4001 (v4i16 DPR:$Vm), imm1_15:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, imm1_7:$SIMM, pred:$p);
  string AsmString = "vshll${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (anonymous_4001 (v8i8 DPR:$Vm), imm1_7:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, imm1_31:$SIMM, pred:$p);
  string AsmString = "vshll${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (anonymous_4002 (v2i32 DPR:$Vm), imm1_31:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, imm1_15:$SIMM, pred:$p);
  string AsmString = "vshll${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (anonymous_4002 (v4i16 DPR:$Vm), imm1_15:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VLSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, imm1_7:$SIMM, pred:$p);
  string AsmString = "vshll${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (anonymous_4002 (v8i8 DPR:$Vm), imm1_7:$SIMM)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLiv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vshl${p}.i8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvshl (v16i8 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLiv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vshl${p}.i64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvshl (v1i64 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLiv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vshl${p}.i32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvshl (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLiv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vshl${p}.i64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvshl (v2i64 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLiv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vshl${p}.i16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvshl (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLiv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vshl${p}.i32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvshl (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLiv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vshl${p}.i16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvshl (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLiv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vshl${p}.i8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvshl (v8i8 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.s8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vshifts (v16i8 QPR:$Vm), (v16i8 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.s64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vshifts (v1i64 DPR:$Vm), (v1i64 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.s32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vshifts (v2i32 DPR:$Vm), (v2i32 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.s64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vshifts (v2i64 QPR:$Vm), (v2i64 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.s16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vshifts (v4i16 DPR:$Vm), (v4i16 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.s32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vshifts (v4i32 QPR:$Vm), (v4i32 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.s16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vshifts (v8i16 QPR:$Vm), (v8i16 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.s8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vshifts (v8i8 DPR:$Vm), (v8i8 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.u8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (int_arm_neon_vshiftu (v16i8 QPR:$Vm), (v16i8 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.u64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (int_arm_neon_vshiftu (v1i64 DPR:$Vm), (v1i64 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.u32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (int_arm_neon_vshiftu (v2i32 DPR:$Vm), (v2i32 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.u64	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (int_arm_neon_vshiftu (v2i64 QPR:$Vm), (v2i64 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHLuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.u16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (int_arm_neon_vshiftu (v4i16 DPR:$Vm), (v4i16 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.u32	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (int_arm_neon_vshiftu (v4i32 QPR:$Vm), (v4i32 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, QPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.u16	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (int_arm_neon_vshiftu (v8i16 QPR:$Vm), (v8i16 QPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHLuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VDIntSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, DPR:$Vn, pred:$p);
  string AsmString = "vshl${p}.u8	$Vd, $Vm, $Vn";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vshiftu (v8i8 DPR:$Vm), (v8i8 DPR:$Vn))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegVShFrm;
  bits<6> Form = { 1, 0, 0, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op24 = ?;
  bit N3VInt_QHSDSh::op23 = ?;
  bits<4> N3VInt_QHSDSh::op11_8 = { ?, ?, ?, ? };
  bit N3VInt_QHSDSh::op4 = ?;
  Format N3VInt_QHSDSh::f = ?;
  InstrItinClass N3VInt_QHSDSh::itinD16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinD32 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ16 = ?;
  InstrItinClass N3VInt_QHSDSh::itinQ32 = ?;
  string N3VInt_QHSDSh::OpcodeStr = ?;
  string N3VInt_QHSDSh::Dt = ?;
  SDPatternOperator N3VInt_QHSDSh::IntOp = ?;
  string NAME = ?;
}
def VSHRNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vshrn${p}.i64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (anonymous_4012 (v2i64 QPR:$Vm), (i32 shr_imm32:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vshrn${p}.i32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (anonymous_4012 (v4i32 QPR:$Vm), (i32 shr_imm16:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRNv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VNSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vshrn${p}.i16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (anonymous_4012 (v8i16 QPR:$Vm), (i32 shr_imm8:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vshr${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvshrs (v16i8 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vshr${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvshrs (v1i64 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vshr${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvshrs (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vshr${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvshrs (v2i64 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vshr${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvshrs (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vshr${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvshrs (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vshr${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvshrs (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vshr${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvshrs (v8i8 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vshr${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvshru (v16i8 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vshr${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvshru (v1i64 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vshr${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvshru (v2i32 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vshr${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvshru (v2i64 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vshr${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvshru (v4i16 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vshr${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvshru (v4i32 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vshr${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvshru (v8i16 QPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHRuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDSh
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vshr${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvshru (v8i8 DPR:$Vm), (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHTOD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{4}, 1, 1, 1, 0, 1, 0, dst{3}, dst{2}, dst{1}, dst{0}, 1, 0, 1, 1, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f64.s16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTID;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHTOH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 0, 1, 0, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 0, 1, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f16.s16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIH;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSHTOS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 0, 1, 0, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 1, 0, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f32.s16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIS;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSITOD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IDs_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 1, 0, 0, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.f64.s32	$Dd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTID;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSITOH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IHs_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.f16.s32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIH;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSITOS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1In AVConv1InSs_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.f32.s32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIS;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLIv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vsli${p}.8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvsli QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLIv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vsli${p}.64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvsli DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLIv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vsli${p}.32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvsli DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLIv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vsli${p}.64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvsli QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLIv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vsli${p}.16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvsli DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLIv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vsli${p}.32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvsli QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLIv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vsli${p}.16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvsli QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLIv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM, pred:$p);
  string AsmString = "vsli${p}.8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvsli DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShLFrm;
  bits<6> Form = { 1, 0, 0, 0, 1, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLTOD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{4}, 1, 1, 1, 0, 1, 0, dst{3}, dst{2}, dst{1}, dst{0}, 1, 0, 1, 1, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f64.s32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTID;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLTOH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 0, 1, 0, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 0, 1, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f16.s32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIH;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSLTOS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 0, 1, 0, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 1, 0, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f32.s32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIS;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSQRTD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADuI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 0, 0, 0, 1, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vsqrt${p}.f64	$Dd, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSQRT64;
  list<SchedReadWrite> SchedRW = [WriteFPSQRT64];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSQRTH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHuI
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vsqrt${p}.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSQRT16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSQRTS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASuI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 0, 0, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vsqrt${p}.f32	$Sd, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fsqrt SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpSQRT32;
  list<SchedReadWrite> SchedRW = [WriteFPSQRT32];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPUnaryFrm;
  bits<6> Form = { 0, 0, 1, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAsv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vsra${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (add QPR:$src1, (v16i8 (NEONvshrs QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAsv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vsra${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (add DPR:$src1, (v1i64 (NEONvshrs DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAsv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vsra${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (add DPR:$src1, (v2i32 (NEONvshrs DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vsra${p}.s64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (add QPR:$src1, (v2i64 (NEONvshrs QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAsv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vsra${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (add DPR:$src1, (v4i16 (NEONvshrs DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vsra${p}.s32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (add QPR:$src1, (v4i32 (NEONvshrs QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vsra${p}.s16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (add QPR:$src1, (v8i16 (NEONvshrs QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAsv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vsra${p}.s8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (add DPR:$src1, (v8i8 (NEONvshrs DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAuv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vsra${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (add QPR:$src1, (v16i8 (NEONvshru QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAuv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vsra${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (add DPR:$src1, (v1i64 (NEONvshru DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAuv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vsra${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (add DPR:$src1, (v2i32 (NEONvshru DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vsra${p}.u64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (add QPR:$src1, (v2i64 (NEONvshru QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAuv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vsra${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (add DPR:$src1, (v4i16 (NEONvshru DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vsra${p}.u32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (add QPR:$src1, (v4i32 (NEONvshru QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vsra${p}.u16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (add QPR:$src1, (v8i16 (NEONvshru QPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRAuv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShAdd
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vsra${p}.u8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (add DPR:$src1, (v8i8 (NEONvshru DPR:$Vm, (i32 imm:$SIMM))))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPALiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRIv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vsri${p}.8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvsri QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRIv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vsri${p}.64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (NEONvsri DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRIv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vsri${p}.32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvsri DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRIv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, SIMM{5}, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm64:$SIMM, pred:$p);
  string AsmString = "vsri${p}.64	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (NEONvsri QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRIv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vsri${p}.16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvsri DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRIv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, SIMM{4}, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm32:$SIMM, pred:$p);
  string AsmString = "vsri${p}.32	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvsri QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRIv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VQShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$src1, QPR:$Vm, shr_imm16:$SIMM, pred:$p);
  string AsmString = "vsri${p}.16	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvsri QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSRIv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2VImm N2VDShIns
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, 1, SIMM{2}, SIMM{1}, SIMM{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$src1, DPR:$Vm, shr_imm8:$SIMM, pred:$p);
  string AsmString = "vsri${p}.8	$Vd, $Vm, $SIMM";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvsri DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vm = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegVShRFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bits<6> SIMM = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VST1LNd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST1LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, lane{1}, lane{0}, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane, pred:$p);
  string AsmString = "vst1${p}.16	\{$Vd[$lane]\}, $Rn";
  list<dag> Pattern = [(truncstorei16 (NEONvgetlaneu (v4i16 DPR:$Vd), imm:$lane), addrmode6:$Rn)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST1LNd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST1LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, lane{1}, lane{0}, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, nohash_imm:$lane, pred:$p);
  string AsmString = "vst1${p}.16	\{$Vd[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [(set GPR:$wb, (post_truncsti16 (NEONvgetlaneu (v4i16 DPR:$Vd), imm:$lane), addrmode6:$Rn, am6offset:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST1LNd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST1LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, lane{0}, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane, pred:$p);
  string AsmString = "vst1${p}.32	\{$Vd[$lane]\}, $Rn";
  list<dag> Pattern = [(store (extractelt (v2i32 DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST1LNd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST1LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, lane{0}, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6oneL32:$Rn, am6offset:$Rm, DPR:$Vd, nohash_imm:$lane, pred:$p);
  string AsmString = "vst1${p}.32	\{$Vd[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [(set GPR:$wb, (post_store (extractelt (v2i32 DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn, am6offset:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST1LNd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST1LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, lane{2}, lane{1}, lane{0}, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane, pred:$p);
  string AsmString = "vst1${p}.8	\{$Vd[$lane]\}, $Rn";
  list<dag> Pattern = [(truncstorei8 (NEONvgetlaneu (v8i8 DPR:$Vd), imm:$lane), addrmode6:$Rn)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST1LNd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST1LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, lane{2}, lane{1}, lane{0}, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, nohash_imm:$lane, pred:$p);
  string AsmString = "vst1${p}.8	\{$Vd[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [(set GPR:$wb, (post_truncsti8 (NEONvgetlaneu (v8i8 DPR:$Vd), imm:$lane), addrmode6:$Rn, am6offset:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST1LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST1LNdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, pred:$p);
  string AsmString = "vst1${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vst1${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst1${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, pred:$p);
  string AsmString = "vst1${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vst1${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst1${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst1${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst1${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst1${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNq16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNPseudo Sched VST1QLNPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(truncstorei16 (NEONvgetlaneu (v8i16 QPR:$src), imm:$lane), addrmode6:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNq16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNWBPseudo Sched VST1QLNWBPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$wb, (post_truncsti16 (NEONvgetlaneu (v8i16 QPR:$src), imm:$lane), addrmode6:$addr, am6offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNq32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNPseudo Sched VST1QLNPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(store (extractelt (v4i32 QPR:$src), imm:$lane), addrmode6:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNq32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNWBPseudo Sched VST1QLNWBPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$wb, (post_store (extractelt (v4i32 QPR:$src), imm:$lane), addrmode6:$addr, am6offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNq8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNPseudo Sched VST1QLNPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(truncstorei8 (NEONvgetlaneu (v16i8 QPR:$src), imm:$lane), addrmode6:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1LNq8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNWBPseudo Sched VST1QLNWBPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$wb, (post_truncsti8 (NEONvgetlaneu (v16i8 QPR:$src), imm:$lane), addrmode6:$addr, am6offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1d16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d16Q {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D4
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d16Qwb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d16Qwb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d16T {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d16Twb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d16Twb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d32Q {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D4
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d32Qwb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d32Qwb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d32T {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d32Twb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d32Twb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d64 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d64Q {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D4
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d64QPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1d64QPseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1d64QPseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1d64Qwb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d64Qwb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d64T {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d64TPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1d64TPseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1d64TPseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST1d64Twb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d64Twb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 1, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d64wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d64wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 1, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d8Q {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D4
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d8Qwb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d8Qwb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d8T {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1D3
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1d8Twb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d8Twb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, VecListThreeD:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1d8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, 0, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1d8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64:$Rn, rGPR:$Rm, VecListOneD:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1q16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x2;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1q16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1q16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1q32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x2;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1q32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1q32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1q64 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x2;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1q64wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1q64wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 1, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.64	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST1q8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST1Q
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST1x2;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST1q8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST1q8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst1${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1x2u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST1Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST2LNd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, lane{1}, lane{0}, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNd16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNd16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, lane{1}, lane{0}, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, lane{0}, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNd32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNd32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, lane{0}, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, lane{2}, lane{1}, lane{0}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.8	\{$Vd[$lane], $src2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNd8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNd8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, lane{2}, lane{1}, lane{0}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.8	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vst2${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst2${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, pred:$p);
  string AsmString = "vst2${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vst2${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst2${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, pred:$p);
  string AsmString = "vst2${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst2${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst2${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst2${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNq16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, lane{1}, lane{0}, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNq16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNq16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNq16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, lane{1}, lane{0}, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNq32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST2LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, lane{0}, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNq32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2ln;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNq32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = [WriteVST1];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNq32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST2LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, lane{0}, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, nohash_imm:$lane, pred:$p);
  string AsmString = "vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST2LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST2LNqAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vst2${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNqAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst2${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNqWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vst2${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNqWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst2${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNqWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst2${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2LNqWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst2${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2b16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VST2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPairSpaced:$Vd, pred:$p);
  string AsmString = "vst2${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST2b16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPairSpaced:$Vd, pred:$p);
  string AsmString = "vst2${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST2b16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPairSpaced:$Vd, pred:$p);
  string AsmString = "vst2${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST2b32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VST2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPairSpaced:$Vd, pred:$p);
  string AsmString = "vst2${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST2b32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPairSpaced:$Vd, pred:$p);
  string AsmString = "vst2${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST2b32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPairSpaced:$Vd, pred:$p);
  string AsmString = "vst2${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST2b8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VST2
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPairSpaced:$Vd, pred:$p);
  string AsmString = "vst2${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST2b8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPairSpaced:$Vd, pred:$p);
  string AsmString = "vst2${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST2b8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPairSpaced:$Vd, pred:$p);
  string AsmString = "vst2${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST2d16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VST2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst2${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST2d16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst2${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST2d16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst2${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST2d32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VST2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst2${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST2d32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst2${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST2d32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst2${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST2d8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VST2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst2${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST2d8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst2${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST2d8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, VecListDPair:$Vd, pred:$p);
  string AsmString = "vst2${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST2q16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VST2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst2${p}.16	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST2q16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2q16PseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2q16PseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBregisterPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2q16wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst2${p}.16	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST2q16wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst2${p}.16	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST2q32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VST2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst2${p}.32	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST2q32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2q32PseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2q32PseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBregisterPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2q32wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst2${p}.32	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST2q32wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst2${p}.32	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST2q8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt VST2 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst2${p}.8	$Vd, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST2q8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2q8PseudoWB_fixed {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBfixedPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2q8PseudoWB_register {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBregisterPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, rGPR:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST2x2u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST2q8wb_fixed {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst2${p}.8	$Vd, $Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 0, 1 };
  string NAME = ?;
}
def VST2q8wb_register {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128or256:$Rn, rGPR:$Rm, VecListFourD:$Vd, pred:$p);
  string AsmString = "vst2${p}.8	$Vd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VLD1u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST2Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST3LNd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, lane{1}, lane{0}, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNd16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNd16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, lane{1}, lane{0}, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, lane{0}, 0, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNd32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNd32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, lane{0}, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, lane{2}, lane{1}, lane{0}, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNd8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNd8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, lane{2}, lane{1}, lane{0}, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNq16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, lane{1}, lane{0}, 1, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNq16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQLNPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNq16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNq16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, lane{1}, lane{0}, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNq32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST3LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, lane{0}, 1, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNq32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQLNPseudo
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3ln;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNq32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNq32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST3LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, lane{0}, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane, pred:$p);
  string AsmString = "vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST3LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST3LNqAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNqAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNqWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNqWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNqWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3LNqWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3d16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST3d16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3d16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3d16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST3d32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST3d32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3d32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3d32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 1, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST3d8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST3d8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3d8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3d8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 0, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST3dAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3dAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3dAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3dWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3dWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3dWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3dWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3dWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3dWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3q16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST3q16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3q16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 1, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST3q16oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3q16oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3q32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST3q32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3q32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 1, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST3q32oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3q32oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3q8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST3q8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3q8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST3DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 0, 1, 0, 0, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, pred:$p);
  string AsmString = "vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST3Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST3q8oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3q8oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST3u;
  list<SchedReadWrite> SchedRW = [WriteVST3];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3qAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3qAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3qAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3qWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3qWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3qWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst3${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3qWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3qWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST3qWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst3${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNd16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, lane{1}, lane{0}, 0, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNd16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNd16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNd16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, lane{1}, lane{0}, 0, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNd32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, lane{0}, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNd32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNd32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNd32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, lane{0}, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNd8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, lane{2}, lane{1}, lane{0}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNd8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNd8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNd8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, lane{2}, lane{1}, lane{0}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNdAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNdAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNdAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vst4${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNdWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNdWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNdWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, pred:$p);
  string AsmString = "vst4${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNdWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNdWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNdWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNq16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, lane{1}, lane{0}, 1, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNq16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNq16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNq16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 1, lane{1}, lane{0}, 1, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNq32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn Sched VST4LN
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, lane{0}, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNq32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQLNPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4ln;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNq32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQLNWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = [WriteVST2];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNq32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt NLdStLn VST4LNWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 1, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, lane{0}, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane, pred:$p);
  string AsmString = "vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4lnu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVST4LN";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<3> lane = { ?, ?, ? };
  string NAME = ?;
}
def VST4LNqAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNqAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNqWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNqWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNqWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4LNqWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4d16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST4d16Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4d16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4d16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST4d32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST4d32Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4d32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4d32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST4d8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST4d8Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4d8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4d8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST4dAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4dAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4dAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4dWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4dWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4dWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4dWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4dWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4dWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4q16 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST4q16Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4q16_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST4q16oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4q16oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4q32 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST4q32Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4q32_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST4q32oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4q32oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4q8 {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4D
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { 1, 1, 1, 1 };
  string NAME = ?;
}
def VST4q8Pseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4q8_UPD {	// Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched VST4DWB
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, pred:$p);
  string AsmString = "vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONLoadStore";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$Rn.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
  string DecoderMethod = "DecodeVLDST4Instruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NLdStFrm;
  bits<6> Form = { 0, 1, 1, 1, 1, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<6> Rn = { ?, ?, ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def VST4q8oddPseudo {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode6:$addr, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4q8oddPseudo_UPD {	// Instruction InstTemplate Encoding InstARM PseudoNLdSt VSTQQQQWBPseudo Sched
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = ?;
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VST4u;
  list<SchedReadWrite> SchedRW = [WriteVST4];
  string Constraints = "$addr.addr = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode6;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4qAsm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4qAsm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4qAsm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.8	$list, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4qWB_fixed_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4qWB_fixed_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4qWB_fixed_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p);
  string AsmString = "vst4${p}.8	$list, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4qWB_register_Asm_16 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.16	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4qWB_register_Asm_32 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.32	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VST4qWB_register_Asm_8 {	// Instruction InstTemplate AsmPseudoInst Requires NEONDataTypeAsmPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p);
  string AsmString = "vst4${p}.8	$list, $addr, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VSTMDDB_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXDI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, 0, regs{12}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "vstmdb${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSTMDIA {	// Instruction InstTemplate Encoding InstARM VFPXI AXDI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, regs{12}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "vstmia${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSTMDIA_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXDI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, regs{12}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{11}, regs{10}, regs{9}, regs{8}, 1, 0, 1, 1, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops);
  string AsmString = "vstmia${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSTMQIA {	// Instruction InstTemplate Encoding InstARM PseudoVFPLdStM
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins DPair:$src, GPR:$Rn, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(word_alignedstore (v2f64 DPair:$src), GPR:$Rn)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VSTMSDB_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXSI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, 0, regs{8}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{12}, regs{11}, regs{10}, regs{9}, 1, 0, 1, 0, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops);
  string AsmString = "vstmdb${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSTMSIA {	// Instruction InstTemplate Encoding InstARM VFPXI AXSI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, regs{8}, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{12}, regs{11}, regs{10}, regs{9}, 1, 0, 1, 0, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops);
  string AsmString = "vstmia${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSTMSIA_UPD {	// Instruction InstTemplate Encoding InstARM VFPXI AXSI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 0, 1, regs{8}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{12}, regs{11}, regs{10}, regs{9}, 1, 0, 1, 0, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops);
  string AsmString = "vstmia${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = VFPLdStMulFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 1 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<13> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSTRD {	// Instruction InstTemplate Encoding InstARM VFPI ADI5
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, Dd{4}, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins DPR:$Dd, addrmode5:$addr, pred:$p);
  string AsmString = "vstr${p}	$Dd, $addr";
  list<dag> Pattern = [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore64;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode5;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSTRH {	// Instruction InstTemplate Encoding InstARM VFPI AHI5 Requires
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, Sd{0}, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins HPR:$Sd, addrmode5fp16:$addr, pred:$p);
  string AsmString = "vstr${p}.16	$Sd, $addr";
  list<dag> Pattern = [(alignedstore16 HPR:$Sd, addrmode5fp16:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore16;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode5FP16;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSTRS {	// Instruction InstTemplate Encoding InstARM VFPI ASI5
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 0, 1, addr{8}, Sd{0}, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins SPR:$Sd, addrmode5:$addr, pred:$p);
  string AsmString = "vstr${p}	$Sd, $addr";
  list<dag> Pattern = [(alignedstore32 SPR:$Sd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpStore32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode5;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPLdStFrm;
  bits<6> Form = { 0, 1, 0, 1, 1, 0 };
  Domain D = VFPNeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ADbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Dd{4}, 1, 1, Dn{3}, Dn{2}, Dn{1}, Dn{0}, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, Dn{4}, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins DPR:$Dn, DPR:$Dm, pred:$p);
  string AsmString = "vsub${p}.f64	$Dd, $Dn, $Dm";
  list<dag> Pattern = [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpALU64;
  list<SchedReadWrite> SchedRW = [WriteFPALU64];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Dn = $Dd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Dn = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AHbI Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 1, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins HPR:$Sn, HPR:$Sm, pred:$p);
  string AsmString = "vsub${p}.f16	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set HPR:$Sd, (fsub HPR:$Sn, HPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpALU16;
  list<SchedReadWrite> SchedRW = [WriteFPALU32];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Sn = $Sd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBHNv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vsubhn${p}.i64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (null_frag (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBHNv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vsubhn${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (null_frag (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBHNv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VNInt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 1, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vsubhn${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (null_frag (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBLsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubl${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v2i64 (sext (v2i32 DPR:$Vn))), (v2i64 (sext (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBLsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubl${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v4i32 (sext (v4i16 DPR:$Vn))), (v4i32 (sext (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBLsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubl${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v8i16 (sext (v8i8 DPR:$Vn))), (v8i16 (sext (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBLuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubl${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v2i64 (zext (v2i32 DPR:$Vn))), (v2i64 (zext (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBLuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubl${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v4i32 (zext (v4i16 DPR:$Vn))), (v4i32 (zext (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBLuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VLExt
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubl${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v8i16 (zext (v8i8 DPR:$Vn))), (v8i16 (zext (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSHLiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI ASbI ASbIn Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 0, Sd{0}, 1, 1, Sn{4}, Sn{3}, Sn{2}, Sn{1}, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, Sn{0}, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sn, SPR:$Sm, pred:$p);
  string AsmString = "vsub${p}.f32	$Sd, $Sn, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpALU32;
  list<SchedReadWrite> SchedRW = [WriteFPALU32];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Sn = $Sd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPBinaryFrm;
  bits<6> Form = { 0, 1, 0, 0, 0, 0 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sn = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBWsv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubw${p}.s32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v2i64 QPR:$Vn), (v2i64 (sext (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBWsv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubw${p}.s16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v4i32 QPR:$Vn), (v4i32 (sext (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBWsv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubw${p}.s8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v8i16 QPR:$Vn), (v8i16 (sext (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBWuv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubw${p}.u32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v2i64 QPR:$Vn), (v2i64 (zext (v2i32 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBWuv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubw${p}.u16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v4i32 QPR:$Vn), (v4i32 (zext (v4i16 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBWuv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VW
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsubw${p}.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (sub (v8i16 QPR:$Vn), (v8i16 (zext (v8i8 DPR:$Vm)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBfd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2f32 (fsub (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBfq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.f32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4f32 (fsub (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBhd {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4f16 (fsub (v4f16 DPR:$Vn), (v4f16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBIND;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBhq {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.f16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8f16 (fsub (v8f16 QPR:$Vn), (v8f16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (sub (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VSUBv1i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.i64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v1i64 (sub (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (sub (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VSUBv2i64 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.i64	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v2i64 (sub (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSUBv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (sub (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VSUBv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.i32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (sub (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VSUBv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.i16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (sub (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VSUBv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vsub${p}.i8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (sub (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VSUBiD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit N3V_QHSD::op24 = ?;
  bit N3V_QHSD::op23 = ?;
  bits<4> N3V_QHSD::op11_8 = { ?, ?, ?, ? };
  bit N3V_QHSD::op4 = ?;
  InstrItinClass N3V_QHSD::itinD = ?;
  InstrItinClass N3V_QHSD::itinQ = ?;
  string N3V_QHSD::OpcodeStr = ?;
  string N3V_QHSD::Dt = ?;
  SDNode N3V_QHSD::OpNode = ?;
  bit N3V_QHSD::Commutable = 0;
  string NAME = ?;
}
def VSWPd {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N2VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$Vm);
  dag InOperandList = (ins DPR:$in1, DPR:$in2, pred:$p);
  string AsmString = "vswp${p}	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$in1 = $Vd, $in2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VSWPq {	// Instruction InstTemplate Encoding InstARM NeonXI NDataXI N2VX
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$in1, QPR:$in2, pred:$p);
  string AsmString = "vswp${p}	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$in1 = $Vd, $in2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTBL1 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins VecListOneD:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtbl${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvtbl1 VecListOneD:$Vn, DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTB1;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVTBLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTBL2 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins VecListDPair:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtbl${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTB2;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVTBLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTBL3 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins VecListThreeD:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtbl${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTB3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVTBLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTBL3Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNeonI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins QQPR:$tbl, DPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTB3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VTBL4 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins VecListFourD:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtbl${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTB4;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVTBLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTBL4Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNeonI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins QQPR:$tbl, DPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTB4;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VTBX1 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtbx${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTBX1;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$orig = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVTBLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTBX2 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtbx${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTBX2;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$orig = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVTBLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTBX3 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 0, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtbx${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTBX3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$orig = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVTBLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTBX3Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNeonI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$orig, QQPR:$tbl, DPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTBX3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$orig = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VTBX4 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 1, 1, Vn{4}, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtbx${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTBX4;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$orig = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = NVTBLFrm;
  bits<6> Form = { 1, 0, 1, 0, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTBX4Pseudo {	// Instruction InstTemplate Encoding InstARM PseudoNeonI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$orig, QQPR:$tbl, DPR:$src, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VTBX4;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$orig = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeTBLInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def VTOSHD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{4}, 1, 1, 1, 1, 1, 0, dst{3}, dst{2}, dst{1}, dst{0}, 1, 0, 1, 1, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.s16.f64	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSHH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 1, 1, 0, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 0, 1, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.s16.f16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSHS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 1, 1, 0, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 1, 0, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.s16.f32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSIRD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vcvtr${p}.s32.f64	$Sd, $Dm";
  list<dag> Pattern = [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSIRH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IsH_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtr${p}.s32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSIRS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1In AVConv1InsS_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtr${p}.s32.f32	$Sd, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSIZD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vcvt${p}.s32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSIZH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IsH_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.s32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSIZS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1In AVConv1InsS_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 1, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.s32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSLD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{4}, 1, 1, 1, 1, 1, 0, dst{3}, dst{2}, dst{1}, dst{0}, 1, 0, 1, 1, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.s32.f64	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSLH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 1, 1, 0, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 0, 1, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.s32.f16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOSLS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 1, 1, 0, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 1, 0, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.s32.f32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSI;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOUHD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{4}, 1, 1, 1, 1, 1, 1, dst{3}, dst{2}, dst{1}, dst{0}, 1, 0, 1, 1, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.u16.f64	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOUHH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 1, 1, 1, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 0, 1, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.u16.f16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOUHS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 1, 1, 1, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 1, 0, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.u16.f32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSI;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOUIRD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 0, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vcvtr${p}.u32.f64	$Sd, $Dm";
  list<dag> Pattern = [(set SPR:$Sd, (int_arm_vcvtru (f64 DPR:$Dm)))];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOUIRH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IsH_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtr${p}.u32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOUIRS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1In AVConv1InsS_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvtr${p}.u32.f32	$Sd, $Sm";
  list<dag> Pattern = [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))];
  list<Register> Uses = [FPSCR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOUIZD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 1, 1, 1, Dm{4}, 0, Dm{3}, Dm{2}, Dm{1}, Dm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins DPR:$Dm, pred:$p);
  string AsmString = "vcvt${p}.u32.f64	$Sd, $Dm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Dm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOUIZH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IsH_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins HPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.u32.f16	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOUIZS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1In AVConv1InsS_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 1, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 1, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.u32.f32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOULD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{4}, 1, 1, 1, 1, 1, 1, dst{3}, dst{2}, dst{1}, dst{0}, 1, 0, 1, 1, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.u32.f64	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTDI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOULH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 1, 1, 1, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 0, 1, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.u32.f16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTHI;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTOULS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 1, 1, 1, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 1, 0, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.u32.f32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTSI;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTRNd16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$Vm);
  dag InOperandList = (ins DPR:$src1, DPR:$src2, pred:$p);
  string AsmString = "vtrn${p}.16	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTRNd32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$Vm);
  dag InOperandList = (ins DPR:$src1, DPR:$src2, pred:$p);
  string AsmString = "vtrn${p}.32	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTRNd8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$Vm);
  dag InOperandList = (ins DPR:$src1, DPR:$src2, pred:$p);
  string AsmString = "vtrn${p}.8	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTRNq16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = "vtrn${p}.16	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTRNq32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = "vtrn${p}.32	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTRNq8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 0, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = "vtrn${p}.8	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMQ;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTSTv16i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vtst${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v16i8 (NEONvtst (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTSTv2i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtst${p}.32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v2i32 (NEONvtst (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTSTv4i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtst${p}.16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v4i16 (NEONvtst (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTSTv4i32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vtst${p}.32	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v4i32 (NEONvtst (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTSTv8i16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VQ
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 1, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins QPR:$Vn, QPR:$Vm, pred:$p);
  string AsmString = "vtst${p}.16	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set QPR:$Vd, (v8i16 (NEONvtst (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4Q;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VTSTv8i8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N3VCommon N3V N3VD
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 0, 0, Vd{4}, 0, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd);
  dag InOperandList = (ins DPR:$Vn, DPR:$Vm, pred:$p);
  string AsmString = "vtst${p}.8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set DPR:$Vd, (v8i8 (NEONvtst (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VBINi4D;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "$Vn = $Vd";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUDOTD {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp VDOT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$Vd, DPR:$Vn, DPR:$Vm);
  string AsmString = "vudot.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set (v2i32 DPR:$dst), (int_arm_neon_udot (v2i32 DPR:$Vd), (v8i8 DPR:$Vn), (v8i8 DPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDotProd];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VDOTPROD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$dst = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUDOTDI {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 0, lane, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$Vd, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane);
  string AsmString = "vudot.u8	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDotProd];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VDOTPROD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$dst = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VUDOTDIanonymous_3962 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (int_arm_neon_udot (v2i32 DPR:$Vd), (v8i8 DPR:$Vn), (v8i8 (bitconvert (v2i32 (NEONvduplane (v2i32 DPR:$Vm), VectorIndex32:$lane))))));
  list<dag> ResultInstrs = [(VUDOTDI DPR:$Vd, DPR:$Vn, (v2i32 DPR_VFP2:$Vm), VectorIndex32:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VUDOTQ {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp VDOT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, Vm{4}, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins QPR:$Vd, QPR:$Vn, QPR:$Vm);
  string AsmString = "vudot.u8	$Vd, $Vn, $Vm";
  list<dag> Pattern = [(set (v4i32 QPR:$dst), (int_arm_neon_udot (v4i32 QPR:$Vd), (v16i8 QPR:$Vn), (v16i8 QPR:$Vm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDotProd];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VDOTPROD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$dst = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUDOTQI {	// Instruction InstTemplate Encoding InstARM NeonInp N3Vnp
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, 0, Vd{4}, 1, 0, Vn{3}, Vn{2}, Vn{1}, Vn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 0, 1, Vn{4}, 1, lane, 1, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$dst);
  dag InOperandList = (ins QPR:$Vd, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane);
  string AsmString = "vudot.u8	$Vd, $Vn, $Vm$lane";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDotProd];
  int Size = 4;
  string DecoderNamespace = "VFPV8";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VDOTPROD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$dst = $Vd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N3RegFrm;
  bits<6> Form = { 1, 0, 0, 1, 0, 1 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vn = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  bit lane = ?;
  string NAME = ?;
}
def VUDOTQIanonymous_3962 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_udot (v4i32 QPR:$Vd), (v16i8 QPR:$Vn), (v16i8 (bitconvert (v4i32 (NEONvduplane (v4i32 QPR:$Vm), VectorIndex32:$lane))))));
  list<dag> ResultInstrs = [(VUDOTQI QPR:$Vd, QPR:$Vn, (EXTRACT_SUBREG QPR:$Vm, dsub_0), VectorIndex32:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def VUHTOD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{4}, 1, 1, 1, 0, 1, 1, dst{3}, dst{2}, dst{1}, dst{0}, 1, 0, 1, 1, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f64.u16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTID;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUHTOH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 0, 1, 1, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 0, 1, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f16.u16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIH;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUHTOS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 0, 1, 1, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 1, 0, 0, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits16:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f32.u16	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIS;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUITOD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IDs_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Dd{4}, 1, 1, 1, 0, 0, 0, Dd{3}, Dd{2}, Dd{1}, Dd{0}, 1, 0, 1, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Dd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.f64.u32	$Dd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTID;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Dd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUITOH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1IHs_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 0, 1, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs HPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.f16.u32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIH;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUITOS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1In AVConv1InSs_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, Sd{0}, 1, 1, 1, 0, 0, 0, Sd{4}, Sd{3}, Sd{2}, Sd{1}, 1, 0, 1, 0, 0, 1, Sm{0}, 0, Sm{4}, Sm{3}, Sm{2}, Sm{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$Sd);
  dag InOperandList = (ins SPR:$Sm, pred:$p);
  string AsmString = "vcvt${p}.f32.u32	$Sd, $Sm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIS;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> Sd = { ?, ?, ?, ?, ? };
  bits<5> Sm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VULTOD {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsD_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{4}, 1, 1, 1, 0, 1, 1, dst{3}, dst{2}, dst{1}, dst{0}, 1, 0, 1, 1, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$dst);
  dag InOperandList = (ins DPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f64.u32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTID;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VULTOH {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Requires Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 0, 1, 1, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 0, 1, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f16.u32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasFullFP16];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIH;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VULTOS {	// Instruction InstTemplate Encoding InstARM VFPI VFPAI AVConv1I AVConv1XI AVConv1XInsS_Encode Sched
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 1, 1, 0, 1, dst{0}, 1, 1, 1, 0, 1, 1, dst{4}, dst{3}, dst{2}, dst{1}, 1, 0, 1, 0, 1, 1, fbits{0}, 0, fbits{4}, fbits{3}, fbits{2}, fbits{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs SPR:$dst);
  dag InOperandList = (ins SPR:$a, fbits32:$fbits, pred:$p);
  string AsmString = "vcvt${p}.f32.u32	$dst, $a, $fbits";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasVFP2];
  int Size = 4;
  string DecoderNamespace = "VFP";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_fpCVTIS;
  list<SchedReadWrite> SchedRW = [WriteFPCVT];
  string Constraints = "$a = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "VFPThumb2PostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = VFPConv1Frm;
  bits<6> Form = { 0, 1, 0, 0, 0, 1 };
  Domain D = VFPNeonA8Domain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<5> fbits = { ?, ?, ?, ?, ? };
  bits<5> dst = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUZPd16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$Vm);
  dag InOperandList = (ins DPR:$src1, DPR:$src2, pred:$p);
  string AsmString = "vuzp${p}.16	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUZPd8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$Vm);
  dag InOperandList = (ins DPR:$src1, DPR:$src2, pred:$p);
  string AsmString = "vuzp${p}.8	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUZPq16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = "vuzp${p}.16	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMQ3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUZPq32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = "vuzp${p}.32	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMQ3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VUZPq8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 0, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = "vuzp${p}.8	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMQ3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VZIPd16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$Vm);
  dag InOperandList = (ins DPR:$src1, DPR:$src2, pred:$p);
  string AsmString = "vzip${p}.16	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VZIPd8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VDShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 0, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs DPR:$Vd, DPR:$Vm);
  dag InOperandList = (ins DPR:$src1, DPR:$src2, pred:$p);
  string AsmString = "vzip${p}.8	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMD;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VZIPq16 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 1, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = "vzip${p}.16	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMQ3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VZIPq32 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 1, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = "vzip${p}.32	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMQ3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VZIPq8 {	// Instruction InstTemplate Encoding InstARM NeonI NDataI N2V N2VQShuffle
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, Vd{4}, 1, 1, 0, 0, 1, 0, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 0, 0, 0, 1, 1, 1, Vm{4}, 0, Vm{3}, Vm{2}, Vm{1}, Vm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd, QPR:$Vm);
  dag InOperandList = (ins QPR:$src1, QPR:$src2, pred:$p);
  string AsmString = "vzip${p}.8	$Vd, $Vm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasNEON];
  int Size = 4;
  string DecoderNamespace = "NEONData";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_VPERMQ3;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src1 = $Vd, $src2 = $Vm";
  string DisableEncoding = "";
  string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = N2RegFrm;
  bits<6> Form = { 1, 0, 0, 0, 0, 0 };
  Domain D = NeonDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> Vd = { ?, ?, ?, ?, ? };
  bits<5> Vm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def VecListDPair {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPair;
  string PrintMethod = "printVectorListTwo";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListDPairAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListDPairAllLanes {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPair;
  string PrintMethod = "printVectorListTwoAllLanes";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListDPairAllLanesAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListDPairAllLanesAsmOperand {	// AsmOperandClass
  string Name = "VecListDPairAllLanes";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListDPairAsmOperand {	// AsmOperandClass
  string Name = "VecListDPair";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListDPairSpaced {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPair;
  string PrintMethod = "printVectorListTwoSpaced";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListDPairSpacedAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListDPairSpacedAllLanes {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPair;
  string PrintMethod = "printVectorListTwoSpacedAllLanes";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListDPairSpacedAllLanesAsmOperand {	// AsmOperandClass
  string Name = "VecListDPairSpacedAllLanes";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListDPairSpacedAsmOperand {	// AsmOperandClass
  string Name = "VecListDPairSpaced";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourD {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListFour";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListFourDAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListFourDAllLanes {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListFourAllLanes";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListFourDAllLanesAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListFourDAllLanesAsmOperand {	// AsmOperandClass
  string Name = "VecListFourDAllLanes";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourDAsmOperand {	// AsmOperandClass
  string Name = "VecListFourD";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourDByteIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListFourDByteIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourDByteIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListFourDByteIndexAsmOperand;
  string NAME = ?;
}
def VecListFourDHWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListFourDHWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourDHWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListFourDHWordIndexAsmOperand;
  string NAME = ?;
}
def VecListFourDWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListFourDWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourDWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListFourDWordIndexAsmOperand;
  string NAME = ?;
}
def VecListFourQ {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListFourSpaced";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListFourQAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListFourQAllLanes {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListFourSpacedAllLanes";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListFourQAllLanesAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListFourQAllLanesAsmOperand {	// AsmOperandClass
  string Name = "VecListFourQAllLanes";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourQAsmOperand {	// AsmOperandClass
  string Name = "VecListFourQ";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourQHWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListFourQHWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourQHWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListFourQHWordIndexAsmOperand;
  string NAME = ?;
}
def VecListFourQWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListFourQWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListFourQWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListFourQWordIndexAsmOperand;
  string NAME = ?;
}
def VecListOneD {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListOne";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListOneDAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListOneDAllLanes {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListOneAllLanes";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListOneDAllLanesAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListOneDAllLanesAsmOperand {	// AsmOperandClass
  string Name = "VecListOneDAllLanes";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListOneDAsmOperand {	// AsmOperandClass
  string Name = "VecListOneD";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListOneDByteIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListOneDByteIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListOneDByteIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListOneDByteIndexAsmOperand;
  string NAME = ?;
}
def VecListOneDHWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListOneDHWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListOneDHWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListOneDHWordIndexAsmOperand;
  string NAME = ?;
}
def VecListOneDWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListOneDWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListOneDWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListOneDWordIndexAsmOperand;
  string NAME = ?;
}
def VecListThreeD {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListThree";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListThreeDAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListThreeDAllLanes {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListThreeAllLanes";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListThreeDAllLanesAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListThreeDAllLanesAsmOperand {	// AsmOperandClass
  string Name = "VecListThreeDAllLanes";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListThreeDAsmOperand {	// AsmOperandClass
  string Name = "VecListThreeD";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListThreeDByteIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListThreeDByteIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListThreeDByteIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListThreeDByteIndexAsmOperand;
  string NAME = ?;
}
def VecListThreeDHWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListThreeDHWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListThreeDHWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
  string NAME = ?;
}
def VecListThreeDWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListThreeDWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListThreeDWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListThreeDWordIndexAsmOperand;
  string NAME = ?;
}
def VecListThreeQ {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListThreeSpaced";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListThreeQAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListThreeQAllLanes {	// DAGOperand RegisterOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  RegisterClass RegClass = DPR;
  string PrintMethod = "printVectorListThreeSpacedAllLanes";
  string EncoderMethod = "";
  AsmOperandClass ParserMatchClass = VecListThreeQAllLanesAsmOperand;
  string OperandType = "OPERAND_REGISTER";
  Register GIZeroRegister = ?;
  string NAME = ?;
}
def VecListThreeQAllLanesAsmOperand {	// AsmOperandClass
  string Name = "VecListThreeQAllLanes";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListThreeQAsmOperand {	// AsmOperandClass
  string Name = "VecListThreeQ";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListThreeQHWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListThreeQHWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListThreeQHWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
  string NAME = ?;
}
def VecListThreeQWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListThreeQWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListThreeQWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListThreeQWordIndexAsmOperand;
  string NAME = ?;
}
def VecListTwoDByteIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListTwoDByteIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListTwoDByteIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListTwoDByteIndexAsmOperand;
  string NAME = ?;
}
def VecListTwoDHWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListTwoDHWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListTwoDHWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
  string NAME = ?;
}
def VecListTwoDWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListTwoDWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListTwoDWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListTwoDWordIndexAsmOperand;
  string NAME = ?;
}
def VecListTwoQHWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListTwoQHWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListTwoQHWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
  string NAME = ?;
}
def VecListTwoQWordIndexAsmOperand {	// AsmOperandClass
  string Name = "VecListTwoQWordIndexed";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addVecListIndexedOperands";
  string ParserMethod = "parseVectorList";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VecListTwoQWordIndexed {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VecListTwoQWordIndexAsmOperand;
  string NAME = ?;
}
def VectorIndex16 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printVectorIndex";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VectorIndex16Operand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return ((uint64_t)Imm) < 4;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def VectorIndex16Operand {	// AsmOperandClass
  string Name = "VectorIndex16";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VectorIndex32 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printVectorIndex";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VectorIndex32Operand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return ((uint64_t)Imm) < 2;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def VectorIndex32Operand {	// AsmOperandClass
  string Name = "VectorIndex32";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VectorIndex64 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printVectorIndex";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VectorIndex64Operand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return ((uint64_t)Imm) < 1;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def VectorIndex64Operand {	// AsmOperandClass
  string Name = "VectorIndex64";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def VectorIndex8 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printVectorIndex";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = VectorIndex8Operand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return ((uint64_t)Imm) < 8;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def VectorIndex8Operand {	// AsmOperandClass
  string Name = "VectorIndex8";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def WIN__CHKSTK {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = [(win__chkstk)];
  list<Register> Uses = [R4];
  list<Register> Defs = [R4, SP];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def WIN__DBZCHK {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$divisor);
  string AsmString = "";
  list<dag> Pattern = [(win__dbzchk tGPR:$divisor)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def WriteALU {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteALUSsr {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteALUsi {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteALUsr {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteBr {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteBrL {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteBrTbl {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteCMP {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteCMPsi {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteCMPsr {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteDIV {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPALU32 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPALU64 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPCVT {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPDIV32 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPDIV64 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPMAC32 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPMAC64 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPMOV {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPMUL32 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPMUL64 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPSQRT32 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteFPSQRT64 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteLd {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteMAC16 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteMAC32 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteMAC64Hi {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteMAC64Lo {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteMUL16 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteMUL32 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteMUL64Hi {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteMUL64Lo {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteNoop {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WritePreLd {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteST {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteVLD1 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteVLD2 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteVLD3 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteVLD4 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteVST1 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteVST2 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteVST3 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def WriteVST4 {	// SchedReadWrite SchedWrite
  string NAME = ?;
}
def XScale {	// SubtargetFeature Architecture
  string Name = "xscale";
  string Attribute = "ARMArch";
  string Value = "ARMv5te";
  string Desc = "ARMv5te architecture";
  list<SubtargetFeature> Implies = [ARMv5te];
  string NAME = ?;
}
def abd_shr {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$in1, node:$in2, node:$shift);
  dag Fragment = (NEONvshrs (sub (zext node:$in1), (zext node:$in2)), (i32 ?:$shift));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def abs {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ABS";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def add {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::ADD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def addc {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPOutGlue];
  string Opcode = "ISD::ADDC";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def adde {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPOutGlue, SDNPInGlue];
  string Opcode = "ISD::ADDE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def addr_offset_none {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode7Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode7Operand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemNoOffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 1;
  string SelectFunc = "SelectAddrOffsetNone";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode3 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode3
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode3Operand<false>";
  string EncoderMethod = "getAddrMode3OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode3AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 3;
  string SelectFunc = "SelectAddrMode3";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode3_pre {	// DAGOperand Operand MemOperand ComplexPattern AddrMode3
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode3Operand<true>";
  string EncoderMethod = "getAddrMode3OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode3AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 3;
  string SelectFunc = "SelectAddrMode3";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode5 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode5
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode5Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode5Operand<false>";
  string EncoderMethod = "getAddrMode5OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode5AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode5";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode5_pre {	// DAGOperand Operand MemOperand ComplexPattern AddrMode5
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode5Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode5Operand<true>";
  string EncoderMethod = "getAddrMode5OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode5AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode5";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode5fp16 {	// DAGOperand Operand ComplexPattern AddrMode5FP16
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode5FP16Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode5FP16Operand<false>";
  string EncoderMethod = "getAddrMode5FP16OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops GPR:$base, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode5FP16AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode5FP16";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode6Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6AddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm:$align);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6align16 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6Align
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode6Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6AddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm:$align);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6Align16AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6align32 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6Align
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode6Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6AddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm:$align);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6Align32AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6align64 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6Align
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode6Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6AddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm:$align);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6Align64AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6align64or128 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6Align
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode6Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6AddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm:$align);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6Align64or128AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6align64or128or256 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6Align
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode6Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6AddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm:$align);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6alignNone {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6Align
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrMode6Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6AddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm:$align);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6AlignNoneAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6dup {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6DupAddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6dupalign16 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6DupAlign
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6DupAddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6dupAlign16AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6dupalign32 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6DupAlign
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6DupAddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6dupAlign32AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6dupalign64 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6DupAlign
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6DupAddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6dupAlign64AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6dupalign64or128 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6DupAlign
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6DupAddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6dupalignNone {	// DAGOperand Operand MemOperand ComplexPattern AddrMode6DupAlign
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6DupAddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode6oneL32 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6Operand";
  string EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$addr, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode6";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantParent];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode_imm12 {	// DAGOperand Operand MemOperand ComplexPattern AddrMode_Imm12
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrModeImm12Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrModeImm12Operand<false>";
  string EncoderMethod = "getAddrModeImm12OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm12OffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrModeImm12";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode_imm12_pre {	// DAGOperand Operand MemOperand ComplexPattern AddrMode_Imm12
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeAddrModeImm12Operand";
  ValueType Type = i32;
  string PrintMethod = "printAddrModeImm12Operand<true>";
  string EncoderMethod = "getAddrModeImm12OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm12OffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrModeImm12";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def addrmode_tbb {	// DAGOperand Operand MemOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrModeTBB";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = addrmode_tbb_asmoperand;
  string NAME = ?;
}
def addrmode_tbb_asmoperand {	// AsmOperandClass
  string Name = "MemTBB";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def addrmode_tbh {	// DAGOperand Operand MemOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrModeTBH";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = addrmode_tbh_asmoperand;
  string NAME = ?;
}
def addrmode_tbh_asmoperand {	// AsmOperandClass
  string Name = "MemTBH";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def addrmodepc {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrModePCOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrModePC";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def addrspacecast {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ADDRSPACECAST";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTUnaryOp;
  string NAME = ?;
}
def adrlabel {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAdrLabelOperand<0>";
  string EncoderMethod = "getAdrLabelOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AdrLabelAsmOperand;
  string NAME = ?;
}
def alignedload16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (load node:$ptr);
  code PredicateCode = [{
  return cast<LoadSDNode>(N)->getAlignment() >= 2;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def alignedload32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (load node:$ptr);
  code PredicateCode = [{
  return cast<LoadSDNode>(N)->getAlignment() >= 4;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def alignednontemporalload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (nontemporalload node:$ptr);
  code PredicateCode = [{
  LoadSDNode *Ld = cast<LoadSDNode>(N);
  return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def alignednontemporalstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (nontemporalstore node:$val, node:$ptr);
  code PredicateCode = [{
  StoreSDNode *St = cast<StoreSDNode>(N);
  return St->getAlignment() >= St->getMemoryVT().getStoreSize();
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def alignedstore16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (store node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<StoreSDNode>(N)->getAlignment() >= 2;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def alignedstore32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (store node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<StoreSDNode>(N)->getAlignment() >= 4;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def am2offset_imm {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode2OffsetOperand";
  string EncoderMethod = "getAddrMode2OffsetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPRnopc, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AM2OffsetImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode2OffsetImm";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantRoot];
  int Complexity = -1;
  string NAME = ?;
}
def am2offset_reg {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode2OffsetOperand";
  string EncoderMethod = "getAddrMode2OffsetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPRnopc, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = PostIdxRegShiftedAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode2OffsetReg";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantRoot];
  int Complexity = -1;
  string NAME = ?;
}
def am3offset {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode3OffsetOperand";
  string EncoderMethod = "getAddrMode3OffsetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = AM3OffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectAddrMode3Offset";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantRoot];
  int Complexity = -1;
  string NAME = ?;
}
def am6offset {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeGPRRegisterClass";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode6OffsetOperand";
  string EncoderMethod = "getAddrMode6OffsetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 1;
  string SelectFunc = "SelectAddrMode6Offset";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantRoot];
  int Complexity = -1;
  string NAME = ?;
}
def and {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::AND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def and_su {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (and node:$lhs, node:$rhs);
  code PredicateCode = [{
  return N->hasOneUse();
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_0 {	// IntrinsicProperty NoCapture
  int ArgNo = 1;
  string NAME = ?;
}
def anonymous_1 {	// IntrinsicProperty NoCapture
  int ArgNo = 2;
  string NAME = ?;
}
def anonymous_10 {	// IntrinsicProperty WriteOnly
  int ArgNo = 1;
  string NAME = ?;
}
def anonymous_100 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_102];
  string NAME = ?;
}
def anonymous_1000 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [5, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1001 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_m;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [1, 1, 1, 1, 4];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1002 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_mu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [2, 1, 1, 1, 4];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1003 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_mBr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983, anonymous_939];
  list<int> OperandCycles = [1, 2, 1, 1, 4];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1004 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoadiALU;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939, anonymous_939];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1005 {	// InstrItinData
  InstrItinClass TheClass = IIC_iPop;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [1, 1, 4];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1006 {	// InstrItinData
  InstrItinClass TheClass = IIC_iPop_Br;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983, anonymous_939];
  list<int> OperandCycles = [1, 2, 4];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1007 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1008 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1009 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_d_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_101 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_102];
  string NAME = ?;
}
def anonymous_1010 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1011 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1012 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_d_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1013 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1014 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1015 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1016 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1017 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1018 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1019 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_d_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_102 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "fragid";
  string NAME = ?;
}
def anonymous_1020 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [2, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1021 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [2, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1022 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_m;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1023 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_mu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1024 {	// InstrItinData
  InstrItinClass TheClass = IIC_Br;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1025 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpSTAT;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1026 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpUNA32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [5, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1027 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpUNA64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [5, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1028 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCMP32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1029 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCMP64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_103 {	// AMDGPUArg
  LLVMType Type = llvm_i32_ty;
  string Name = "fragid";
  string NAME = ?;
}
def anonymous_1030 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTSD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [5, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1031 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTDS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [5, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1032 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTSI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [9, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1033 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTDI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [9, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1034 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTIS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [9, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1035 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTID;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [9, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1036 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpALU32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [9, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1037 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpALU64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [9, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1038 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMUL32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [9, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1039 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMUL64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [9, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_104 {	// AMDGPUArg
  LLVMType Type = llvm_i16_ty;
  string Name = "fragid";
  string NAME = ?;
}
def anonymous_1040 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMAC32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [9, 2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1041 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMAC64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [9, 2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1042 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpFMAC32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [9, 2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1043 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpFMAC64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [9, 2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1044 {	// InstrStage
  int Cycles = 15;
  list<FuncUnit> Units = [V6_Pipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1045 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpDIV32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1044];
  list<int> OperandCycles = [20, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1046 {	// InstrStage
  int Cycles = 29;
  list<FuncUnit> Units = [V6_Pipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1047 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpDIV64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1046];
  list<int> OperandCycles = [34, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1048 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpSQRT32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1044];
  list<int> OperandCycles = [20, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1049 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpSQRT64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1046];
  list<int> OperandCycles = [34, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_105 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "LOAD";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_1050 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVIS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [10, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1051 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVID;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [10, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1052 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVSI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [10, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1053 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVDI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [10, 10, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1054 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [5, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1055 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [5, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1056 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad_m;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [2, 1, 1, 5];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1057 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad_mu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [3, 2, 1, 1, 5];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1058 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1059 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_106 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  string NAME = ?;
}
def anonymous_1060 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore_m;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [2, 2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1061 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore_mu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [3, 2, 2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1062 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A8_Pipe0, A8_Pipe1];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1063 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUx;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1064 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1065 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1066 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1067 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUsir;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1068 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1069 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_107 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  string NAME = ?;
}
def anonymous_1070 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1071 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1072 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1073 {	// InstrItinData
  InstrItinClass TheClass = IIC_iUNAr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1074 {	// InstrItinData
  InstrItinClass TheClass = IIC_iUNAsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1075 {	// InstrItinData
  InstrItinClass TheClass = IIC_iEXTr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1076 {	// InstrItinData
  InstrItinClass TheClass = IIC_iEXTAr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1077 {	// InstrItinData
  InstrItinClass TheClass = IIC_iEXTAsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1078 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1079 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_108 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "LOAD_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_114];
  string NAME = ?;
}
def anonymous_1080 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1081 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1082 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1083 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1084 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1085 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1086 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1087 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1088 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1089 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_109 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "mip";
  string NAME = ?;
}
def anonymous_1090 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVix2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1062];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1091 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVix2addpc;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1062, anonymous_1062];
  list<int> OperandCycles = [3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1092 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A8_LSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1093 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVix2ld;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1062, anonymous_1092];
  list<int> OperandCycles = [5];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1094 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1095 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1096 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1097 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1098 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVix2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1062];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1099 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_11 {	// IntrinsicProperty ReadNone
  int ArgNo = 0;
  string NAME = ?;
}
def anonymous_110 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_112];
  string NAME = ?;
}
def anonymous_1100 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1101 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1102 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1103 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A8_Pipe0];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1104 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMUL16;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1103];
  list<int> OperandCycles = [5, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1105 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A8_Pipe0];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1106 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMAC16;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1105];
  list<int> OperandCycles = [6, 1, 1, 4];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1107 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMUL32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1105];
  list<int> OperandCycles = [6, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1108 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMAC32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1105];
  list<int> OperandCycles = [6, 1, 1, 4];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1109 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A8_Pipe0];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_111 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_112];
  string NAME = ?;
}
def anonymous_1110 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMUL64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1109];
  list<int> OperandCycles = [6, 6, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1111 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMAC64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1109];
  list<int> OperandCycles = [6, 6, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1112 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A8_Pipe0, A8_Pipe1];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1113 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1114 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1115 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_d_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1116 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1117 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1118 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_d_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1119 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A8_Pipe0, A8_Pipe1];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_112 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "mip";
  string NAME = ?;
}
def anonymous_1120 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1119, anonymous_1092];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1121 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1119, anonymous_1092];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1122 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1123 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1124 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1125 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1126 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_d_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1127 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A8_LSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1128 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1119, anonymous_1127];
  list<int> OperandCycles = [4, 3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1129 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1119, anonymous_1127];
  list<int> OperandCycles = [4, 3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_113 {	// AMDGPUArg
  LLVMType Type = llvm_i32_ty;
  string Name = "mip";
  string NAME = ?;
}
def anonymous_1130 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A8_Pipe0];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1131 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_m;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1130, anonymous_1127];
  list<int> OperandCycles = [1, 1, 1, 1, 3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1132 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A8_Pipe0];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1133 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A8_LSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1134 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_mu;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1132, anonymous_1133];
  list<int> OperandCycles = [2, 1, 1, 1, 3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1135 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_mBr;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1132, anonymous_1133, anonymous_1062];
  list<int> OperandCycles = [1, 2, 1, 1, 3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1136 {	// InstrItinData
  InstrItinClass TheClass = IIC_iPop;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1132, anonymous_1133];
  list<int> OperandCycles = [1, 1, 3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1137 {	// InstrItinData
  InstrItinClass TheClass = IIC_iPop_Br;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1132, anonymous_1133, anonymous_1062];
  list<int> OperandCycles = [1, 1, 3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1138 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoadiALU;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092, anonymous_1062];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1139 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_114 {	// AMDGPUArg
  LLVMType Type = llvm_i16_ty;
  string Name = "mip";
  string NAME = ?;
}
def anonymous_1140 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1141 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_d_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1142 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1143 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1144 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_d_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1145 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1119, anonymous_1127];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1146 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1119, anonymous_1127];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1147 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [2, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1148 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [2, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1149 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [2, 3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_115 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "LOAD_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_114];
  string NAME = ?;
}
def anonymous_1150 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [2, 3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1151 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_d_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1092];
  list<int> OperandCycles = [2, 3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1152 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1119, anonymous_1127];
  list<int> OperandCycles = [3, 3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1153 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1119, anonymous_1127];
  list<int> OperandCycles = [3, 3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1154 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_m;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1130, anonymous_1127];
  list<int> OperandCycles = [];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1155 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_mu;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1130, anonymous_1127];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1156 {	// InstrItinData
  InstrItinClass TheClass = IIC_Preload;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1157 {	// InstrItinData
  InstrItinClass TheClass = IIC_Br;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062];
  list<int> OperandCycles = [];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1158 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1159 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpSTAT;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158];
  list<int> OperandCycles = [20];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_116 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_112];
  string NAME = ?;
}
def anonymous_1160 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1161 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpUNA32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [7, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1162 {	// InstrStage
  int Cycles = 4;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1163 {	// InstrStage
  int Cycles = 4;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1164 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpUNA64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1162, anonymous_1163];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1165 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCMP32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1166 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCMP64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1162, anonymous_1163];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1167 {	// InstrStage
  int Cycles = 7;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1168 {	// InstrStage
  int Cycles = 7;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1169 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTSD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1167, anonymous_1168];
  list<int> OperandCycles = [7, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_117 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_112];
  string NAME = ?;
}
def anonymous_1170 {	// InstrStage
  int Cycles = 5;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1171 {	// InstrStage
  int Cycles = 5;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1172 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTDS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1170, anonymous_1171];
  list<int> OperandCycles = [5, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1173 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTSI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [7, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1174 {	// InstrStage
  int Cycles = 8;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1175 {	// InstrStage
  int Cycles = 8;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1176 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTDI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1174, anonymous_1175];
  list<int> OperandCycles = [8, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1177 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTIS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [7, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1178 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTID;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1174, anonymous_1175];
  list<int> OperandCycles = [8, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1179 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpALU32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [7, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_118 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "LOAD_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83, anonymous_114];
  string NAME = ?;
}
def anonymous_1180 {	// InstrStage
  int Cycles = 9;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1181 {	// InstrStage
  int Cycles = 9;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1182 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpALU64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1180, anonymous_1181];
  list<int> OperandCycles = [9, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1183 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMUL32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [7, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1184 {	// InstrStage
  int Cycles = 11;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1185 {	// InstrStage
  int Cycles = 11;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1186 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMUL64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1184, anonymous_1185];
  list<int> OperandCycles = [11, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1187 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMAC32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [7, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1188 {	// InstrStage
  int Cycles = 19;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1189 {	// InstrStage
  int Cycles = 19;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_119 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_81, anonymous_112];
  string NAME = ?;
}
def anonymous_1190 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMAC64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1188, anonymous_1189];
  list<int> OperandCycles = [19, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1191 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpFMAC32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [7, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1192 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpFMAC64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1188, anonymous_1189];
  list<int> OperandCycles = [19, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1193 {	// InstrStage
  int Cycles = 20;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1194 {	// InstrStage
  int Cycles = 20;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1195 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpDIV32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1193, anonymous_1194];
  list<int> OperandCycles = [20, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1196 {	// InstrStage
  int Cycles = 29;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1197 {	// InstrStage
  int Cycles = 29;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1198 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpDIV64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1196, anonymous_1197];
  list<int> OperandCycles = [29, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1199 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpSQRT32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1188, anonymous_1189];
  list<int> OperandCycles = [19, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_12 {	// LLVMType LLVMAnyPointerType
  ValueType VT = iPTRAny;
  int isAny = 1;
  LLVMType ElTy = anonymous_6;
  string NAME = ?;
}
def anonymous_120 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_81, anonymous_112];
  string NAME = ?;
}
def anonymous_1200 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpSQRT64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1196, anonymous_1197];
  list<int> OperandCycles = [29, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1201 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVIS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1202 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVID;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1203 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVSI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [20, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1204 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVDI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [20, 20, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1205 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1206 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1205, anonymous_1092];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1207 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1205, anonymous_1092];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1208 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad_m;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1205, anonymous_1092, anonymous_1205, anonymous_1092];
  list<int> OperandCycles = [1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1209 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad_mu;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1205, anonymous_1092, anonymous_1205, anonymous_1092];
  list<int> OperandCycles = [2, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_121 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "LOAD_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89, anonymous_114];
  string NAME = ?;
}
def anonymous_1210 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1205, anonymous_1092];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1211 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1205, anonymous_1092];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1212 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore_m;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1205, anonymous_1092, anonymous_1205, anonymous_1092];
  list<int> OperandCycles = [1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1213 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore_mu;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1205, anonymous_1092, anonymous_1205, anonymous_1092];
  list<int> OperandCycles = [2, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1214 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1215 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1216 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1217 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1218 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1219 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_122 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_87, anonymous_112];
  string NAME = ?;
}
def anonymous_1220 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1221 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1222 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x3u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1223 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x4u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1224 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [3, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1225 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [3, 2, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1226 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1dup;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1227 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1dupu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1228 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1229 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2x2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_123 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_87, anonymous_112];
  string NAME = ?;
}
def anonymous_1230 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [3, 3, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1231 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 2, 2, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1232 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2x2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1233 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [3, 3, 2, 1, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1234 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2dup;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1235 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2dupu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1236 {	// InstrStage
  int Cycles = 4;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1237 {	// InstrStage
  int Cycles = 4;
  list<FuncUnit> Units = [A8_LSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1238 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [3, 3, 4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1239 {	// InstrStage
  int Cycles = 5;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_124 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "LOAD_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95, anonymous_114];
  string NAME = ?;
}
def anonymous_1240 {	// InstrStage
  int Cycles = 5;
  list<FuncUnit> Units = [A8_LSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1241 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1239, anonymous_1240];
  list<int> OperandCycles = [4, 4, 5, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1242 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [3, 3, 4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1243 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1239, anonymous_1240];
  list<int> OperandCycles = [4, 4, 5, 2, 1, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1244 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3dup;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1245 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3dupu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1246 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [3, 3, 4, 4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1247 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1239, anonymous_1240];
  list<int> OperandCycles = [4, 4, 5, 5, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1248 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [3, 3, 4, 4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1249 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1239, anonymous_1240];
  list<int> OperandCycles = [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_125 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_93, anonymous_112];
  string NAME = ?;
}
def anonymous_1250 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4dup;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1251 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4dupu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 2, 3, 3, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1252 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1253 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1254 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1255 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1256 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1257 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1258 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x3u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1259 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x4u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_126 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_93, anonymous_112];
  string NAME = ?;
}
def anonymous_1260 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1261 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1062, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1262 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1263 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2x2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1264 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1265 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2x2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1266 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1267 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1214, anonymous_1127];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1268 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1269 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST3u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_127 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "LOAD_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_114];
  string NAME = ?;
}
def anonymous_1270 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST3ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1271 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST3lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1217, anonymous_1133];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1272 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1273 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST4u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1274 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST4ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1275 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST4lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1236, anonymous_1237];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1276 {	// InstrItinData
  InstrItinClass TheClass = IIC_VUNAD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [5, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1277 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1278 {	// InstrItinData
  InstrItinClass TheClass = IIC_VUNAQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [6, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1279 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBIND;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [5, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_128 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_93, anonymous_112];
  string NAME = ?;
}
def anonymous_1280 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPBIND;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [5, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1281 {	// InstrItinData
  InstrItinClass TheClass = IIC_VFMULD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [5, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1282 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [6, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1283 {	// InstrItinData
  InstrItinClass TheClass = IIC_VFMULQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [6, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1284 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOV;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1285 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVImm;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1286 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1287 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A8_NLSPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1288 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1287];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1289 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVIS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_129 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_93, anonymous_112];
  string NAME = ?;
}
def anonymous_1290 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVID;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1291 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVSI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158];
  list<int> OperandCycles = [20, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1292 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVDI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158];
  list<int> OperandCycles = [20, 20, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1293 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVISL;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1287];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1294 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVN;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1295 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPERMD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1296 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPERMQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1287];
  list<int> OperandCycles = [3, 3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1297 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1298 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPERMQ3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158, anonymous_1297, anonymous_1287];
  list<int> OperandCycles = [4, 4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1299 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [9, 3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_13 {	// LLVMType LLVMMatchType LLVMVectorSameWidth
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = 0;
  ValueType ElTy = i1;
  string NAME = ?;
}
def anonymous_130 {	// AMDGPUArg
  LLVMType Type = llvm_anyfloat_ty;
  string Name = "vdata";
  string NAME = ?;
}
def anonymous_1300 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [10, 3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1301 {	// InstrItinData
  InstrItinClass TheClass = IIC_VFMACD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [9, 3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1302 {	// InstrItinData
  InstrItinClass TheClass = IIC_VFMACQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [10, 3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1303 {	// InstrItinData
  InstrItinClass TheClass = IIC_VRECSD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [9, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1304 {	// InstrItinData
  InstrItinClass TheClass = IIC_VRECSQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [10, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1305 {	// InstrItinData
  InstrItinClass TheClass = IIC_VCNTiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1306 {	// InstrItinData
  InstrItinClass TheClass = IIC_VCNTiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [4, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1307 {	// InstrItinData
  InstrItinClass TheClass = IIC_VUNAiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [4, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1308 {	// InstrItinData
  InstrItinClass TheClass = IIC_VUNAiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [4, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1309 {	// InstrItinData
  InstrItinClass TheClass = IIC_VQUNAiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_131 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "STORE";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_1310 {	// InstrItinData
  InstrItinClass TheClass = IIC_VQUNAiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1311 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1312 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1313 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINi4D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1314 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINi4Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1315 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSUBiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1316 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSUBiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1317 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSUBi4D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1318 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSUBi4Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1319 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSHLiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_132 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "STORE";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_1320 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSHLiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1321 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSHLi4D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1322 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSHLi4Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [5, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1323 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPALiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [6, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1324 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPALiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [7, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1325 {	// InstrItinData
  InstrItinClass TheClass = IIC_VABAD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [6, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1326 {	// InstrItinData
  InstrItinClass TheClass = IIC_VABAQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [6, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1327 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMULi16D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [6, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1328 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMULi32D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [7, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1329 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMULi16Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [7, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_133 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "STORE";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_1330 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A8_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1331 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMULi32Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160, anonymous_1214, anonymous_1330];
  list<int> OperandCycles = [9, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1332 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACi16D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160];
  list<int> OperandCycles = [6, 3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1333 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACi32D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [7, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1334 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACi16Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1277];
  list<int> OperandCycles = [7, 3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1335 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACi32Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1160, anonymous_1214, anonymous_1330];
  list<int> OperandCycles = [9, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1336 {	// InstrItinData
  InstrItinClass TheClass = IIC_VEXTD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1337 {	// InstrItinData
  InstrItinClass TheClass = IIC_VEXTQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1287];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1338 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTB1;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1287];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1339 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTB2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1287];
  list<int> OperandCycles = [3, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_134 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "STORE";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_1340 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTB3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158, anonymous_1297, anonymous_1287];
  list<int> OperandCycles = [4, 2, 2, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1341 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTB4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158, anonymous_1297, anonymous_1287];
  list<int> OperandCycles = [4, 2, 2, 3, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1342 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTBX1;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1287];
  list<int> OperandCycles = [3, 1, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1343 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTBX2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1287];
  list<int> OperandCycles = [3, 1, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1344 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTBX3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158, anonymous_1297, anonymous_1287];
  list<int> OperandCycles = [4, 1, 2, 2, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1345 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTBX4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1112, anonymous_1158, anonymous_1297, anonymous_1287];
  list<int> OperandCycles = [4, 1, 2, 2, 3, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1346 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_Issue0, A9_Issue1];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1347 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_ALU0, A9_ALU1];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1348 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1349 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_135 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "STORE";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_1350 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1351 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_ALU0, A9_ALU1];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1352 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1353 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVix2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347, anonymous_1347];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1354 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVix2addpc;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347, anonymous_1347, anonymous_1347];
  list<int> OperandCycles = [3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1355 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_MUX0];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1356 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_AGU];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1357 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_LSUnit];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1358 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVix2ld;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347, anonymous_1347, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [5];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1359 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_136 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "STORE";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_1360 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [NoBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_1361 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1362 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A9_ALU0, A9_ALU1];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1363 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1362];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1364 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUx;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1365 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [NoBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_1366 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [NoBypass, A9_LdBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_1367 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [NoBypass, A9_LdBypass, NoBypass];
  string NAME = ?;
}
def anonymous_1368 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUsir;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [NoBypass, NoBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_1369 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1362];
  list<int> OperandCycles = [3, 1, 1, 1];
  list<Bypass> Bypasses = [NoBypass, A9_LdBypass, NoBypass, NoBypass];
  string NAME = ?;
}
def anonymous_137 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "STORE";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_1370 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1371 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1372 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1373 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1362];
  list<int> OperandCycles = [3, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1374 {	// InstrItinData
  InstrItinClass TheClass = IIC_iUNAr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1375 {	// InstrItinData
  InstrItinClass TheClass = IIC_iUNAsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1376 {	// InstrItinData
  InstrItinClass TheClass = IIC_iEXTr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1377 {	// InstrItinData
  InstrItinClass TheClass = IIC_iEXTAr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1378 {	// InstrItinData
  InstrItinClass TheClass = IIC_iEXTAsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1362];
  list<int> OperandCycles = [3, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1379 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_138 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "STORE";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_1380 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [A9_LdBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_1381 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [A9_LdBypass, NoBypass];
  string NAME = ?;
}
def anonymous_1382 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1362];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass, NoBypass, NoBypass];
  string NAME = ?;
}
def anonymous_1383 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1384 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1385 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1386 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1362];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1387 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1388 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1389 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_139 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "STORE_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_114];
  string NAME = ?;
}
def anonymous_1390 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1351];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1391 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVix2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1347, anonymous_1346, anonymous_1347];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1392 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_ALU0];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1393 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMUL16;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1392];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1394 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMAC16;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1392];
  list<int> OperandCycles = [3, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1395 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMUL32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1392];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1396 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMAC32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1392];
  list<int> OperandCycles = [4, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1397 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A9_ALU0];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1398 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMUL64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1397];
  list<int> OperandCycles = [4, 5, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1399 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMAC64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1397];
  list<int> OperandCycles = [4, 5, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_14 {	// LLVMType LLVMMatchType LLVMVectorOfAnyPointersToElt
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = 0;
  string NAME = ?;
}
def anonymous_140 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "STORE_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_114];
  string NAME = ?;
}
def anonymous_1400 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1401 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_AGU];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1402 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1401, anonymous_1357];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1403 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_d_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1401, anonymous_1357];
  list<int> OperandCycles = [3, 3, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1404 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1405 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1401, anonymous_1357];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1406 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_d_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1401, anonymous_1357];
  list<int> OperandCycles = [3, 3, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1407 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_LSUnit];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1408 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1407];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1409 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1401, anonymous_1357];
  list<int> OperandCycles = [5, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_141 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "STORE_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83, anonymous_114];
  string NAME = ?;
}
def anonymous_1410 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1411 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1401, anonymous_1357];
  list<int> OperandCycles = [4, 3, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1412 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [3, 2, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1413 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1401, anonymous_1357];
  list<int> OperandCycles = [4, 3, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1414 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_d_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1401, anonymous_1357];
  list<int> OperandCycles = [3, 3, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1415 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [4, 3, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1416 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1401, anonymous_1357];
  list<int> OperandCycles = [5, 4, 1, 1];
  list<Bypass> Bypasses = [A9_LdBypass];
  string NAME = ?;
}
def anonymous_1417 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_AGU];
  int TimeInc = 1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1418 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_LSUnit];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1419 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_m;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1418];
  list<int> OperandCycles = [1, 1, 1, 1, 3];
  list<Bypass> Bypasses = [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_142 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "STORE_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89, anonymous_114];
  string NAME = ?;
}
def anonymous_1420 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_mu;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1418];
  list<int> OperandCycles = [2, 1, 1, 1, 3];
  list<Bypass> Bypasses = [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_1421 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_AGU];
  int TimeInc = 1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1422 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_Branch];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1423 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_mBr;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1421, anonymous_1418, anonymous_1422];
  list<int> OperandCycles = [1, 2, 1, 1, 3];
  list<Bypass> Bypasses = [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_1424 {	// InstrItinData
  InstrItinClass TheClass = IIC_iPop;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1418];
  list<int> OperandCycles = [1, 1, 3];
  list<Bypass> Bypasses = [NoBypass, NoBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_1425 {	// InstrItinData
  InstrItinClass TheClass = IIC_iPop_Br;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1418, anonymous_1422];
  list<int> OperandCycles = [1, 1, 3];
  list<Bypass> Bypasses = [NoBypass, NoBypass, A9_LdBypass];
  string NAME = ?;
}
def anonymous_1426 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoadiALU;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357, anonymous_1347];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1427 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1428 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1357];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1429 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_d_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1357];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_143 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "STORE_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95, anonymous_114];
  string NAME = ?;
}
def anonymous_1430 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1431 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1432 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_d_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1433 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1434 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1435 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1436 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1357];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1437 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [2, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1438 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1357];
  list<int> OperandCycles = [3, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1439 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_d_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1357];
  list<int> OperandCycles = [3, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_144 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "STORE_MIP";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [];
  list<AMDGPUArg> DataArgs = [anonymous_130];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_112];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_114];
  string NAME = ?;
}
def anonymous_1440 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1357];
  list<int> OperandCycles = [2, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1441 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_bh_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1417, anonymous_1357];
  list<int> OperandCycles = [3, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1442 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_m;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1418];
  list<int> OperandCycles = [];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1443 {	// InstrItinData
  InstrItinClass TheClass = IIC_iStore_mu;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1356, anonymous_1418];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1444 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_Issue0, A9_Issue1];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1445 {	// InstrItinData
  InstrItinClass TheClass = IIC_Preload;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1444];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1446 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_Issue0];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1447 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_Issue1];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1448 {	// InstrItinData
  InstrItinClass TheClass = IIC_Br;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1446, anonymous_1447, anonymous_1422];
  list<int> OperandCycles = [];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1449 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_145 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_149];
  string NAME = ?;
}
def anonymous_1450 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1451 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1452 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpSTAT;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1450, anonymous_1451];
  list<int> OperandCycles = [1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1453 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1454 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpUNA32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1453, anonymous_1451];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1455 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpUNA64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1453, anonymous_1451];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1456 {	// InstrStage
  int Cycles = 5;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1457 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCMP32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1458 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCMP64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1459 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTSD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_146 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31];
  string NAME = ?;
}
def anonymous_1460 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTDS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1461 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTSH;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1462 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTHS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1453, anonymous_1451];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1463 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTSI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1464 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTDI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1465 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTIS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1466 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpCVTID;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1467 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpALU32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1468 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpALU64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1456, anonymous_1451];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1469 {	// InstrStage
  int Cycles = 6;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_147 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31];
  string NAME = ?;
}
def anonymous_1470 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMUL32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1469, anonymous_1451];
  list<int> OperandCycles = [5, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1471 {	// InstrStage
  int Cycles = 7;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1472 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1473 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMUL64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1471, anonymous_1472];
  list<int> OperandCycles = [6, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1474 {	// InstrStage
  int Cycles = 9;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1475 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMAC32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1474, anonymous_1451];
  list<int> OperandCycles = [8, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1476 {	// InstrStage
  int Cycles = 10;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1477 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMAC64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1476, anonymous_1472];
  list<int> OperandCycles = [9, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1478 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpFMAC32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1474, anonymous_1451];
  list<int> OperandCycles = [8, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1479 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpFMAC64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1476, anonymous_1472];
  list<int> OperandCycles = [9, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_148 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "s";
  string NAME = ?;
}
def anonymous_1480 {	// InstrStage
  int Cycles = 16;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1481 {	// InstrStage
  int Cycles = 10;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1482 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpDIV32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1480, anonymous_1481];
  list<int> OperandCycles = [15, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1483 {	// InstrStage
  int Cycles = 26;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1484 {	// InstrStage
  int Cycles = 20;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1485 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpDIV64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1483, anonymous_1484];
  list<int> OperandCycles = [25, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1486 {	// InstrStage
  int Cycles = 18;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1487 {	// InstrStage
  int Cycles = 13;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1488 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpSQRT32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1486, anonymous_1487];
  list<int> OperandCycles = [17, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1489 {	// InstrStage
  int Cycles = 33;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_149 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "s";
  string NAME = ?;
}
def anonymous_1490 {	// InstrStage
  int Cycles = 28;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1491 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpSQRT64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1489, anonymous_1490];
  list<int> OperandCycles = [32, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1492 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVIS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1453, anonymous_1451];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1493 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVID;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1453, anonymous_1451];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1494 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVSI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1495 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpMOVDI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1496 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1497 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1450, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1498 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1450, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1499 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad_m;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1450, anonymous_1496, anonymous_1418];
  list<int> OperandCycles = [1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_15 {	// LLVMType LLVMMatchType LLVMPointerToElt
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = 0;
  string NAME = ?;
}
def anonymous_150 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149];
  string NAME = ?;
}
def anonymous_1500 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpLoad_mu;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1450, anonymous_1496, anonymous_1418];
  list<int> OperandCycles = [2, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1501 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1450, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1502 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1450, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1503 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore_m;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1450, anonymous_1496, anonymous_1418];
  list<int> OperandCycles = [1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1504 {	// InstrItinData
  InstrItinClass TheClass = IIC_fpStore_mu;
  int NumMicroOps = -1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1449, anonymous_1450, anonymous_1496, anonymous_1418];
  list<int> OperandCycles = [2, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1505 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1506 {	// InstrStage
  int Cycles = 7;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1507 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1508 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1509 {	// InstrStage
  int Cycles = 8;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_151 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31];
  string NAME = ?;
}
def anonymous_1510 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1511 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [1, 1, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1512 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [1, 1, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1513 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1514 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1515 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x3u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [1, 1, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1516 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1x4u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [1, 1, 2, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1517 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [3, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1518 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [3, 2, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1519 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1dup;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_152 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_62];
  string NAME = ?;
}
def anonymous_1520 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD1dupu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1521 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1522 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2x2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [2, 3, 2, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1523 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [3, 3, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1524 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 2, 2, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1525 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2x2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [2, 3, 2, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1526 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [3, 3, 2, 1, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1527 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2dup;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1528 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD2dupu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1529 {	// InstrStage
  int Cycles = 9;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_153 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149];
  string NAME = ?;
}
def anonymous_1530 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1531 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A9_LSUnit];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1532 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [3, 3, 4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1533 {	// InstrStage
  int Cycles = 11;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1534 {	// InstrStage
  int Cycles = 5;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1535 {	// InstrStage
  int Cycles = 5;
  list<FuncUnit> Units = [A9_LSUnit];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1536 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1533, anonymous_1534, anonymous_1535];
  list<int> OperandCycles = [5, 5, 6, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1537 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [3, 3, 4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1538 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1533, anonymous_1534, anonymous_1535];
  list<int> OperandCycles = [5, 5, 6, 2, 1, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1539 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3dup;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [3, 3, 4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_154 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31];
  string NAME = ?;
}
def anonymous_1540 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD3dupu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [3, 3, 4, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1541 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [3, 3, 4, 4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1542 {	// InstrStage
  int Cycles = 10;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1543 {	// InstrStage
  int Cycles = 4;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1544 {	// InstrStage
  int Cycles = 4;
  list<FuncUnit> Units = [A9_LSUnit];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1545 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1542, anonymous_1543, anonymous_1544];
  list<int> OperandCycles = [4, 4, 5, 5, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1546 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [3, 3, 4, 4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1547 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1542, anonymous_1543, anonymous_1544];
  list<int> OperandCycles = [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1548 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4dup;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [2, 2, 3, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1549 {	// InstrItinData
  InstrItinClass TheClass = IIC_VLD4dupu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [2, 2, 3, 3, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_155 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_63];
  string NAME = ?;
}
def anonymous_1550 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1551 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1552 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1553 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1554 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1555 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1556 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1557 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1558 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x3u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1559 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1x4u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_156 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149];
  string NAME = ?;
}
def anonymous_1560 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1561 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST1lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1562 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1563 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1564 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2x2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1563, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1565 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1566 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2x2u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1563, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1567 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1568 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST2lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1496, anonymous_1357];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1569 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_157 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31];
  string NAME = ?;
}
def anonymous_1570 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST3u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1571 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST3ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1563, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1572 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST3lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1563, anonymous_1530, anonymous_1531];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1573 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1574 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST4u;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1575 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST4ln;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1576 {	// InstrItinData
  InstrItinClass TheClass = IIC_VST4lnu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1553, anonymous_1510, anonymous_1418];
  list<int> OperandCycles = [2, 1, 1, 1, 1, 1, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1577 {	// InstrItinData
  InstrItinClass TheClass = IIC_VUNAiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1578 {	// InstrItinData
  InstrItinClass TheClass = IIC_VUNAiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1579 {	// InstrItinData
  InstrItinClass TheClass = IIC_VQUNAiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_158 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63];
  string NAME = ?;
}
def anonymous_1580 {	// InstrItinData
  InstrItinClass TheClass = IIC_VQUNAiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1581 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1582 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1583 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSUBiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1584 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSUBiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1585 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSHLiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1586 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSHLiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1587 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSHLi4D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1588 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSHLi4Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1589 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINi4D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_159 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_1590 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINi4Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1591 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSUBi4D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1592 {	// InstrItinData
  InstrItinClass TheClass = IIC_VSUBi4Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1593 {	// InstrItinData
  InstrItinClass TheClass = IIC_VCNTiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1594 {	// InstrItinData
  InstrItinClass TheClass = IIC_VCNTiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [4, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1595 {	// InstrItinData
  InstrItinClass TheClass = IIC_VABAD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [6, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1596 {	// InstrItinData
  InstrItinClass TheClass = IIC_VABAQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1472];
  list<int> OperandCycles = [6, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1597 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPALiD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [6, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1598 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPALiQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1472];
  list<int> OperandCycles = [6, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1599 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMULi16D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [6, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_16 {	// IntrinsicProperty Returned
  int ArgNo = 0;
  string NAME = ?;
}
def anonymous_160 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "clamp";
  string NAME = ?;
}
def anonymous_1600 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMULi16Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [7, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1601 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMULi32D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [7, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1602 {	// InstrStage
  int Cycles = 4;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1603 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMULi32Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1542, anonymous_1602];
  list<int> OperandCycles = [9, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1604 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACi16D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [6, 3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1605 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACi32D;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [7, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1606 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACi16Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [7, 3, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1607 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACi32Q;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1542, anonymous_1602];
  list<int> OperandCycles = [9, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1608 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOV;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1550, anonymous_1451];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1609 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVImm;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_161 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_163];
  string NAME = ?;
}
def anonymous_1610 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1611 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1612 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVIS;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1563, anonymous_1451];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1613 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVID;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1563, anonymous_1451];
  list<int> OperandCycles = [1, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1614 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVSI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1563, anonymous_1451];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1615 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVDI;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1563, anonymous_1451];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1616 {	// InstrStage
  int Cycles = 4;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1617 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVISL;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1616, anonymous_1472];
  list<int> OperandCycles = [3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1618 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMOVN;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1619 {	// InstrItinData
  InstrItinClass TheClass = IIC_VUNAD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [5, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_162 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_163];
  string NAME = ?;
}
def anonymous_1620 {	// InstrItinData
  InstrItinClass TheClass = IIC_VUNAQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [6, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1621 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBIND;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [5, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1622 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPBIND;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [5, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1623 {	// InstrItinData
  InstrItinClass TheClass = IIC_VFMULD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [5, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1624 {	// InstrItinData
  InstrItinClass TheClass = IIC_VBINQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [6, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1625 {	// InstrItinData
  InstrItinClass TheClass = IIC_VFMULQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1451];
  list<int> OperandCycles = [6, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1626 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [6, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1627 {	// InstrItinData
  InstrItinClass TheClass = IIC_VMACQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1542, anonymous_1602];
  list<int> OperandCycles = [8, 4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1628 {	// InstrItinData
  InstrItinClass TheClass = IIC_VFMACD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [6, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1629 {	// InstrItinData
  InstrItinClass TheClass = IIC_VFMACQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1542, anonymous_1602];
  list<int> OperandCycles = [8, 4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_163 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "clamp";
  string NAME = ?;
}
def anonymous_1630 {	// InstrItinData
  InstrItinClass TheClass = IIC_VRECSD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1533, anonymous_1451];
  list<int> OperandCycles = [9, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1631 {	// InstrStage
  int Cycles = 12;
  list<FuncUnit> Units = [A9_DRegsVFP];
  int TimeInc = 0;
  int Kind = 1;
  string NAME = ?;
}
def anonymous_1632 {	// InstrItinData
  InstrItinClass TheClass = IIC_VRECSQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1631, anonymous_1472];
  list<int> OperandCycles = [10, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1633 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPERMD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [2, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1634 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPERMQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [3, 3, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1635 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [A9_NPipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1636 {	// InstrItinData
  InstrItinClass TheClass = IIC_VPERMQ3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1635];
  list<int> OperandCycles = [4, 4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1637 {	// InstrItinData
  InstrItinClass TheClass = IIC_VEXTD;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1506, anonymous_1451];
  list<int> OperandCycles = [2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1638 {	// InstrItinData
  InstrItinClass TheClass = IIC_VEXTQ;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [3, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1639 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTB1;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_164 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "clamp";
  string NAME = ?;
}
def anonymous_1640 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [A9_DRegsN];
  int TimeInc = 0;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_1641 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTB2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1640, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [3, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1642 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTB3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1640, anonymous_1529, anonymous_1635];
  list<int> OperandCycles = [4, 2, 2, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1643 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTB4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1635];
  list<int> OperandCycles = [4, 2, 2, 3, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1644 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTBX1;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [3, 1, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1645 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTBX2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1509, anonymous_1472];
  list<int> OperandCycles = [3, 1, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1646 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTBX3;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1635];
  list<int> OperandCycles = [4, 1, 2, 2, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1647 {	// InstrItinData
  InstrItinClass TheClass = IIC_VTBX4;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_1346, anonymous_1355, anonymous_1505, anonymous_1529, anonymous_1472];
  list<int> OperandCycles = [4, 1, 2, 2, 3, 3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_1648 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [A9UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteALUsi;
  string NAME = ?;
}
def anonymous_1649 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL16;
  SchedReadWrite AliasRW = A9WriteM16;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_165 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "clamp";
  string NAME = ?;
}
def anonymous_1650 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL32;
  SchedReadWrite AliasRW = A9WriteM;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1651 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL64Lo;
  SchedReadWrite AliasRW = A9WriteM;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1652 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL64Hi;
  SchedReadWrite AliasRW = A9WriteMHi;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1653 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC16;
  SchedReadWrite AliasRW = A9WriteM16;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1654 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC32;
  SchedReadWrite AliasRW = A9WriteM;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1655 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC64Lo;
  SchedReadWrite AliasRW = A9WriteM;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1656 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC64Hi;
  SchedReadWrite AliasRW = A9WriteMHi;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1657 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedRead ReadType = ReadMUL;
  string NAME = ?;
}
def anonymous_1658 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedRead ReadType = ReadMAC;
  string NAME = ?;
}
def anonymous_1659 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteVLD1;
  string NAME = ?;
}
def anonymous_166 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_1660 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteVLD2;
  string NAME = ?;
}
def anonymous_1661 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteVLD3;
  string NAME = ?;
}
def anonymous_1662 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteVLD4;
  string NAME = ?;
}
def anonymous_1663 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteVST1;
  string NAME = ?;
}
def anonymous_1664 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteVST2;
  string NAME = ?;
}
def anonymous_1665 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteVST3;
  string NAME = ?;
}
def anonymous_1666 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteVST4;
  string NAME = ?;
}
def anonymous_1667 {	// SchedAlias
  SchedReadWrite MatchRW = WriteLd;
  SchedReadWrite AliasRW = A9WriteL;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1668 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr1Pred;
  list<SchedReadWrite> Selected = [A9WriteAdr1];
  string NAME = ?;
}
def anonymous_1669 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr2Pred;
  list<SchedReadWrite> Selected = [A9WriteAdr2];
  string NAME = ?;
}
def anonymous_167 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_163];
  string NAME = ?;
}
def anonymous_1670 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr3Pred;
  list<SchedReadWrite> Selected = [A9WriteAdr3];
  string NAME = ?;
}
def anonymous_1671 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr4Pred;
  list<SchedReadWrite> Selected = [A9WriteAdr4];
  string NAME = ?;
}
def anonymous_1672 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr5Pred;
  list<SchedReadWrite> Selected = [A9WriteAdr5];
  string NAME = ?;
}
def anonymous_1673 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr6Pred;
  list<SchedReadWrite> Selected = [A9WriteAdr6];
  string NAME = ?;
}
def anonymous_1674 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr7Pred;
  list<SchedReadWrite> Selected = [A9WriteAdr7];
  string NAME = ?;
}
def anonymous_1675 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr8Pred;
  list<SchedReadWrite> Selected = [A9WriteAdr8];
  string NAME = ?;
}
def anonymous_1676 {	// SchedVar
  SchedPredicate Predicate = A9LMUnknownPred;
  list<SchedReadWrite> Selected = [A9WriteAdr2];
  string NAME = ?;
}
def anonymous_1677 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr1Pred;
  list<SchedReadWrite> Selected = [A9WriteL1, A9WriteL1Hi];
  string NAME = ?;
}
def anonymous_1678 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr2Pred;
  list<SchedReadWrite> Selected = [A9WriteL1, A9WriteL1Hi, A9WriteL2, A9WriteL2Hi];
  string NAME = ?;
}
def anonymous_1679 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr3Pred;
  list<SchedReadWrite> Selected = [A9WriteL1, A9WriteL1Hi, A9WriteL2, A9WriteL2Hi, A9WriteL3, A9WriteL3Hi];
  string NAME = ?;
}
def anonymous_168 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_1680 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr4Pred;
  list<SchedReadWrite> Selected = [A9WriteL1, A9WriteL1Hi, A9WriteL2, A9WriteL2Hi, A9WriteL3, A9WriteL3Hi, A9WriteL4, A9WriteL4Hi];
  string NAME = ?;
}
def anonymous_1681 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr5Pred;
  list<SchedReadWrite> Selected = [A9WriteL1, A9WriteL1Hi, A9WriteL2, A9WriteL2Hi, A9WriteL3, A9WriteL3Hi, A9WriteL4, A9WriteL4Hi, A9WriteL5, A9WriteL5Hi];
  string NAME = ?;
}
def anonymous_1682 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr6Pred;
  list<SchedReadWrite> Selected = [A9WriteL1, A9WriteL1Hi, A9WriteL2, A9WriteL2Hi, A9WriteL3, A9WriteL3Hi, A9WriteL4, A9WriteL4Hi, A9WriteL5, A9WriteL5Hi, A9WriteL6, A9WriteL6Hi];
  string NAME = ?;
}
def anonymous_1683 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr7Pred;
  list<SchedReadWrite> Selected = [A9WriteL1, A9WriteL1Hi, A9WriteL2, A9WriteL2Hi, A9WriteL3, A9WriteL3Hi, A9WriteL4, A9WriteL4Hi, A9WriteL5, A9WriteL5Hi, A9WriteL6, A9WriteL6Hi, A9WriteL7, A9WriteL7Hi];
  string NAME = ?;
}
def anonymous_1684 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr8Pred;
  list<SchedReadWrite> Selected = [A9WriteL1, A9WriteL1Hi, A9WriteL2, A9WriteL2Hi, A9WriteL3, A9WriteL3Hi, A9WriteL4, A9WriteL4Hi, A9WriteL5, A9WriteL5Hi, A9WriteL6, A9WriteL6Hi, A9WriteL7, A9WriteL7Hi, A9WriteL8, A9WriteL8Hi];
  string NAME = ?;
}
def anonymous_1685 {	// SchedVar
  SchedPredicate Predicate = A9LMUnknownPred;
  list<SchedReadWrite> Selected = [A9WriteL1, A9WriteL1Hi, A9WriteL2, A9WriteL2Hi, A9WriteL3Hi, A9WriteL3Hi, A9WriteL4Hi, A9WriteL4Hi, A9WriteL5Hi, A9WriteL5Hi, A9WriteL6Hi, A9WriteL6Hi, A9WriteL7Hi, A9WriteL7Hi, A9WriteL8Hi, A9WriteL8Hi];
  string NAME = ?;
}
def anonymous_1686 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr1Pred;
  list<SchedReadWrite> Selected = [A9WriteLfp1];
  string NAME = ?;
}
def anonymous_1687 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr2Pred;
  list<SchedReadWrite> Selected = [A9WriteLfp2];
  string NAME = ?;
}
def anonymous_1688 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr3Pred;
  list<SchedReadWrite> Selected = [A9WriteLfp3];
  string NAME = ?;
}
def anonymous_1689 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr4Pred;
  list<SchedReadWrite> Selected = [A9WriteLfp4];
  string NAME = ?;
}
def anonymous_169 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_163];
  string NAME = ?;
}
def anonymous_1690 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr5Pred;
  list<SchedReadWrite> Selected = [A9WriteLfp5];
  string NAME = ?;
}
def anonymous_1691 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr6Pred;
  list<SchedReadWrite> Selected = [A9WriteLfp6];
  string NAME = ?;
}
def anonymous_1692 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr7Pred;
  list<SchedReadWrite> Selected = [A9WriteLfp7];
  string NAME = ?;
}
def anonymous_1693 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr8Pred;
  list<SchedReadWrite> Selected = [A9WriteLfp8];
  string NAME = ?;
}
def anonymous_1694 {	// SchedVar
  SchedPredicate Predicate = A9LMUnknownPred;
  list<SchedReadWrite> Selected = [A9WriteLfp2];
  string NAME = ?;
}
def anonymous_1695 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr1Pred;
  list<SchedReadWrite> Selected = [A9WriteLMfp1, A9WriteLMfp1Hi];
  string NAME = ?;
}
def anonymous_1696 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr2Pred;
  list<SchedReadWrite> Selected = [A9WriteLMfp1, A9WriteLMfp2, A9WriteLMfp2Hi, A9WriteLMfp2Hi];
  string NAME = ?;
}
def anonymous_1697 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr3Pred;
  list<SchedReadWrite> Selected = [A9WriteLMfp1, A9WriteLMfp2, A9WriteLMfp3, A9WriteLMfp2Hi, A9WriteLMfp3Hi, A9WriteLMfp3Hi];
  string NAME = ?;
}
def anonymous_1698 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr4Pred;
  list<SchedReadWrite> Selected = [A9WriteLMfp1, A9WriteLMfp2, A9WriteLMfp3, A9WriteLMfp4, A9WriteLMfp3Hi, A9WriteLMfp3Hi, A9WriteLMfp4Hi, A9WriteLMfp4Hi];
  string NAME = ?;
}
def anonymous_1699 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr5Pred;
  list<SchedReadWrite> Selected = [A9WriteLMfp1, A9WriteLMfp2, A9WriteLMfp3, A9WriteLMfp4, A9WriteLMfp5, A9WriteLMfp3Hi, A9WriteLMfp4Hi, A9WriteLMfp4Hi, A9WriteLMfp5Hi, A9WriteLMfp5Hi];
  string NAME = ?;
}
def anonymous_17 {	// LLVMType LLVMMatchType LLVMExtendedType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = 0;
  string NAME = ?;
}
def anonymous_170 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_1700 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr6Pred;
  list<SchedReadWrite> Selected = [A9WriteLMfp1, A9WriteLMfp2, A9WriteLMfp3, A9WriteLMfp4, A9WriteLMfp5, A9WriteLMfp6, A9WriteLMfp4Hi, A9WriteLMfp4Hi, A9WriteLMfp5Hi, A9WriteLMfp5Hi, A9WriteLMfp6Hi, A9WriteLMfp6Hi];
  string NAME = ?;
}
def anonymous_1701 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr7Pred;
  list<SchedReadWrite> Selected = [A9WriteLMfp1, A9WriteLMfp2, A9WriteLMfp3, A9WriteLMfp4, A9WriteLMfp5, A9WriteLMfp6, A9WriteLMfp7, A9WriteLMfp4Hi, A9WriteLMfp5Hi, A9WriteLMfp5Hi, A9WriteLMfp6Hi, A9WriteLMfp6Hi, A9WriteLMfp7Hi, A9WriteLMfp7Hi];
  string NAME = ?;
}
def anonymous_1702 {	// SchedVar
  SchedPredicate Predicate = A9LMAdr8Pred;
  list<SchedReadWrite> Selected = [A9WriteLMfp1, A9WriteLMfp2, A9WriteLMfp3, A9WriteLMfp4, A9WriteLMfp5, A9WriteLMfp6, A9WriteLMfp7, A9WriteLMfp8, A9WriteLMfp5Hi, A9WriteLMfp5Hi, A9WriteLMfp6Hi, A9WriteLMfp6Hi, A9WriteLMfp7Hi, A9WriteLMfp7Hi, A9WriteLMfp8Hi, A9WriteLMfp8Hi];
  string NAME = ?;
}
def anonymous_1703 {	// SchedVar
  SchedPredicate Predicate = A9LMUnknownPred;
  list<SchedReadWrite> Selected = [A9WriteLMfp1, A9WriteLMfp2, A9WriteLMfp3Hi, A9WriteLMfp4Hi, A9WriteLMfp5Hi, A9WriteLMfp6Hi, A9WriteLMfp7Hi, A9WriteLMfp8Hi, A9WriteLMfp5Hi, A9WriteLMfp5Hi, A9WriteLMfp6Hi, A9WriteLMfp6Hi, A9WriteLMfp7Hi, A9WriteLMfp7Hi, A9WriteLMfp8Hi, A9WriteLMfp8Hi];
  string NAME = ?;
}
def anonymous_1704 {	// SchedVar
  SchedPredicate Predicate = A9PreRA;
  list<SchedReadWrite> Selected = [A9WriteLMfpPreRA];
  string NAME = ?;
}
def anonymous_1705 {	// SchedVar
  SchedPredicate Predicate = A9PostRA;
  list<SchedReadWrite> Selected = [A9WriteLMfpPostRA];
  string NAME = ?;
}
def anonymous_1706 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iMOVi, IIC_iMOVr, IIC_iMOVsi, IIC_iMVNi, IIC_iMVNsi, IIC_iCMOVi, IIC_iCMOVr, IIC_iCMOVsi];
  list<SchedReadWrite> OperandReadWrites = [WriteALU];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1707 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iMVNr];
  list<SchedReadWrite> OperandReadWrites = [WriteALU, A9ReadALU];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1708 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iMOVsr, IIC_iMVNsr, IIC_iCMOVsr];
  list<SchedReadWrite> OperandReadWrites = [A9WriteIsr];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1709 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iMOVix2, IIC_iCMOVix2];
  list<SchedReadWrite> OperandReadWrites = [A9WriteI2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_171 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_163];
  string NAME = ?;
}
def anonymous_1710 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iMOVix2addpc];
  list<SchedReadWrite> OperandReadWrites = [A9WriteI2pc];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1711 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iMOVix2ld];
  list<SchedReadWrite> OperandReadWrites = [A9WriteI2ld];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1712 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iBITi, IIC_iBITr, IIC_iUNAr, IIC_iTSTi, IIC_iTSTr];
  list<SchedReadWrite> OperandReadWrites = [WriteALU];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1713 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iALUi, IIC_iCMPi, IIC_iCMPsi];
  list<SchedReadWrite> OperandReadWrites = [WriteALU, A9ReadALU];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1714 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iALUr, IIC_iCMPr];
  list<SchedReadWrite> OperandReadWrites = [WriteALU, A9ReadALU, A9ReadALU];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1715 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iBITsi, IIC_iUNAsi, IIC_iEXTr, IIC_iTSTsi];
  list<SchedReadWrite> OperandReadWrites = [WriteALUsi];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1716 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iALUsi];
  list<SchedReadWrite> OperandReadWrites = [WriteALUsi, A9ReadALU];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1717 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iALUsir];
  list<SchedReadWrite> OperandReadWrites = [WriteALUsi, ReadDefault, A9ReadALU];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1718 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iBITsr, IIC_iTSTsr, IIC_iEXTAr, IIC_iEXTAsr];
  list<SchedReadWrite> OperandReadWrites = [A9WriteALUsr];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1719 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iALUsr, IIC_iCMPsr];
  list<SchedReadWrite> OperandReadWrites = [A9WriteALUsr, A9ReadALU];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_172 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149];
  string NAME = ?;
}
def anonymous_1720 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iMUL32, IIC_iMAC32, IIC_iMUL64, IIC_iMAC64];
  list<SchedReadWrite> OperandReadWrites = [A9WriteM, A9WriteMHi];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1721 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iMUL16, IIC_iMAC16];
  list<SchedReadWrite> OperandReadWrites = [A9WriteM16, A9WriteM16Hi];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1722 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpSTAT, IIC_fpMOVIS, IIC_fpMOVID, IIC_fpMOVSI, IIC_fpUNA32, IIC_fpUNA64, IIC_fpCMP32, IIC_fpCMP64];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFMov];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1723 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpMOVDI];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFMov, A9WriteFMov];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1724 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpCVTSD, IIC_fpCVTDS, IIC_fpCVTSH, IIC_fpCVTHS, IIC_fpCVTIS, IIC_fpCVTID, IIC_fpCVTSI, IIC_fpCVTDI, IIC_fpALU32, IIC_fpALU64];
  list<SchedReadWrite> OperandReadWrites = [A9WriteF];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1725 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpMUL32];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFMulS];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1726 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpMUL64];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFMulD];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1727 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpMAC32];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFMAS];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1728 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpMAC64];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFMAD];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1729 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpDIV32];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFDivS];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_173 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31];
  string NAME = ?;
}
def anonymous_1730 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpDIV64];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFDivD];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1731 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpSQRT32];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFSqrtS];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1732 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpSQRT64];
  list<SchedReadWrite> OperandReadWrites = [A9WriteFSqrtD];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1733 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_Br];
  list<SchedReadWrite> OperandReadWrites = [A9WriteB];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1734 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_Preload];
  list<SchedReadWrite> OperandReadWrites = [];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1735 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iLoad_i, IIC_iLoad_r, IIC_iLoad_iu, IIC_iLoad_ru];
  list<SchedReadWrite> OperandReadWrites = [A9WriteL, A9WriteAdr];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1736 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iLoad_si, IIC_iLoad_siu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLsi, A9WriteAdr];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1737 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iLoad_bh_i, IIC_iLoad_bh_r, IIC_iLoad_bh_iu, IIC_iLoad_bh_ru];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLb, A9WriteAdr2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1738 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iLoad_bh_si, IIC_iLoad_bh_siu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLbsi, A9WriteAdr2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1739 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iLoad_d_i, IIC_iLoad_d_r, IIC_iLoad_d_ru];
  list<SchedReadWrite> OperandReadWrites = [A9WriteL, A9WriteLHi, A9WriteAdr];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_174 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_64];
  string NAME = ?;
}
def anonymous_1740 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iStore_i, IIC_iStore_r, IIC_iStore_iu, IIC_iStore_ru, IIC_iStore_d_i, IIC_iStore_d_r, IIC_iStore_d_ru];
  list<SchedReadWrite> OperandReadWrites = [A9WriteAdr, A9WriteS];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1741 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iStore_si, IIC_iStore_siu, IIC_iStore_bh_i, IIC_iStore_bh_r, IIC_iStore_bh_iu, IIC_iStore_bh_ru];
  list<SchedReadWrite> OperandReadWrites = [A9WriteAdr2, A9WriteS];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1742 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iStore_bh_si, IIC_iStore_bh_siu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteAdr3, A9WriteS];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1743 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iLoad_m, IIC_iPop];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLM, A9WriteLMAdr, A9WriteIssue];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1744 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iLoad_mu, IIC_iStore_m, IIC_iStore_mu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLMAdr, A9WriteLM, A9WriteIssue];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1745 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iLoad_mBr, IIC_iPop_Br];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLM, A9WriteLMAdr, A9WriteB];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1746 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_iLoadiALU];
  list<SchedReadWrite> OperandReadWrites = [A9WriteL, A9WriteAdr, WriteALU];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1747 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpLoad32, IIC_fpLoad64];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLSfp, A9WriteAdr];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1748 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpLoad_m];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLMfp, A9WriteLMAdr];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1749 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpLoad_mu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLMAdr, A9WriteLMfp];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_175 {	// arglistmatchshift
  list<AMDGPUArg> ret = [];
  string NAME = ?;
}
def anonymous_1750 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_fpStore32, IIC_fpStore64, IIC_fpStore_m, IIC_fpStore_mu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteAdr, A9WriteLSfp];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1751 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VLD1, IIC_VLD1u, IIC_VLD1x2, IIC_VLD1x2u];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLfp1, A9WriteAdr1];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1752 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VLD1x3, IIC_VLD1x3u, IIC_VLD1x4, IIC_VLD1x4u, IIC_VLD4dup, IIC_VLD4dupu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLfp2, A9WriteAdr2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1753 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VLD1dup, IIC_VLD1dupu, IIC_VLD2, IIC_VLD2u, IIC_VLD2dup, IIC_VLD2dupu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLfp1Mov, A9WriteAdr1];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1754 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VLD1ln, IIC_VLD1lnu, IIC_VLD2x2, IIC_VLD2x2u, IIC_VLD2ln, IIC_VLD2lnu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLfp2Mov, A9WriteAdr1];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1755 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VLD3, IIC_VLD3u, IIC_VLD3dup, IIC_VLD3dupu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLfp3Mov, A9WriteAdr3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1756 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VLD4, IIC_VLD4u, IIC_VLD4ln, IIC_VLD4lnu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLfp4Mov, A9WriteAdr4];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1757 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VLD3ln, IIC_VLD3lnu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteLfp5Mov, A9WriteAdr5];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1758 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VST1, IIC_VST1u, IIC_VST1x2, IIC_VST1x2u, IIC_VST1ln, IIC_VST1lnu, IIC_VST2, IIC_VST2u, IIC_VST2x2, IIC_VST2x2u, IIC_VST2ln, IIC_VST2lnu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteAdr1, A9WriteLfp1];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1759 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VST1x3, IIC_VST1x3u, IIC_VST1x4, IIC_VST1x4u, IIC_VST3, IIC_VST3u, IIC_VST3ln, IIC_VST3lnu, IIC_VST4, IIC_VST4u, IIC_VST4ln, IIC_VST4lnu];
  list<SchedReadWrite> OperandReadWrites = [A9WriteAdr2, A9WriteLfp2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_176 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31];
  string NAME = ?;
}
def anonymous_1760 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMOVSI, IIC_VMOVDI, IIC_VMOVD, IIC_VMOVQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1761 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMOV, IIC_VMOVIS, IIC_VMOVID];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV1];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1762 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMOVISL, IIC_VMOVN];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1763 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VBINiD, IIC_VBINiQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1764 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VSUBiD, IIC_VSUBiQ, IIC_VCNTiD];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1765 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VBINi4D, IIC_VBINi4Q];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV4, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1766 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VSUBi4D, IIC_VSUBi4Q];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV4, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1767 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VQUNAiD, IIC_VQUNAiQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV4];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1768 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VUNAiD, IIC_VUNAiQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV4, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1769 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VCNTiQ];
  list<SchedReadWrite> OperandReadWrites = [A9Write2V4, A9Read3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_177 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "bias";
  string NAME = ?;
}
def anonymous_1770 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMOVImm];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1771 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VABAD, IIC_VABAQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV6, A9Read3, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1772 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VPALiD, IIC_VPALiQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV6, A9Read3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1773 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMULi16D];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV6, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1774 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMULi16Q];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV7, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1775 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMULi32D];
  list<SchedReadWrite> OperandReadWrites = [A9Write2V7, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1776 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMULi32Q];
  list<SchedReadWrite> OperandReadWrites = [A9Write2V9, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1777 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMACi16D];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV6, A9Read3, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1778 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMACi16Q];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV7, A9Read3, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1779 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMACi32D];
  list<SchedReadWrite> OperandReadWrites = [A9Write2V7, A9Read3, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_178 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "bias";
  string NAME = ?;
}
def anonymous_1780 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMACi32Q];
  list<SchedReadWrite> OperandReadWrites = [A9Write2V9, A9Read3, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1781 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VSHLiD, IIC_VSHLiQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1782 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VSHLi4D, IIC_VSHLi4Q];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV4];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1783 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VPERMD, IIC_VPERMQ, IIC_VEXTD];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV2, A9WriteV2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1784 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VPERMQ3, IIC_VEXTQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3, A9WriteV4, ReadDefault, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1785 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VTB1];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1786 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VTB2];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1787 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VTB3];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV4, A9Read2, A9Read2, A9Read3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1788 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VTB4];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV4, A9Read2, A9Read2, A9Read3, A9Read3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1789 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VTBX1];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3, ReadDefault, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_179 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149];
  string NAME = ?;
}
def anonymous_1790 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VTBX2];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV3, ReadDefault, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1791 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VTBX3];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV4, ReadDefault, A9Read2, A9Read2, A9Read3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1792 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VTBX4];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV4, ReadDefault, A9Read2, A9Read2, A9Read3, A9Read3];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1793 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VBIND];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV5, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1794 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VBINQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV6, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1795 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VUNAD, IIC_VFMULD];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV5, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1796 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VUNAQ, IIC_VFMULQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV6, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1797 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMACD, IIC_VFMACD];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV9, A9Read3, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1798 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VMACQ, IIC_VFMACQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV10, A9Read3, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1799 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VRECSD];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV9, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_18 {	// LLVMType LLVMMatchType LLVMTruncatedType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = 0;
  string NAME = ?;
}
def anonymous_180 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31];
  string NAME = ?;
}
def anonymous_1800 {	// ItinRW
  list<InstrItinClass> MatchedItinClasses = [IIC_VRECSQ];
  list<SchedReadWrite> OperandReadWrites = [A9WriteV10, A9Read2, A9Read2];
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1801 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALU;
  SchedReadWrite AliasRW = A9WriteALU;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1802 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALUsr;
  SchedReadWrite AliasRW = A9WriteALUsr;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1803 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALUSsr;
  SchedReadWrite AliasRW = A9WriteALUsr;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1804 {	// SchedAlias
  SchedReadWrite MatchRW = ReadALU;
  SchedReadWrite AliasRW = A9ReadALU;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1805 {	// SchedAlias
  SchedReadWrite MatchRW = ReadALUsr;
  SchedReadWrite AliasRW = A9ReadALU;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1806 {	// SchedAlias
  SchedReadWrite MatchRW = WriteST;
  SchedReadWrite AliasRW = A9WriteS;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1807 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [A9UnitFP, A9UnitAGU];
  list<int> ResourceCycles = [];
  int Latency = 4;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteFPCVT;
  string NAME = ?;
}
def anonymous_1808 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMOV;
  SchedReadWrite AliasRW = A9WriteFMov;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1809 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPALU32;
  SchedReadWrite AliasRW = A9WriteF;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_181 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64];
  string NAME = ?;
}
def anonymous_1810 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPALU64;
  SchedReadWrite AliasRW = A9WriteF;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1811 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMUL32;
  SchedReadWrite AliasRW = A9WriteFMulS;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1812 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMUL64;
  SchedReadWrite AliasRW = A9WriteFMulD;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1813 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMAC32;
  SchedReadWrite AliasRW = A9WriteFMAS;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1814 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMAC64;
  SchedReadWrite AliasRW = A9WriteFMAD;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1815 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPDIV32;
  SchedReadWrite AliasRW = A9WriteFDivS;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1816 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPDIV64;
  SchedReadWrite AliasRW = A9WriteFDivD;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1817 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPSQRT32;
  SchedReadWrite AliasRW = A9WriteFSqrtS;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1818 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPSQRT64;
  SchedReadWrite AliasRW = A9WriteFSqrtD;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1819 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedRead ReadType = ReadFPMUL;
  string NAME = ?;
}
def anonymous_182 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149];
  string NAME = ?;
}
def anonymous_1820 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedRead ReadType = ReadFPMAC;
  string NAME = ?;
}
def anonymous_1821 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteALU];
  dag Instrs = (instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr", "EORrr", "BICrr");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1822 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteALUsi];
  dag Instrs = (instregex "ANDrsi", "ORRrsi", "EORrsi", "BICrsi");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1823 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteALUsr];
  dag Instrs = (instregex "ANDrsr", "ORRrsr", "EORrsr", "BICrsr");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1824 {	// SchedAlias
  SchedReadWrite MatchRW = WriteCMP;
  SchedReadWrite AliasRW = A9WriteALU;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1825 {	// SchedAlias
  SchedReadWrite MatchRW = WriteCMPsi;
  SchedReadWrite AliasRW = A9WriteALU;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1826 {	// SchedAlias
  SchedReadWrite MatchRW = WriteCMPsr;
  SchedReadWrite AliasRW = A9WriteALU;
  SchedMachineModel SchedModel = CortexA9Model;
  string NAME = ?;
}
def anonymous_1827 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteIsr];
  dag Instrs = (instregex "MOVsr", "MOVsi", "MVNsr", "MOVCCsi", "MOVCCsr");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1828 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteALU, A9ReadALU];
  dag Instrs = (instregex "MVNr");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1829 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteI2];
  dag Instrs = (instregex "MOVCCi32imm", "MOVi32imm");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_183 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31];
  string NAME = ?;
}
def anonymous_1830 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteI2pc];
  dag Instrs = (instregex "MOV_ga_pcrel");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1831 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteI2ld];
  dag Instrs = (instregex "MOV_ga_pcrel_ldr");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1832 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteALU];
  dag Instrs = (instregex "SEL");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1833 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteALUsi];
  dag Instrs = (instregex "BFC", "BFI", "UBFX", "SBFX");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1834 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteM];
  dag Instrs = (instregex "MUL", "MULv5", "SMMUL", "SMMULR", "MLA", "MLAv5", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1835 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteM, A9WriteMHi];
  dag Instrs = (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL", "UMAAL", "SMLALv5", "UMLALv5", "SMLALBB", "SMLALBT", "SMLALTB", "SMLALTT");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1836 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteM, A9WriteMHi];
  dag Instrs = (instregex "SMLAD", "SMLADX", "SMLALD", "SMLALDX", "SMLSD", "SMLSDX", "SMLSLD", "SMLSLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1837 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteM16, A9WriteM16Hi];
  dag Instrs = (instregex "SMULBB", "SMULBT", "SMULTB", "SMULTT", "SMULWB", "SMULWT");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1838 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteM16, A9WriteM16Hi];
  dag Instrs = (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLAWB", "SMLAWT");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1839 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteL];
  dag Instrs = (instregex "LDRi12", "PICLDR$");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_184 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63];
  string NAME = ?;
}
def anonymous_1840 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteLsi];
  dag Instrs = (instregex "LDRrs");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1841 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteLb];
  dag Instrs = (instregex "LDRBi12", "PICLDRH", "PICLDRB", "PICLDRSH", "PICLDRSB", "LDRH", "LDRSH", "LDRSB");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1842 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A9WriteLbsi];
  dag Instrs = (instregex "LDRrs");
  SchedMachineModel SchedModel = CortexA9Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1843 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteDIV;
  string NAME = ?;
}
def anonymous_1844 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [A9UnitB];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteBr;
  string NAME = ?;
}
def anonymous_1845 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [A9UnitB];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteBrL;
  string NAME = ?;
}
def anonymous_1846 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [A9UnitB];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteBrTbl;
  string NAME = ?;
}
def anonymous_1847 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WritePreLd;
  string NAME = ?;
}
def anonymous_1848 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA9Model;
  SchedWrite WriteType = WriteNoop;
  string NAME = ?;
}
def anonymous_1849 {	// SchedVar
  SchedPredicate Predicate = IsFastImmShiftSwiftPred;
  list<SchedReadWrite> Selected = [SwiftWriteP01TwoCycle];
  string NAME = ?;
}
def anonymous_185 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149];
  string NAME = ?;
}
def anonymous_1850 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [WriteALU];
  string NAME = ?;
}
def anonymous_1851 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [SwiftWriteP01ThreeCycleTwoUops];
  string NAME = ?;
}
def anonymous_1852 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [SwiftWriteP01TwoCycle];
  string NAME = ?;
}
def anonymous_1853 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [SwiftWriteP0ThreeCycleThreeUops];
  string NAME = ?;
}
def anonymous_1854 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 2;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_1855 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [anonymous_1854];
  string NAME = ?;
}
def anonymous_1856 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [NoReadAdvance];
  string NAME = ?;
}
def anonymous_1857 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteALU;
  string NAME = ?;
}
def anonymous_1858 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALUsi;
  SchedReadWrite AliasRW = SwiftWriteALUsi;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1859 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALUsr;
  SchedReadWrite AliasRW = SwiftWriteALUsr;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_186 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31];
  string NAME = ?;
}
def anonymous_1860 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALUSsr;
  SchedReadWrite AliasRW = SwiftWriteALUSsr;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1861 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedRead ReadType = ReadALU;
  string NAME = ?;
}
def anonymous_1862 {	// SchedAlias
  SchedReadWrite MatchRW = ReadALUsr;
  SchedReadWrite AliasRW = SwiftReadAdvanceALUsr;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1863 {	// SchedAlias
  SchedReadWrite MatchRW = WriteLd;
  SchedReadWrite AliasRW = SwiftWriteP2ThreeCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1864 {	// SchedAlias
  SchedReadWrite MatchRW = WriteST;
  SchedReadWrite AliasRW = SwiftWriteP2;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1865 {	// SchedVar
  SchedPredicate Predicate = IsFastImmShiftSwiftPred;
  list<SchedReadWrite> Selected = [SwiftWriteP01OneCycle];
  string NAME = ?;
}
def anonymous_1866 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP01];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteCMP;
  string NAME = ?;
}
def anonymous_1867 {	// SchedAlias
  SchedReadWrite MatchRW = WriteCMPsi;
  SchedReadWrite AliasRW = SwiftChooseShiftKindP01OneOrTwoCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1868 {	// SchedAlias
  SchedReadWrite MatchRW = WriteCMPsr;
  SchedReadWrite AliasRW = SwiftWriteP01TwoCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1869 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle];
  dag Instrs = (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16", "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", "t2UXTB16");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_187 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63];
  string NAME = ?;
}
def anonymous_1870 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle2x];
  dag Instrs = (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi32imm", "t2MOVi32imm");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1871 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle3x];
  dag Instrs = (instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel", "t2MOVi16_ga_pcrel");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1872 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle2x_load];
  dag Instrs = (instregex "MOV_ga_pcrel_ldr");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1873 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [SwiftWriteP0TwoCycleTwoUops];
  string NAME = ?;
}
def anonymous_1874 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [SwiftWriteP0OneCycle];
  string NAME = ?;
}
def anonymous_1875 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftPredP0OneOrTwoCycle];
  dag Instrs = (instregex "SEL", "t2SEL");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1876 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01TwoCycle];
  dag Instrs = (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI", "(t|t2)UBFX", "(t|t2)SBFX");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1877 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01TwoCycle];
  dag Instrs = (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT", "USAT16", "QADD8", "QADD16", "QSUB8", "QSUB16", "QASX", "QSAX", "UQADD8", "UQADD16", "UQSUB8", "UQSUB16", "UQASX", "UQSAX", "t2QADD", "t2QSUB", "t2QDADD", "t2QDSUB", "t2SSAT", "t2SSAT16", "t2USAT", "t2QADD8", "t2QADD16", "t2QSUB8", "t2QSUB16", "t2QASX", "t2QSAX", "t2UQADD8", "t2UQADD16", "t2UQSUB8", "t2UQSUB16", "t2UQASX", "t2UQSAX");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1878 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteALUsr];
  dag Instrs = (instregex "SADD8", "SADD16", "SSUB8", "SSUB16", "SASX", "SSAX", "UADD8", "UADD16", "USUB8", "USUB16", "UASX", "USAX", "t2SADD8", "t2SADD16", "t2SSUB8", "t2SSUB16", "t2SASX", "t2SSAX", "t2UADD8", "t2UADD16", "t2USUB8", "t2USUB16", "t2UASX", "t2USAX");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1879 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01TwoCycle];
  dag Instrs = (instregex "SHADD8", "SHADD16", "SHSUB8", "SHSUB16", "SHASX", "SHSAX", "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16", "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16", "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16", "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX", "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_188 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_1880 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0P1FourCycle];
  dag Instrs = (instregex "USAD8");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1881 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0P1FourCycle, ReadALU, ReadALU, anonymous_1854];
  dag Instrs = (instregex "USADA8");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1882 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0FourCycle];
  dag Instrs = (instregex "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDX", "t2MUL", "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT", "t2SMULWB", "t2SMULWT", "t2SMUSD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1883 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [SwiftWriteP0P01FiveCycleTwoUops];
  string NAME = ?;
}
def anonymous_1884 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [SwiftWriteP0FourCycle];
  string NAME = ?;
}
def anonymous_1885 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 4;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_1886 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [anonymous_1885];
  string NAME = ?;
}
def anonymous_1887 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [ReadALU];
  string NAME = ?;
}
def anonymous_1888 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU, SwiftReadAdvanceFourCyclesPred];
  dag Instrs = (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", "t2MLA", "t2MLS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", "t2SMMLSR");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1889 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0FourCycle];
  dag Instrs = (instregex "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_189 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_192];
  string NAME = ?;
}
def anonymous_1890 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU, SwiftReadAdvanceFourCyclesPred];
  dag Instrs = (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX", "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT", "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1891 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftPredP0P01FourFiveCycle];
  dag Instrs = (instregex "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1892 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftP0P0P01FiveCycle, SwiftWrite5Cycle];
  dag Instrs = (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1893 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL16;
  SchedReadWrite AliasRW = SwiftWriteP0FourCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1894 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL32;
  SchedReadWrite AliasRW = SwiftWriteP0FourCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1895 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL64Lo;
  SchedReadWrite AliasRW = SwiftP0P0P01FiveCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1896 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL64Hi;
  SchedReadWrite AliasRW = SwiftWrite5Cycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1897 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC16;
  SchedReadWrite AliasRW = SwiftPredP0P01FourFiveCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1898 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC32;
  SchedReadWrite AliasRW = SwiftPredP0P01FourFiveCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1899 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC64Lo;
  SchedReadWrite AliasRW = SwiftWrite5Cycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_19 {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = 1;
  string NAME = ?;
}
def anonymous_190 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_192];
  string NAME = ?;
}
def anonymous_1900 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC64Hi;
  SchedReadWrite AliasRW = Swift2P03P01FiveCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1901 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedRead ReadType = ReadMUL;
  string NAME = ?;
}
def anonymous_1902 {	// SchedAlias
  SchedReadWrite MatchRW = ReadMAC;
  SchedReadWrite AliasRW = SwiftReadAdvanceFourCyclesPred;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_1903 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite5Cycle, Swift2P03P01FiveCycle, ReadALU, ReadALU, anonymous_1885, anonymous_1904];
  dag Instrs = (instregex "SMLAL", "UMLAL", "SMLALBT", "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX", "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBB", "t2SMLALBT", "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX", "t2UMAAL");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1904 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_1905 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitDiv];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteDIV;
  string NAME = ?;
}
def anonymous_1906 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftDiv];
  dag Instrs = (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1907 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2ThreeCycle];
  dag Instrs = (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)", "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)", "tLDR(r|i|spi|pci|pciASM)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1908 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2ThreeCycle];
  dag Instrs = (instregex "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1909 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2P01FourCycle];
  dag Instrs = (instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$", "t2LDRpci_pic", "tLDRS(B|H)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_191 {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = 2;
  string NAME = ?;
}
def anonymous_1910 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2P01ThreeCycle, SwiftWrBackOne];
  dag Instrs = (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)", "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1911 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2P01P01FourCycle, SwiftWrBackOne];
  dag Instrs = (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)", "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)?");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1912 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2P2ThreeCycle, SwiftWriteLdFour];
  dag Instrs = (instregex "t2LDRDi8", "LDRD$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1913 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2P2P01ThreeCycle, SwiftWriteLdFour, SwiftWrBackOne];
  dag Instrs = (instregex "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1914 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr2Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy];
  string NAME = ?;
}
def anonymous_1915 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr3Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy];
  string NAME = ?;
}
def anonymous_1916 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr4Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy];
  string NAME = ?;
}
def anonymous_1917 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr5Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy];
  string NAME = ?;
}
def anonymous_1918 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr6Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy];
  string NAME = ?;
}
def anonymous_1919 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr7Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy];
  string NAME = ?;
}
def anonymous_192 {	// AMDGPUArg
  LLVMType Type = anonymous_191;
  string Name = "clamp";
  string NAME = ?;
}
def anonymous_1920 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr8Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10Cy];
  string NAME = ?;
}
def anonymous_1921 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr9Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM11Cy];
  string NAME = ?;
}
def anonymous_1922 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr10Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM11Cy, SwiftWriteLM12Cy];
  string NAME = ?;
}
def anonymous_1923 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr11Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM11Cy, SwiftWriteLM12Cy, SwiftWriteLM13Cy];
  string NAME = ?;
}
def anonymous_1924 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr12Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM11Cy, SwiftWriteLM12Cy, SwiftWriteLM13Cy, SwiftWriteLM14Cy];
  string NAME = ?;
}
def anonymous_1925 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr13Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM11Cy, SwiftWriteLM12Cy, SwiftWriteLM13Cy, SwiftWriteLM14Cy, SwiftWriteLM15Cy];
  string NAME = ?;
}
def anonymous_1926 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr14Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM11Cy, SwiftWriteLM12Cy, SwiftWriteLM13Cy, SwiftWriteLM14Cy, SwiftWriteLM15Cy, SwiftWriteLM16Cy];
  string NAME = ?;
}
def anonymous_1927 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr15Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM11Cy, SwiftWriteLM12Cy, SwiftWriteLM13Cy, SwiftWriteLM14Cy, SwiftWriteLM15Cy, SwiftWriteLM16Cy, SwiftWriteLM17Cy];
  string NAME = ?;
}
def anonymous_1928 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr16Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5Cy, SwiftWriteLM6Cy, SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM11Cy, SwiftWriteLM12Cy, SwiftWriteLM13Cy, SwiftWriteLM14Cy, SwiftWriteLM15Cy, SwiftWriteLM16Cy, SwiftWriteLM17Cy, SwiftWriteLM18Cy];
  string NAME = ?;
}
def anonymous_1929 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [SwiftWriteLM3Cy, SwiftWriteLM4Cy, SwiftWriteLM5CyNo, SwiftWriteLM6CyNo, SwiftWriteLM7CyNo, SwiftWriteLM8CyNo, SwiftWriteLM9CyNo, SwiftWriteLM10CyNo, SwiftWriteLM11CyNo, SwiftWriteLM12CyNo, SwiftWriteLM13CyNo, SwiftWriteLM14CyNo, SwiftWriteLM15CyNo, SwiftWriteLM16CyNo, SwiftWriteLM17CyNo, SwiftWriteLM18CyNo];
  string NAME = ?;
}
def anonymous_193 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_1930 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM, SwiftWriteLDMAddrNoWB];
  dag Instrs = (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$", "(t|sys)LDM(IA|DA|DB|IB)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1931 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLDMAddrWB, SwiftWriteLM];
  dag Instrs = (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1932 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle];
  dag Instrs = (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1933 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2];
  dag Instrs = (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX", "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1934 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWriteP2];
  dag Instrs = (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)", "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)", "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)", "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1935 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2, SwiftWriteP2, SwiftWriteP01OneCycle];
  dag Instrs = (instregex "STRD$", "t2STRDi8");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1936 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWriteP2, SwiftWriteP2, SwiftWriteP01OneCycle];
  dag Instrs = (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1937 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr2Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM2];
  string NAME = ?;
}
def anonymous_1938 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr3Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM3];
  string NAME = ?;
}
def anonymous_1939 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr4Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM4];
  string NAME = ?;
}
def anonymous_194 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_192];
  string NAME = ?;
}
def anonymous_1940 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr5Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM5];
  string NAME = ?;
}
def anonymous_1941 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr6Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM6];
  string NAME = ?;
}
def anonymous_1942 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr7Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM7];
  string NAME = ?;
}
def anonymous_1943 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr8Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM8];
  string NAME = ?;
}
def anonymous_1944 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr9Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM9];
  string NAME = ?;
}
def anonymous_1945 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr10Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM10];
  string NAME = ?;
}
def anonymous_1946 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr11Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM11];
  string NAME = ?;
}
def anonymous_1947 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr12Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM12];
  string NAME = ?;
}
def anonymous_1948 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr13Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM13];
  string NAME = ?;
}
def anonymous_1949 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr14Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM14];
  string NAME = ?;
}
def anonymous_195 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_1950 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr15Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM15];
  string NAME = ?;
}
def anonymous_1951 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr16Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM16];
  string NAME = ?;
}
def anonymous_1952 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM2];
  string NAME = ?;
}
def anonymous_1953 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteSTM];
  dag Instrs = (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1954 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWriteSTM];
  dag Instrs = (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", "tPUSH");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1955 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2ThreeCycle, WriteALU];
  dag Instrs = (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1956 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2ThreeCycle, SwiftWriteP2ThreeCycle];
  dag Instrs = (instregex "LDRLIT_ga_pcrel_ldr");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1957 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteBr;
  string NAME = ?;
}
def anonymous_1958 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1];
  list<int> ResourceCycles = [];
  int Latency = 2;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteBrL;
  string NAME = ?;
}
def anonymous_1959 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP1, SwiftUnitP2];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteBrTbl;
  string NAME = ?;
}
def anonymous_196 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_192];
  string NAME = ?;
}
def anonymous_1960 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteNoop;
  string NAME = ?;
}
def anonymous_1961 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteNoop];
  dag Instrs = (instregex "t2IT", "IT");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1962 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0TwoCycle];
  dag Instrs = (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL", "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi", "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST", "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF", "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1963 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1TwoCycle];
  dag Instrs = (instregex "VEXT", "VREV16", "VREV32", "VREV64");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1964 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0FourCycle];
  dag Instrs = (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL", "VQRSHL", "VRSHR(u|s)", "VABS(f|v)", "VQABS", "VQNEG", "VQADD", "VQSUB");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1965 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1FourCycle];
  dag Instrs = (instregex "VRECPE", "VRSQRTE");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1966 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0P1FourCycle];
  dag Instrs = (instregex "VADDHN", "VSUBHN", "VSHRN");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1967 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0P1SixCycle];
  dag Instrs = (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN", "VQRSHRN", "VQRSHRUN");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1968 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite1xP1TwoCycle];
  dag Instrs = (instregex "VTB(L|X)1");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1969 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite2xP1TwoCycle];
  dag Instrs = (instregex "VTB(L|X)2");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_197 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_1970 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite3xP1TwoCycle];
  dag Instrs = (instregex "VTB(L|X)3");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1971 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite4xP1TwoCycle];
  dag Instrs = (instregex "VTB(L|X)4");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1972 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1FourCycle, SwiftWriteP1FourCycle, SwiftWriteP1TwoCycle, anonymous_1854];
  dag Instrs = (instregex "VSWP", "VTRN", "VUZP", "VZIP");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1973 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0TwoCycle];
  dag Instrs = (instregex "VABS(S|D)$", "VNEG(S|D)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1974 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0FourCycle];
  dag Instrs = (instregex "VCMP(D|S|ZD|ZS)$", "VCMPE(D|S|ZD|ZS)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1975 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0FourCycle];
  dag Instrs = (instregex "VADD(S|f)", "VSUB(S|f)", "VABD", "VPADDf", "VMAX", "VMIN", "VPMAX", "VPMIN");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1976 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0SixCycle];
  dag Instrs = (instregex "VADDD$", "VSUBD$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1977 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1EightCycle];
  dag Instrs = (instregex "VRECPS", "VRSQRTS");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1978 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1FourCycle];
  dag Instrs = (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH", "VMULL", "VQDMULL");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1979 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1FourCycle];
  dag Instrs = (instregex "VMLA", "VMLS", "VNMLA", "VNMLS", "VFMA(S|D)", "VFMS(S|D)", "VFNMA", "VFNMS", "VMLAL", "VMLSL", "VQDMLAL", "VQDMLSL");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_198 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_192];
  string NAME = ?;
}
def anonymous_1980 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1EightCycle];
  dag Instrs = (instregex "VFMAfd", "VFMSfd");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1981 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1TwelveCyc];
  dag Instrs = (instregex "VFMAfq", "VFMSfq");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1982 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1FourCycle];
  dag Instrs = (instregex "VCVT", "V(S|U)IT", "VTO(S|U)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1983 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0TwoCycle];
  dag Instrs = (instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc", "VMVNv", "VMVN(d|q)", "FCONST(D|S)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1984 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1TwoCycle];
  dag Instrs = (instregex "VMOVN", "VMOVL");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1985 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [anonymous_1986];
  dag Instrs = (instregex "VQMOVN");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1986 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle];
  int Repeat = 1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_1987 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP1TwoCycle];
  dag Instrs = (instregex "VDUPLN");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1988 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [anonymous_1989];
  dag Instrs = (instregex "VDUP(8|16|32)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1989 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle];
  int Repeat = 1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_199 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_205];
  string NAME = ?;
}
def anonymous_1990 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2ThreeCycle];
  dag Instrs = (instregex "VMOVRS$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1991 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [anonymous_1992];
  dag Instrs = (instregex "VMOVSR$", "VSETLN");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1992 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle];
  int Repeat = 1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_1993 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2ThreeCycle, SwiftWriteP2FourCycle];
  dag Instrs = (instregex "VMOVRR(D|S)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1994 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP2FourCycle];
  dag Instrs = (instregex "VMOVDRR$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1995 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [anonymous_1989, anonymous_1996];
  dag Instrs = (instregex "VMOVSRR$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1996 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWrite1Cycle, SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle];
  int Repeat = 1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_1997 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [anonymous_1998];
  dag Instrs = (instregex "VGETLN(u|i)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_1998 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle];
  int Repeat = 1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_1999 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [anonymous_2000];
  dag Instrs = (instregex "VGETLNs");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2 {	// IntrinsicProperty ReadOnly
  int ArgNo = 0;
  string NAME = ?;
}
def anonymous_20 {	// LLVMType LLVMMatchType LLVMHalfElementsVectorType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = 0;
  string NAME = ?;
}
def anonymous_200 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "lod";
  string NAME = ?;
}
def anonymous_2000 {	// SchedReadWrite SchedWrite WriteSequence
  list<SchedWrite> Writes = [SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle, SwiftWriteP01OneCycle];
  int Repeat = 1;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_2001 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy];
  dag Instrs = (instregex "VMRS");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2002 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy];
  dag Instrs = (instregex "VMSR");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2003 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP0TwoCycle];
  dag Instrs = (instregex "FMSTAT");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2004 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM4Cy];
  dag Instrs = (instregex "VLDRD$", "VLDRS$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2005 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM4Cy];
  dag Instrs = (instregex "VSTRD$", "VSTRS$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2006 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM4Cy];
  dag Instrs = (instregex "VLDMQIA$", "VSTMQIA$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2007 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr1Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM4Cy];
  string NAME = ?;
}
def anonymous_2008 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr2Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM4Cy, SwiftWriteLM4CyNo];
  string NAME = ?;
}
def anonymous_2009 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr3Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM13CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm3];
  string NAME = ?;
}
def anonymous_201 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_203];
  string NAME = ?;
}
def anonymous_2010 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr4Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM4Cy, SwiftWriteLM4CyNo, SwiftWriteLM4CyNo, SwiftWriteLM4CyNo];
  string NAME = ?;
}
def anonymous_2011 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr5Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM13CyNo, SwiftWriteLM14CyNo, SwiftWriteLM17CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm5];
  string NAME = ?;
}
def anonymous_2012 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr6Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM10Cy, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm5];
  string NAME = ?;
}
def anonymous_2013 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr7Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM13Cy, SwiftWriteLM14CyNo, SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, SwiftWriteLM21CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm7];
  string NAME = ?;
}
def anonymous_2014 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr8Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM13Cy, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm2];
  string NAME = ?;
}
def anonymous_2015 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr9Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM13Cy, SwiftWriteLM14CyNo, SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm9];
  string NAME = ?;
}
def anonymous_2016 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr10Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM10Cy, SwiftWriteLM14Cy, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm5];
  string NAME = ?;
}
def anonymous_2017 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr11Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM13Cy, SwiftWriteLM14CyNo, SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm9];
  string NAME = ?;
}
def anonymous_2018 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr12Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm3];
  string NAME = ?;
}
def anonymous_2019 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr13Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM13Cy, SwiftWriteLM14CyNo, SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm9];
  string NAME = ?;
}
def anonymous_202 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_203];
  string NAME = ?;
}
def anonymous_2020 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr14Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM10Cy, SwiftWriteLM14Cy, SwiftWriteLM14Cy, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm7];
  string NAME = ?;
}
def anonymous_2021 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr15Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM13Cy, SwiftWriteLM14Cy, SwiftWriteLM17Cy, SwiftWriteLM18CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm9];
  string NAME = ?;
}
def anonymous_2022 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr16Pred;
  list<SchedReadWrite> Selected = [SwiftWriteLM7Cy, SwiftWriteLM10Cy, SwiftWriteLM11Cy, SwiftWriteLM14Cy, SwiftWriteLM15Cy, SwiftWriteLM18CyNo, SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm4];
  string NAME = ?;
}
def anonymous_2023 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM13Cy, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm2];
  string NAME = ?;
}
def anonymous_2024 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteVLDM];
  dag Instrs = (instregex "VLDM[SD](IA|DB)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2025 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle2x, SwiftWriteVLDM];
  dag Instrs = (instregex "VLDM[SD](IA|DB)_UPD$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2026 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr1Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM1];
  string NAME = ?;
}
def anonymous_2027 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr2Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM1];
  string NAME = ?;
}
def anonymous_2028 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr3Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM4];
  string NAME = ?;
}
def anonymous_2029 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr4Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM1];
  string NAME = ?;
}
def anonymous_203 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "lod";
  string NAME = ?;
}
def anonymous_2030 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr5Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM6];
  string NAME = ?;
}
def anonymous_2031 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr6Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM4];
  string NAME = ?;
}
def anonymous_2032 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr7Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM8];
  string NAME = ?;
}
def anonymous_2033 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr8Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM3];
  string NAME = ?;
}
def anonymous_2034 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr9Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM10];
  string NAME = ?;
}
def anonymous_2035 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr10Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM6];
  string NAME = ?;
}
def anonymous_2036 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr11Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM12];
  string NAME = ?;
}
def anonymous_2037 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr12Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM4];
  string NAME = ?;
}
def anonymous_2038 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr13Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM14];
  string NAME = ?;
}
def anonymous_2039 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr14Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM8];
  string NAME = ?;
}
def anonymous_204 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "lod";
  string NAME = ?;
}
def anonymous_2040 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr15Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM16];
  string NAME = ?;
}
def anonymous_2041 {	// SchedVar
  SchedPredicate Predicate = SwiftLMAddr16Pred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM5];
  string NAME = ?;
}
def anonymous_2042 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [SwiftWriteSTM3];
  string NAME = ?;
}
def anonymous_2043 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteVSTM];
  dag Instrs = (instregex "VSTM[SD](IA|DB)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2044 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle2x, SwiftWriteVSTM];
  dag Instrs = (instregex "VSTM[SD](IA|DB)_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2045 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM4Cy];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2046 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM4Cy, SwiftWriteP01OneCycle];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)wb");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2047 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite3xP2FourCy];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)T$", "VLD1d64TPseudo");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2048 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite3xP2FourCy, SwiftWriteP01OneCycle];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)Twb");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2049 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite2xP2FourCy];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)Q$", "VLD1d64QPseudo");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_205 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "lod";
  string NAME = ?;
}
def anonymous_2050 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite2xP2FourCy, SwiftWriteP01OneCycle];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)Qwb");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2051 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM9Cy, SwiftExt2xP0, SwiftVLDMPerm2];
  dag Instrs = (instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2052 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftExt2xP0, SwiftVLDMPerm2];
  dag Instrs = (instregex "VLD2(d|q|b)(8|16|32)wb", "VLD2q(8|16|32)PseudoWB");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2053 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo, SwiftVLDMPerm3, SwiftWrite3xP2FourCy];
  dag Instrs = (instregex "VLD3(d|q)(8|16|32)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2054 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM9Cy, SwiftVLDMPerm3, SwiftWrite3xP2FourCy];
  dag Instrs = (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2055 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm3, SwiftWrite3xP2FourCy];
  dag Instrs = (instregex "VLD3(d|q)(8|16|32)_UPD$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2056 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm3, SwiftWrite3xP2FourCy];
  dag Instrs = (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2057 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4, SwiftWrite3xP2FourCy];
  dag Instrs = (instregex "VLD4(d|q)(8|16|32)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2058 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4, SwiftWrite3xP2FourCy];
  dag Instrs = (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2059 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0, SwiftVLDMPerm4, SwiftWrite3xP2FourCy];
  dag Instrs = (instregex "VLD4(d|q)(8|16|32)_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_206 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_205];
  string NAME = ?;
}
def anonymous_2060 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0, SwiftVLDMPerm4, SwiftWrite3xP2FourCy];
  dag Instrs = (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2061 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM6Cy, SwiftVLDMPerm2];
  dag Instrs = (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2062 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm2];
  dag Instrs = (instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)", "VLD1LNq(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2063 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftExt1xP0, SwiftVLDMPerm2];
  dag Instrs = (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$", "VLD2LN(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2064 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftExt1xP0, SwiftVLDMPerm2];
  dag Instrs = (instregex "VLD2LN(d|q)(8|16|32)_UPD$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2065 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy, SwiftExt1xP0, SwiftVLDMPerm2];
  dag Instrs = (instregex "VLD2DUPd(8|16|32|8x2|16x2|32x2)wb");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2066 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy, SwiftExt1xP0, SwiftVLDMPerm2];
  dag Instrs = (instregex "VLD2LN(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2067 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, SwiftExt1xP0, SwiftVLDMPerm3];
  dag Instrs = (instregex "VLD3(DUP|LN)(d|q)(8|16|32)$", "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2068 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, SwiftWriteP01OneCycle, SwiftExt1xP0, SwiftVLDMPerm3];
  dag Instrs = (instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2069 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM7Cy, SwiftWriteP01OneCycle, SwiftWriteLM8Cy, SwiftWriteLM8Cy, SwiftExt1xP0, SwiftVLDMPerm3];
  dag Instrs = (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_207 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_203];
  string NAME = ?;
}
def anonymous_2070 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo, SwiftWriteLM10CyNo, SwiftExt1xP0, SwiftVLDMPerm5];
  dag Instrs = (instregex "VLD4(LN|DUP)(d|q)(8|16|32)$", "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2071 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo, SwiftWriteLM10CyNo, SwiftWriteP01OneCycle, SwiftExt1xP0, SwiftVLDMPerm5];
  dag Instrs = (instregex "VLD4(DUP|LN)(d|q)(8|16|32)_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2072 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteLM8Cy, SwiftWriteP01OneCycle, SwiftWriteLM9Cy, SwiftWriteLM10CyNo, SwiftWriteLM10CyNo, SwiftExt1xP0, SwiftVLDMPerm5];
  dag Instrs = (instregex "VLD4(DUP|LN)(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2073 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite1xP2];
  dag Instrs = (instregex "VST1d(8|16|32|64)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2074 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite2xP2];
  dag Instrs = (instregex "VST1q(8|16|32|64)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2075 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite1xP2];
  dag Instrs = (instregex "VST1d(8|16|32|64)wb");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2076 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite2xP2];
  dag Instrs = (instregex "VST1q(8|16|32|64)wb");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2077 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite3xP2];
  dag Instrs = (instregex "VST1d(8|16|32|64)T$", "VST1d64TPseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2078 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite3xP2];
  dag Instrs = (instregex "VST1d(8|16|32|64)Twb", "VST1d64TPseudoWB");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2079 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite4xP2];
  dag Instrs = (instregex "VST1d(8|16|32|64)(Q|QPseudo)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_208 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_205];
  string NAME = ?;
}
def anonymous_2080 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite4xP2];
  dag Instrs = (instregex "VST1d(8|16|32|64)(Qwb|QPseudoWB)");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2081 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite1xP2, SwiftVLDMPerm1];
  dag Instrs = (instregex "VST2(d|b)(8|16|32)$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2082 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1];
  dag Instrs = (instregex "VST2(b|d)(8|16|32)wb");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2083 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite2xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2084 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite2xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST2q(8|16|32)wb", "VST2q(8|16|32)PseudoWB");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2085 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite4xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST3(d|q)(8|16|32)$", "VST3(d|q)(8|16|32)(oddP|P)seudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2086 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST3(d|q)(8|16|32)_UPD", "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2087 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite4xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST4(d|q)(8|16|32)$", "VST4(d|q)(8|16|32)(oddP|P)seudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2088 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm4];
  dag Instrs = (instregex "VST4(d|q)(8|16|32)_UPD", "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2089 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite1xP2, SwiftVLDMPerm1];
  dag Instrs = (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_209 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_203];
  string NAME = ?;
}
def anonymous_2090 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1];
  dag Instrs = (instregex "VST1LNd(8|16|32)_UPD", "VST1LNq(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2091 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite1xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2092 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST2LN(d|q)(8|16|32)_UPD", "VST2LN(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2093 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite4xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2094 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST3LN(d|q)(8|16|32)_UPD", "VST3LN(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2095 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWrite2xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST4LN(d|q)(8|16|32)$", "VST4LN(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2096 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle, SwiftWrite2xP2, SwiftVLDMPerm2];
  dag Instrs = (instregex "VST4LN(d|q)(8|16|32)_UPD", "VST4LN(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2097 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftDiv17];
  dag Instrs = (instregex "VDIVS", "VSQRTS");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2098 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftDiv32];
  dag Instrs = (instregex "VDIVD", "VSQRTD");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2099 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPCVT;
  SchedReadWrite AliasRW = SwiftWriteP1FourCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_21 {	// IntrinsicProperty NoCapture
  int ArgNo = 3;
  string NAME = ?;
}
def anonymous_210 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_205];
  string NAME = ?;
}
def anonymous_2100 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMOV;
  SchedReadWrite AliasRW = SwiftWriteP2ThreeCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2101 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPALU32;
  SchedReadWrite AliasRW = SwiftWriteP0FourCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2102 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPALU64;
  SchedReadWrite AliasRW = SwiftWriteP0SixCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2103 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMUL32;
  SchedReadWrite AliasRW = SwiftWriteP1FourCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2104 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMUL64;
  SchedReadWrite AliasRW = SwiftWriteP1SixCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2105 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMAC32;
  SchedReadWrite AliasRW = SwiftWriteP1FourCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2106 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMAC64;
  SchedReadWrite AliasRW = SwiftWriteP1FourCycle;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2107 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPDIV32;
  SchedReadWrite AliasRW = SwiftDiv17;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2108 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPSQRT32;
  SchedReadWrite AliasRW = SwiftDiv17;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2109 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPDIV64;
  SchedReadWrite AliasRW = SwiftDiv32;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_211 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_203];
  string NAME = ?;
}
def anonymous_2110 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPSQRT64;
  SchedReadWrite AliasRW = SwiftDiv32;
  SchedMachineModel SchedModel = SwiftModel;
  string NAME = ?;
}
def anonymous_2111 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedRead ReadType = ReadFPMUL;
  string NAME = ?;
}
def anonymous_2112 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedRead ReadType = ReadFPMAC;
  string NAME = ?;
}
def anonymous_2113 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteVLD1;
  string NAME = ?;
}
def anonymous_2114 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteVLD2;
  string NAME = ?;
}
def anonymous_2115 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteVLD3;
  string NAME = ?;
}
def anonymous_2116 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteVLD4;
  string NAME = ?;
}
def anonymous_2117 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteVST1;
  string NAME = ?;
}
def anonymous_2118 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteVST2;
  string NAME = ?;
}
def anonymous_2119 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteVST3;
  string NAME = ?;
}
def anonymous_212 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_149];
  string NAME = ?;
}
def anonymous_2120 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WriteVST4;
  string NAME = ?;
}
def anonymous_2121 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [SwiftWriteP01OneCycle2x];
  dag Instrs = (instregex "ABS");
  SchedMachineModel SchedModel = SwiftModel;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2122 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [SwiftUnitP2];
  list<int> ResourceCycles = [0];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = SwiftModel;
  SchedWrite WriteType = WritePreLd;
  string NAME = ?;
}
def anonymous_2123 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteALU;
  string NAME = ?;
}
def anonymous_2124 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteALUsi;
  string NAME = ?;
}
def anonymous_2125 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteALUsr;
  string NAME = ?;
}
def anonymous_2126 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 3;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteALUSsr;
  string NAME = ?;
}
def anonymous_2127 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteCMP;
  string NAME = ?;
}
def anonymous_2128 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteCMPsi;
  string NAME = ?;
}
def anonymous_2129 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteCMPsr;
  string NAME = ?;
}
def anonymous_213 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149];
  string NAME = ?;
}
def anonymous_2130 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitDiv];
  list<int> ResourceCycles = [8];
  int Latency = 8;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteDIV;
  string NAME = ?;
}
def anonymous_2131 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitB];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteBr;
  string NAME = ?;
}
def anonymous_2132 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitB];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteBrL;
  string NAME = ?;
}
def anonymous_2133 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitALU];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteBrTbl;
  string NAME = ?;
}
def anonymous_2134 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteNoop;
  string NAME = ?;
}
def anonymous_2135 {	// ProcReadAdvance ReadAdvance
  int Cycles = 1;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = ReadALU;
  string NAME = ?;
}
def anonymous_2136 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = ReadALUsr;
  string NAME = ?;
}
def anonymous_2137 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = ReadMUL;
  string NAME = ?;
}
def anonymous_2138 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = ReadMAC;
  string NAME = ?;
}
def anonymous_2139 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPMUL];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteFPMUL32;
  string NAME = ?;
}
def anonymous_214 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149];
  string NAME = ?;
}
def anonymous_2140 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPMUL, R52UnitFPMUL];
  list<int> ResourceCycles = [];
  int Latency = 6;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteFPMUL64;
  string NAME = ?;
}
def anonymous_2141 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPMUL, R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteFPMAC32;
  string NAME = ?;
}
def anonymous_2142 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitFPMUL, R52UnitFPMUL, R52UnitFPALU, R52UnitFPALU];
  list<int> ResourceCycles = [];
  int Latency = 11;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteFPMAC64;
  string NAME = ?;
}
def anonymous_2143 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitDiv];
  list<int> ResourceCycles = [7];
  int Latency = 7;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteFPDIV32;
  string NAME = ?;
}
def anonymous_2144 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitDiv];
  list<int> ResourceCycles = [17];
  int Latency = 17;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteFPDIV64;
  string NAME = ?;
}
def anonymous_2145 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitDiv];
  list<int> ResourceCycles = [];
  int Latency = 7;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteFPSQRT32;
  string NAME = ?;
}
def anonymous_2146 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitDiv];
  list<int> ResourceCycles = [];
  int Latency = 17;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteFPSQRT64;
  string NAME = ?;
}
def anonymous_2147 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteVST1;
  string NAME = ?;
}
def anonymous_2148 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteVST2;
  string NAME = ?;
}
def anonymous_2149 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteVST3;
  string NAME = ?;
}
def anonymous_215 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149];
  string NAME = ?;
}
def anonymous_2150 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteVST4;
  string NAME = ?;
}
def anonymous_2151 {	// ProcReadAdvance ReadAdvance
  int Cycles = 1;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = ReadFPMUL;
  string NAME = ?;
}
def anonymous_2152 {	// ProcReadAdvance ReadAdvance
  int Cycles = 1;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = ReadFPMAC;
  string NAME = ?;
}
def anonymous_2153 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = R52Read_ISS;
  string NAME = ?;
}
def anonymous_2154 {	// ProcReadAdvance ReadAdvance
  int Cycles = 1;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = R52Read_EX1;
  string NAME = ?;
}
def anonymous_2155 {	// ProcReadAdvance ReadAdvance
  int Cycles = 2;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = R52Read_EX2;
  string NAME = ?;
}
def anonymous_2156 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = R52Read_F0;
  string NAME = ?;
}
def anonymous_2157 {	// ProcReadAdvance ReadAdvance
  int Cycles = 1;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = R52Read_F1;
  string NAME = ?;
}
def anonymous_2158 {	// ProcReadAdvance ReadAdvance
  int Cycles = 2;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedRead ReadType = R52Read_F2;
  string NAME = ?;
}
def anonymous_2159 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL16;
  SchedReadWrite AliasRW = R52WriteMAC;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_216 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_219, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_221, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_223, anonymous_149];
  string NAME = ?;
}
def anonymous_2160 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL32;
  SchedReadWrite AliasRW = R52WriteMAC;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2161 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL64Lo;
  SchedReadWrite AliasRW = R52WriteMAC;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2162 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL64Hi;
  SchedReadWrite AliasRW = R52WriteMACHi;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2163 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC16;
  SchedReadWrite AliasRW = R52WriteMAC;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2164 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC32;
  SchedReadWrite AliasRW = R52WriteMAC;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2165 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC64Lo;
  SchedReadWrite AliasRW = R52WriteMAC;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2166 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC64Hi;
  SchedReadWrite AliasRW = R52WriteMACHi;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2167 {	// SchedAlias
  SchedReadWrite MatchRW = WritePreLd;
  SchedReadWrite AliasRW = R52WriteLd;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2168 {	// SchedAlias
  SchedReadWrite MatchRW = WriteLd;
  SchedReadWrite AliasRW = R52WriteLd;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2169 {	// SchedAlias
  SchedReadWrite MatchRW = WriteST;
  SchedReadWrite AliasRW = R52WriteST;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_217 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_219, anonymous_31];
  string NAME = ?;
}
def anonymous_2170 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPCVT;
  SchedReadWrite AliasRW = R52WriteFPALU_F5;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2171 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMOV;
  SchedReadWrite AliasRW = R52WriteFPALU_F3;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2172 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPALU32;
  SchedReadWrite AliasRW = R52WriteFPALU_F5;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2173 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPALU64;
  SchedReadWrite AliasRW = R52WriteFPALU_F5;
  SchedMachineModel SchedModel = CortexR52Model;
  string NAME = ?;
}
def anonymous_2174 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteALU];
  dag Instrs = (instrs COPY);
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2175 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1, R52Read_ISS];
  dag Instrs = (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16", "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", "t2UXTB16");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2176 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX1, R52Read_ISS];
  dag Instrs = (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi", "t2MOVi");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2177 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1];
  dag Instrs = (instregex "MOV_ga_pcrel$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2178 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd, R52Read_ISS];
  dag Instrs = (instregex "MOV_ga_pcrel_ldr");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2179 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1];
  dag Instrs = (instregex "SEL", "t2SEL");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_218 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_35, anonymous_219];
  string NAME = ?;
}
def anonymous_2180 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI", "(t|t2)UBFX", "(t|t2)SBFX");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2181 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_WRI, R52Read_EX1, R52Read_EX1];
  dag Instrs = (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT", "QADD8", "QADD16", "QSUB8", "QSUB16", "QASX", "QSAX", "UQADD8", "UQADD16", "UQSUB8", "UQSUB16", "UQASX", "UQSAX", "t2QADD", "t2QSUB", "t2QDADD", "t2QDSUB", "t2SSAT", "t2SSAT16", "t2USAT", "t2QADD8", "t2QADD16", "t2QSUB8", "t2QSUB16", "t2QASX", "t2QSAX", "t2UQADD8", "t2UQADD16", "t2UQSUB8", "t2UQSUB16", "t2UQASX", "t2UQSAX", "t2ABS");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2182 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1];
  dag Instrs = (instregex "SADD8", "SADD16", "SSUB8", "SSUB16", "SASX", "SSAX", "UADD8", "UADD16", "USUB8", "USUB16", "UASX", "USAX", "t2SADD8", "t2SADD16", "t2SSUB8", "t2SSUB16", "t2SASX", "t2SSAX", "t2UADD8", "t2UADD16", "t2USUB8", "t2USUB16", "t2UASX", "t2USAX");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2183 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1];
  dag Instrs = (instregex "SHADD8", "SHADD16", "SHSUB8", "SHSUB16", "SHASX", "SHSAX", "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16", "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16", "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16", "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX", "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2184 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_WRI, R52Read_ISS, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "USAD8", "t2USAD8", "USADA8", "t2USADA8");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2185 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteMAC, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDX", "t2MUL", "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT", "t2SMULWB", "t2SMULWT", "t2SMUSD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2186 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteMAC, R52Read_ISS, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", "t2MLA", "t2MLS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", "t2SMMLSR", "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX", "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX", "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT", "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT", "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX", "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$", "SMLAL", "UMLAL", "SMLALBT", "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX", "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBT", "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX", "t2UMAAL");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2187 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteDIV, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "t2SDIV", "t2UDIV");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2188 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)", "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "t2LDREX", "tLDR[BH](r|i|spi|pci|pciASM)", "tLDR(r|i|spi|pci|pciASM)", "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$", "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$", "t2LDRpci_pic", "tLDRS(B|H)", "t2LDRDi8", "LDRD$", "LDA", "t2LDA");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2189 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)", "LDRBT_POST$", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)", "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T", "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)", "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)?", "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_219 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "dsdv";
  string NAME = ?;
}
def anonymous_2190 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1];
  dag Instrs = (instregex "MOVS?sr", "t2MOVS?sr");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2191 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_WRI, R52Read_EX2];
  dag Instrs = (instregex "MOVT", "t2MOVT");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2192 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1];
  dag Instrs = (instregex "AD(C|D)S?ri", "ANDS?ri", "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri", "t2AD(C|D)S?ri", "t2ANDS?ri", "t2BICS?ri", "t2CLZ", "t2EORri", "t2MVN", "t2ORRri", "t2RSBS?ri", "t2SBCri");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2193 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1];
  dag Instrs = (instregex "AD(C|D)S?rr", "ANDS?rr", "BICS?rr", "CRC", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr", "t2AD(C|D)S?rr", "t2ANDS?rr", "t2BICS?rr", "t2CRC", "t2EORrr", "t2SBCrr");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2194 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1, R52Read_ISS];
  dag Instrs = (instregex "AD(C|D)S?rsi", "ANDS?rsi", "BICS?rsi", "EORrsi", "ORRrsi", "RSBrsi", "RSCrsi", "SBCrsi", "t2AD(C|D)S?rs", "t2ANDS?rs", "t2BICS?rs", "t2EORrs", "t2ORRrs", "t2RSBrs", "t2SBCrs");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2195 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_EX1, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr", "ORRrsr", "RSBrsr", "RSCrsr", "SBCrsr");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2196 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX1];
  dag Instrs = (instregex "ADR", "MOVsi", "MVNS?s?i", "t2MOVS?si");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2197 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX1, R52Read_ISS];
  dag Instrs = (instregex "ASRi", "RORS?i");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2198 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX1, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "ASRr", "RORS?r", "LSR", "LSL");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2199 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteCC, R52Read_EX1];
  dag Instrs = (instregex "CMPri", "CMNri");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_22 {	// IntrinsicProperty NoCapture
  int ArgNo = 4;
  string NAME = ?;
}
def anonymous_220 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "dsdh";
  string NAME = ?;
}
def anonymous_2200 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteCC, R52Read_EX1, R52Read_EX1];
  dag Instrs = (instregex "CMPrr", "CMNzrr");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2201 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteCC, R52Read_EX1, R52Read_ISS];
  dag Instrs = (instregex "CMPrsi", "CMNzrsi");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2202 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteCC, R52Read_EX1, R52Read_ISS, R52Read_ISS];
  dag Instrs = (instregex "CMPrsr", "CMNzrsr");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2203 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteALU_EX2, R52Read_ISS];
  dag Instrs = (instregex "t2LDC", "RBIT", "REV", "REV16", "REVSH", "RRX");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2204 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteCC, R52Read_ISS];
  dag Instrs = (instregex "TST");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2205 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd];
  dag Instrs = (instregex "MRS", "MRSbanked");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2206 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd, R52Read_EX1];
  dag Instrs = (instregex "MSR", "MSRbanked");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2207 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr2Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy];
  string NAME = ?;
}
def anonymous_2208 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr3Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy];
  string NAME = ?;
}
def anonymous_2209 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr4Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy];
  string NAME = ?;
}
def anonymous_221 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "dsdv";
  string NAME = ?;
}
def anonymous_2210 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr5Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy];
  string NAME = ?;
}
def anonymous_2211 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr6Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy];
  string NAME = ?;
}
def anonymous_2212 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr7Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy];
  string NAME = ?;
}
def anonymous_2213 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr8Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy, R52WriteILDM11Cy];
  string NAME = ?;
}
def anonymous_2214 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr9Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy, R52WriteILDM11Cy, R52WriteILDM12Cy];
  string NAME = ?;
}
def anonymous_2215 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr10Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy, R52WriteILDM11Cy, R52WriteILDM12Cy, R52WriteILDM13Cy];
  string NAME = ?;
}
def anonymous_2216 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr11Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy, R52WriteILDM11Cy, R52WriteILDM12Cy, R52WriteILDM13Cy, R52WriteILDM14Cy];
  string NAME = ?;
}
def anonymous_2217 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr12Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy, R52WriteILDM11Cy, R52WriteILDM12Cy, R52WriteILDM13Cy, R52WriteILDM14Cy, R52WriteILDM15Cy];
  string NAME = ?;
}
def anonymous_2218 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr13Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy, R52WriteILDM11Cy, R52WriteILDM12Cy, R52WriteILDM13Cy, R52WriteILDM14Cy, R52WriteILDM15Cy, R52WriteILDM16Cy];
  string NAME = ?;
}
def anonymous_2219 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr14Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy, R52WriteILDM11Cy, R52WriteILDM12Cy, R52WriteILDM13Cy, R52WriteILDM14Cy, R52WriteILDM15Cy, R52WriteILDM16Cy, R52WriteILDM17Cy];
  string NAME = ?;
}
def anonymous_222 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "dsdh";
  string NAME = ?;
}
def anonymous_2220 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr15Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy, R52WriteILDM11Cy, R52WriteILDM12Cy, R52WriteILDM13Cy, R52WriteILDM14Cy, R52WriteILDM15Cy, R52WriteILDM16Cy, R52WriteILDM17Cy, R52WriteILDM18Cy];
  string NAME = ?;
}
def anonymous_2221 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr15Pred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6Cy, R52WriteILDM7Cy, R52WriteILDM8Cy, R52WriteILDM9Cy, R52WriteILDM10Cy, R52WriteILDM11Cy, R52WriteILDM12Cy, R52WriteILDM13Cy, R52WriteILDM14Cy, R52WriteILDM15Cy, R52WriteILDM16Cy, R52WriteILDM17Cy, R52WriteILDM18Cy, R52WriteILDM19Cy];
  string NAME = ?;
}
def anonymous_2222 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [R52WriteILDM4Cy, R52WriteILDM5Cy, R52WriteILDM6CyNo, R52WriteILDM7CyNo, R52WriteILDM8CyNo, R52WriteILDM9CyNo, R52WriteILDM10CyNo, R52WriteILDM11CyNo, R52WriteILDM12CyNo, R52WriteILDM13CyNo, R52WriteILDM14CyNo, R52WriteILDM15CyNo, R52WriteILDM16CyNo, R52WriteILDM17CyNo, R52WriteILDM18Cy, R52WriteILDM19Cy];
  string NAME = ?;
}
def anonymous_2223 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr2Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM2];
  string NAME = ?;
}
def anonymous_2224 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr3Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM3];
  string NAME = ?;
}
def anonymous_2225 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr4Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM4];
  string NAME = ?;
}
def anonymous_2226 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr5Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM5];
  string NAME = ?;
}
def anonymous_2227 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr6Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM6];
  string NAME = ?;
}
def anonymous_2228 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr7Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM7];
  string NAME = ?;
}
def anonymous_2229 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr8Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM8];
  string NAME = ?;
}
def anonymous_223 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "dsdv";
  string NAME = ?;
}
def anonymous_2230 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr9Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM9];
  string NAME = ?;
}
def anonymous_2231 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr10Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM10];
  string NAME = ?;
}
def anonymous_2232 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr11Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM11];
  string NAME = ?;
}
def anonymous_2233 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr12Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM12];
  string NAME = ?;
}
def anonymous_2234 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr13Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM13];
  string NAME = ?;
}
def anonymous_2235 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr14Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM14];
  string NAME = ?;
}
def anonymous_2236 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr15Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM15];
  string NAME = ?;
}
def anonymous_2237 {	// SchedVar
  SchedPredicate Predicate = R52ILDMAddr16Pred;
  list<SchedReadWrite> Selected = [R52WriteISTM16];
  string NAME = ?;
}
def anonymous_2238 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [R52WriteISTM2];
  string NAME = ?;
}
def anonymous_2239 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteILDM, R52Read_ISS];
  dag Instrs = (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$", "(t|sys)LDM(IA|DA|DB|IB)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_224 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_219, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_221, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_223, anonymous_149];
  string NAME = ?;
}
def anonymous_2240 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteILDM, R52WriteAdr, R52Read_ISS];
  dag Instrs = (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2241 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteILDM, R52WriteAdr, R52Read_ISS];
  dag Instrs = (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2242 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd, R52Read_ISS, R52Read_EX2];
  dag Instrs = (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX", "SRS", "t2SRS", "t2SRSDB", "t2STREX", "t2STREXB", "t2STREXD", "t2STREXH", "t2STR(i12|i8|s)$", "RFE", "t2RFE", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2243 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2];
  dag Instrs = (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)", "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)", "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)", "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2244 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd, R52Read_ISS, R52Read_EX2];
  dag Instrs = (instregex "STRD$", "t2STRDi8", "STL", "t2STL");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2245 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2];
  dag Instrs = (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2246 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteISTM, R52Read_ISS, R52Read_EX2];
  dag Instrs = (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2247 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteISTM, R52WriteAdr, R52Read_ISS, R52Read_EX2];
  dag Instrs = (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", "tPUSH");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2248 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd];
  dag Instrs = (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2249 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteLd];
  dag Instrs = (instregex "LDRLIT_ga_pcrel_ldr");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_225 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_219, anonymous_31];
  string NAME = ?;
}
def anonymous_2250 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VABD(fd|hd)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2251 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F5, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VABD(fq|hq)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2252 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F1];
  dag Instrs = (instregex "VABS(D|S|H)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2253 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F1];
  dag Instrs = (instregex "VABS(fd|hd)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2254 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F5, R52Read_F1];
  dag Instrs = (instregex "VABS(fq|hq)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2255 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "(VACGE|VACGT)(fd|hd)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2256 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F3, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "(VACGE|VACGT)(fq|hq)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2257 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "(VADD|VSUB)(D|S|H|fd|hd)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2258 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F5, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "(VADD|VSUB)(fq|hq)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2259 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPLd_F4, R52Read_ISS, R52Read_F1];
  dag Instrs = (instregex "VLDR");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_226 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_219, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_221, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_223, anonymous_149];
  string NAME = ?;
}
def anonymous_2260 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPST_F4, R52Read_ISS, R52Read_F1];
  dag Instrs = (instregex "VSTR");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2261 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred1;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52ReserveLd5Cy];
  string NAME = ?;
}
def anonymous_2262 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred2;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52ReserveLd5Cy];
  string NAME = ?;
}
def anonymous_2263 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred3;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52ReserveLd6Cy];
  string NAME = ?;
}
def anonymous_2264 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred4;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52ReserveLd6Cy];
  string NAME = ?;
}
def anonymous_2265 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred5;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52ReserveLd4Cy];
  string NAME = ?;
}
def anonymous_2266 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred6;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52ReserveLd7Cy];
  string NAME = ?;
}
def anonymous_2267 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred7;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52ReserveLd8Cy];
  string NAME = ?;
}
def anonymous_2268 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred8;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52ReserveLd8Cy];
  string NAME = ?;
}
def anonymous_2269 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred9;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52WriteLM9Cy, R52ReserveLd9Cy];
  string NAME = ?;
}
def anonymous_227 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_219, anonymous_31];
  string NAME = ?;
}
def anonymous_2270 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred10;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52WriteLM9Cy, R52ReserveLd9Cy];
  string NAME = ?;
}
def anonymous_2271 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred11;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52WriteLM9Cy, R52WriteLM10Cy, R52ReserveLd10Cy];
  string NAME = ?;
}
def anonymous_2272 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred12;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52WriteLM9Cy, R52WriteLM10Cy, R52ReserveLd10Cy];
  string NAME = ?;
}
def anonymous_2273 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred13;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52WriteLM9Cy, R52WriteLM10Cy, R52WriteLM11Cy, R52ReserveLd11Cy];
  string NAME = ?;
}
def anonymous_2274 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred14;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52WriteLM9Cy, R52WriteLM10Cy, R52WriteLM11Cy, R52ReserveLd11Cy];
  string NAME = ?;
}
def anonymous_2275 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred14;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52WriteLM9Cy, R52WriteLM10Cy, R52WriteLM11Cy, R52WriteLM12Cy, R52ReserveLd12Cy];
  string NAME = ?;
}
def anonymous_2276 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred15;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52WriteLM9Cy, R52WriteLM10Cy, R52WriteLM11Cy, R52WriteLM12Cy, R52ReserveLd12Cy];
  string NAME = ?;
}
def anonymous_2277 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [R52WriteLM5Cy, R52WriteLM6Cy, R52WriteLM7Cy, R52WriteLM8Cy, R52WriteLM9Cy, R52WriteLM10Cy, R52WriteLM11Cy, R52WriteLM12Cy, R52ReserveLd5Cy];
  string NAME = ?;
}
def anonymous_2278 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred1;
  list<SchedReadWrite> Selected = [R52WriteSTM5];
  string NAME = ?;
}
def anonymous_2279 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred2;
  list<SchedReadWrite> Selected = [R52WriteSTM5];
  string NAME = ?;
}
def anonymous_228 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_221, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_223, anonymous_149];
  string NAME = ?;
}
def anonymous_2280 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred3;
  list<SchedReadWrite> Selected = [R52WriteSTM6];
  string NAME = ?;
}
def anonymous_2281 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred4;
  list<SchedReadWrite> Selected = [R52WriteSTM6];
  string NAME = ?;
}
def anonymous_2282 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred5;
  list<SchedReadWrite> Selected = [R52WriteSTM7];
  string NAME = ?;
}
def anonymous_2283 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred6;
  list<SchedReadWrite> Selected = [R52WriteSTM7];
  string NAME = ?;
}
def anonymous_2284 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred7;
  list<SchedReadWrite> Selected = [R52WriteSTM8];
  string NAME = ?;
}
def anonymous_2285 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred8;
  list<SchedReadWrite> Selected = [R52WriteSTM8];
  string NAME = ?;
}
def anonymous_2286 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred9;
  list<SchedReadWrite> Selected = [R52WriteSTM9];
  string NAME = ?;
}
def anonymous_2287 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred10;
  list<SchedReadWrite> Selected = [R52WriteSTM9];
  string NAME = ?;
}
def anonymous_2288 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred11;
  list<SchedReadWrite> Selected = [R52WriteSTM10];
  string NAME = ?;
}
def anonymous_2289 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred12;
  list<SchedReadWrite> Selected = [R52WriteSTM10];
  string NAME = ?;
}
def anonymous_229 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31];
  string NAME = ?;
}
def anonymous_2290 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred13;
  list<SchedReadWrite> Selected = [R52WriteSTM11];
  string NAME = ?;
}
def anonymous_2291 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred14;
  list<SchedReadWrite> Selected = [R52WriteSTM11];
  string NAME = ?;
}
def anonymous_2292 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred15;
  list<SchedReadWrite> Selected = [R52WriteSTM12];
  string NAME = ?;
}
def anonymous_2293 {	// SchedVar
  SchedPredicate Predicate = R52LMAddrPred16;
  list<SchedReadWrite> Selected = [R52WriteSTM12];
  string NAME = ?;
}
def anonymous_2294 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [R52WriteSTM6];
  string NAME = ?;
}
def anonymous_2295 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [];
  int Latency = 5;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteVLD1;
  string NAME = ?;
}
def anonymous_2296 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [2];
  int Latency = 6;
  int NumMicroOps = 3;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 1;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteVLD2;
  string NAME = ?;
}
def anonymous_2297 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [3];
  int Latency = 7;
  int NumMicroOps = 5;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 1;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteVLD3;
  string NAME = ?;
}
def anonymous_2298 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [R52UnitLd];
  list<int> ResourceCycles = [4];
  int Latency = 8;
  int NumMicroOps = 7;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 1;
  SchedMachineModel SchedModel = CortexR52Model;
  SchedWrite WriteType = WriteVLD4;
  string NAME = ?;
}
def anonymous_2299 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VABA(u|s)(v8i8|v4i16|v2i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_23 {	// IntrinsicProperty NoCapture
  int ArgNo = 5;
  string NAME = ?;
}
def anonymous_230 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_221, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_223, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_2300 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VABA(u|s)(v16i8|v8i16|v4i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2301 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VABAL(u|s)(v8i16|v4i32|v2i64)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2302 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F4, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VABD(u|s)(v8i8|v4i16|v2i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2303 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F4, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VABD(u|s)(v16i8|v8i16|v4i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2304 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F4, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VABDL(u|s)(v16i8|v8i16|v4i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2305 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F4, R52Read_F1];
  dag Instrs = (instregex "VABS(v16i8|v8i16|v4i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2306 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F4, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VADD|VSUB)(v8i8|v4i16|v2i32|v1i64)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2307 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F4, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VADD|VSUB)(v16i8|v8i16|v4i32|v2i64)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2308 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F5, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VADDHN|VRADDHN|VSUBHN|VRSUBHN)(v8i8|v4i16|v2i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2309 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F4, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VADDL", "VADDW", "VSUBL", "VSUBW");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_231 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  string NAME = ?;
}
def anonymous_2310 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VAND|VBIC|VEOR)d");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2311 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F3, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VAND|VBIC|VEOR)q");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2312 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_F2];
  dag Instrs = (instregex "VBICi(v4i16|v2i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2313 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F3, R52Read_F2];
  dag Instrs = (instregex "VBICi(v8i16|v4i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2314 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VBIF|VBIT|VBSL)d");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2315 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VBIF|VBIT|VBSL)q");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2316 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2317 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VCVT", "VSITO", "VUITO", "VTO");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2318 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_ISS];
  dag Instrs = (instregex "VDUP(8|16|32)d");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2319 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F3, R52Read_ISS];
  dag Instrs = (instregex "VDUP(8|16|32)q");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_232 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_221, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_223, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_2320 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_F1];
  dag Instrs = (instregex "VDUPLN(8|16|32)d");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2321 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F3, R52Read_F1];
  dag Instrs = (instregex "VDUPLN(8|16|32)q");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2322 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VEXTd(8|16|32)", "VSEL");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2323 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F3, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VEXTq(8|16|32|64)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2324 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "(VFMA|VFMS)(f|h)d");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2325 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "(VFMA|VFMS)(f|h)q");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2326 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F4, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VHADD|VHSUB)(u|s)(v8i8|v4i16|v2i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2327 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F4, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VHADD|VHSUB)(u|s)(v16i8|v8i16|v4i32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2328 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVLDM];
  dag Instrs = (instregex "VLDM[SD](IA|DB)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2329 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F4, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VMAX", "VMIN", "VPMAX", "VPMIN");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_233 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  string NAME = ?;
}
def anonymous_2330 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VORR", "VORN", "VREV");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2331 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteNoRSRC_WRI];
  dag Instrs = (instregex "VMRS");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2332 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F1];
  dag Instrs = (instregex "VNEG");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2333 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F4, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VPADDi");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2334 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F4, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VPADAL", "VPADDL");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2335 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F1];
  dag Instrs = (instregex "VQABS(v8i8|v4i16|v2i32|v1i64)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2336 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F5, R52Read_F1];
  dag Instrs = (instregex "VQABS(v16i8|v8i16|v4i32|v2i64)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2337 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VQADD|VQSUB)(u|s)(v8i8|v4i16|v2i32|v1i64)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2338 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPALU_F5, R52Read_F2, R52Read_F2];
  dag Instrs = (instregex "(VQADD|VQSUB)(u|s)(v16i8|v8i16|v4i32|v2i64)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2339 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52Write2FPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VQDMLAL", "VQDMLSL");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_234 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_2340 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPMUL_F5, R52Read_F1, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VQDMUL", "VQRDMUL");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2341 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F5, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VQMOVN", "VQNEG", "VQSHL", "VQSHRN");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2342 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F4, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VRSHL", "VRSHR", "VRSHRN", "VTB");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2343 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteFPALU_F3, R52Read_F1, R52Read_F1];
  dag Instrs = (instregex "VSWP", "VTRN", "VUZP", "VZIP");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2344 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d(8|16|32|64)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2345 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1q(8|16|32|64)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2346 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST3Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d(8|16|32|64)T$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2347 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d(8|16|32|64)Q$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2348 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST3Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d64TPseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2349 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d64QPseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_235 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  string NAME = ?;
}
def anonymous_2350 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1LNd(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2351 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1LNdAsm_(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2352 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1LNq(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2353 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d(8|16|32|64)wb");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2354 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1q(8|16|32|64)wb");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2355 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST3Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d(8|16|32|64)Twb");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2356 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d(8|16|32|64)Qwb");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2357 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST3Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d64TPseudoWB");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2358 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1d64QPseudoWB");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2359 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1LNd(8|16|32)_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_236 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_2360 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1LNdWB_(fixed|register)_Asm_(8|16|32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2361 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST1LNq(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2362 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2(d|b)(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2363 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2q(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2364 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2q(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2365 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNd(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2366 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNdAsm_(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2367 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNd(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2368 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNq(16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2369 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNqAsm_(16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_237 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  string NAME = ?;
}
def anonymous_2370 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNq(16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2371 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2(d|b)(8|16|32)wb");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2372 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2q(8|16|32)wb");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2373 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2q(8|16|32)PseudoWB");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2374 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNd(8|16|32)_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2375 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNdWB_(fixed|register)_Asm_(8|16|32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2376 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNd(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2377 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNq(16|32)_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2378 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNqWB_(fixed|register)_Asm_(16|32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2379 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST2LNq(16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_238 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_219, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_221, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_223, anonymous_149];
  string NAME = ?;
}
def anonymous_2380 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3(d|q)(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2381 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3(d|q)Asm_(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2382 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3d(8|16|32)(oddP|P)seudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2383 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNd(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2384 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNdAsm_(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2385 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNd(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2386 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNq(16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2387 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNqAsm_(16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2388 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNq(16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2389 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3(d|q)(8|16|32)_UPD$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_239 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_219, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_221, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_223, anonymous_149];
  string NAME = ?;
}
def anonymous_2390 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3(d|q)WB_(fixed|register)_Asm_(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2391 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2392 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNd(8|16|32)_UPD$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2393 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNdWB_(fixed|register)_Asm_(8|16|32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2394 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNd(8|16|32)Pseudo_UPD$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2395 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNq(16|32)_UPD$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2396 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNqWB_(fixed|register)_Asm_(16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2397 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST3LNq(16|32)Pseudo_UPD$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2398 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST5Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4(d|q)(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2399 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST5Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4(d|q)Asm_(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_24 {	// LLVMType LLVMAnyPointerType
  ValueType VT = iPTRAny;
  int isAny = 1;
  LLVMType ElTy = llvm_float_ty;
  string NAME = ?;
}
def anonymous_240 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_219, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_221, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_223, anonymous_149];
  string NAME = ?;
}
def anonymous_2400 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST5Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4d(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2401 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNd(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2402 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNdAsm_(8|16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2403 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNd(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2404 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNq(16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2405 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNqAsm_(16|32)$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2406 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNq(16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2407 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST5Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4(d|q)(8|16|32)_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2408 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST5Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4(d|q)WB_(fixed|register)_Asm_(8|16|32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2409 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST5Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_241 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_221, anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_223, anonymous_149];
  string NAME = ?;
}
def anonymous_2410 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNd(8|16|32)_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2411 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNdWB_(fixed|register)_Asm_(8|16|32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2412 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNd(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2413 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNq(16|32)_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2414 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNqWB_(fixed|register)_Asm_(16|32)");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2415 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2];
  dag Instrs = (instregex "VST4LNq(16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexR52Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2416 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteNoop];
  dag Instrs = (instregex "(t)?BKPT$", "(t2)?CDP(2)?$", "(t2)?CLREX$", "CONSTPOOL_ENTRY$", "COPY_STRUCT_BYVAL_I32$", "(t2)?CPS[123]p$", "(t2)?DBG$", "(t2)?DMB$", "(t2)?DSB$", "ERET$", "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$", "(t2)?RFE(DA|DB|IA|IB)", "(t)?SETEND", "(t2)?SETPAN", "(t2)?SMC", "SPACE", "(t2)?SRS(DA|DB|IA|IB)", "SWP(B)?", "t?TRAP", "(t2|t)?UDF$", "t2DCPS", "t2SG", "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "CompilerBarrier", "t__brkdiv0");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2417 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteNoop];
  dag Instrs = (instregex "VMRS", "VMSR", "FMSTAT");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2418 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteNoop, WriteNoop];
  dag Instrs = (instregex "(t2)?LDA", "(t2)?LDC", "(t2)?STC", "(t2)?STL", "(t2)?LDREX", "(t2)?STREX", "MEMCPY");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2419 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteNoop, WriteNoop];
  dag Instrs = (instregex "(t2)?MCR(2|R|R2)?$", "(t2)?MRC(2)?$", "(t2)?MRRC(2)?$", "(t2)?MRS(banked|sys|_AR|_M|sys_AR)?$", "(t2)?MSR(banked|i|_AR|_M)?$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_242 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_221, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_223, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_2420 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteNoop];
  dag Instrs = (instregex "FLDM", "FSTM");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2421 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [WriteNoop];
  dag Instrs = (instregex "(t2)?ABS$", "(t)?ADJCALLSTACKDOWN$", "(t)?ADJCALLSTACKUP$", "(t2|t)?Int_eh_sjlj", "tLDRpci_pic", "(t2)?SUBS_PC_LR", "JUMPTABLE", "tInt_WIN_eh_sjlj_longjmp", "VLD(1|2)LN(d|q)(WB_fixed_|WB_register_)?Asm", "VLD(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm", "VST(1|2)LN(d|q)(WB_fixed_|WB_register_)?Asm", "VST(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm", "WIN__CHKSTK", "WIN__DBZCHK");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2422 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1I];
  dag Instrs = (instrs COPY);
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2423 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1B];
  dag Instrs = (instregex "(t2|t)?B$", "t?BX", "(t2|t)?Bcc$", "t?TAILJMP(d|r)", "TCRETURN(d|r)i", "tBfar", "tCBN?Z");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2424 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1B_1I];
  dag Instrs = (instregex "t?BL$", "BL_pred$", "t?BLXi", "t?TPsoft");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2425 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1B_1I];
  dag Instrs = (instregex "BLX", "tBLX(NS)?r");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2426 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1B_1I];
  dag Instrs = (instregex "BCCi64", "BCCZi64");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2427 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1B_1I];
  dag Instrs = (instregex "BR_JTadd", "t?BR_JTr", "t2BR_JT", "t2BXJ", "(t2)?TB(B|H)(_JT)?$", "tBRIND");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2428 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_6cyc_1B_1L];
  dag Instrs = (instregex "BR_JTm");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2429 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1I];
  dag Instrs = (instregex "tADDframe");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_243 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_221, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_223, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_2430 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1M];
  string NAME = ?;
}
def anonymous_2431 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1M];
  string NAME = ?;
}
def anonymous_2432 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1I];
  string NAME = ?;
}
def anonymous_2433 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [ReadDefault];
  string NAME = ?;
}
def anonymous_2434 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [ReadDefault];
  string NAME = ?;
}
def anonymous_2435 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALUsi;
  SchedReadWrite AliasRW = A57WriteALUsi;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2436 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALUsr;
  SchedReadWrite AliasRW = A57WriteALUsr;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2437 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALUSsr;
  SchedReadWrite AliasRW = A57WriteALUSsr;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2438 {	// SchedAlias
  SchedReadWrite MatchRW = ReadALUsr;
  SchedReadWrite AliasRW = A57ReadALUsr;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2439 {	// SchedAlias
  SchedReadWrite MatchRW = WriteCMP;
  SchedReadWrite AliasRW = A57Write_1cyc_1I;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_244 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_2440 {	// SchedAlias
  SchedReadWrite MatchRW = WriteCMPsi;
  SchedReadWrite AliasRW = A57Write_2cyc_1M;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2441 {	// SchedAlias
  SchedReadWrite MatchRW = WriteCMPsr;
  SchedReadWrite AliasRW = A57WriteCMPsr;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2442 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1I];
  dag Instrs = (instregex "MOV(r|i|i16|r_TC)", "(t2)?MVN(CC)?(r|i)", "BMOVPCB_CALL", "BMOVPCRX_CALL", "MOVCC(r|i|i16|i32imm)", "tMOV", "tMVN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2443 {	// SchedVar
  SchedPredicate Predicate = IsCPSRDefinedPred;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1M];
  string NAME = ?;
}
def anonymous_2444 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_1cyc_1I];
  string NAME = ?;
}
def anonymous_2445 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteMOVsi];
  dag Instrs = (instregex "MOV(CC)?si", "MVNsi", "ASRi", "(t2|t)ASRri", "LSRi", "(t2|t)LSRri", "LSLi", "(t2|t)LSLri", "RORi", "(t2|t)RORri", "(t2)?RRX", "t2MOV", "tROR");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2446 {	// SchedVar
  SchedPredicate Predicate = IsCPSRDefinedAndPredicatedPred;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1I];
  string NAME = ?;
}
def anonymous_2447 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteMOVsr];
  dag Instrs = (instregex "MOV(CC)?sr", "MVNsr", "t2MVNs", "ASRr", "(t2|t)ASRrr", "LSRr", "(t2|t)LSRrr", "LSLr", "(t2|t)?LSLrr", "RORr", "(t2|t)RORrr");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2448 {	// SchedVar
  SchedPredicate Predicate = IsR1P0AndLaterPred;
  list<SchedReadWrite> Selected = [A57Write_1cyc_1I];
  string NAME = ?;
}
def anonymous_2449 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteMOVT];
  dag Instrs = (instregex "MOVTi16");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_245 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "SAMPLE_C_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_165];
  string NAME = ?;
}
def anonymous_2450 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteI2pc];
  dag Instrs = (instregex "MOV_ga_pcrel");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2451 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteI2ld];
  dag Instrs = (instregex "MOV_ga_pcrel_ldr");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2452 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1I];
  dag Instrs = (instregex "MOVPC(LR|RX)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2453 {	// SchedAlias
  SchedReadWrite MatchRW = WriteDIV;
  SchedReadWrite AliasRW = A57Write_20cyc_1M;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2454 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1M];
  dag Instrs = (instregex "tMUL");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2455 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL16;
  SchedReadWrite AliasRW = A57Write_3cyc_1M;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2456 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL32;
  SchedReadWrite AliasRW = A57Write_3cyc_1M;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2457 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedRead ReadType = ReadMUL;
  string NAME = ?;
}
def anonymous_2458 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteMLA];
  dag Instrs = (instregex "t2SMLAD", "t2SMLADX", "t2SMLSD", "t2SMLSDX");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2459 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC16;
  SchedReadWrite AliasRW = A57WriteMLA;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_246 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2460 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC32;
  SchedReadWrite AliasRW = A57WriteMLA;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2461 {	// SchedAlias
  SchedReadWrite MatchRW = ReadMAC;
  SchedReadWrite AliasRW = A57ReadMLA;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2462 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC64Lo;
  SchedReadWrite AliasRW = A57WriteMLAL;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2463 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMAC64Hi;
  SchedReadWrite AliasRW = A57WriteMLAL;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2464 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL64Lo;
  SchedReadWrite AliasRW = A57Write_4cyc_1M;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2465 {	// SchedAlias
  SchedReadWrite MatchRW = WriteMUL64Hi;
  SchedReadWrite AliasRW = A57Write_4cyc_1M;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2466 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1I_1M];
  string NAME = ?;
}
def anonymous_2467 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1I_1M];
  string NAME = ?;
}
def anonymous_2468 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteParArith];
  dag Instrs = (instregex "(t2)?SADD(16|8)", "(t2)?SSUB(16|8)", "(t2)?UADD(16|8)", "(t2)?USUB(16|8)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2469 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1I_1M];
  string NAME = ?;
}
def anonymous_247 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75];
  string NAME = ?;
}
def anonymous_2470 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1I_1M];
  string NAME = ?;
}
def anonymous_2471 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteParArithExch];
  dag Instrs = (instregex "(t2)?SASX", "(t2)?SSAX", "(t2)?UASX", "(t2)?USAX");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2472 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1M];
  dag Instrs = (instregex "(t2)?SHADD(16|8)", "(t2)?SHSUB(16|8)", "(t2)?UHADD(16|8)", "(t2)?UHSUB(16|8)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2473 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1I_1M];
  dag Instrs = (instregex "(t2)?SHASX", "(t2)?SHSAX", "(t2)?UHASX", "(t2)?UHSAX");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2474 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1M];
  dag Instrs = (instregex "QADD(16|8)", "QSUB(16|8)", "UQADD(16|8)", "UQSUB(16|8)", "t2(U?)QADD", "t2(U?)QSUB");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2475 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1I_1M];
  dag Instrs = (instregex "(t2)?QASX", "(t2)?QSAX", "(t2)?UQASX", "(t2)?UQSAX");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2476 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1M];
  dag Instrs = (instregex "(t2)?SSAT(16)?", "(t2)?USAT(16)?");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2477 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1M];
  dag Instrs = (instregex "QADD$", "QSUB$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2478 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1I_1M];
  dag Instrs = (instregex "(t2)?QDADD", "(t2)?QDSUB");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2479 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1I];
  dag Instrs = (instregex "(t2)?SBFX", "(t2)?UBFX");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_248 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75];
  string NAME = ?;
}
def anonymous_2480 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1M];
  dag Instrs = (instregex "(t2)?BFI", "(t2)?BFC");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2481 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteSEL];
  dag Instrs = (instregex "(t2)?SEL");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2482 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1I];
  dag Instrs = (instregex "(t2|t)?SXT(B|H)$", "(t2|t)?UXT(B|H)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2483 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1M];
  dag Instrs = (instregex "(t2)?SXTA(B|H)$", "(t2)?UXTA(B|H)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2484 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1M];
  dag Instrs = (instregex "(t2)?SXTAB16", "(t2)?UXTAB16");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2485 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1M];
  dag Instrs = (instregex "(t2)?USAD8", "(t2)?USADA8");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2486 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L];
  dag Instrs = (instregex "LDRi12", "LDRBi12", "LDRcp", "(t2|t)?LDRConstPool", "LDRLIT_ga_(pcrel|abs)", "PICLDR", "tLDR");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2487 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L];
  dag Instrs = (instregex "t2LDRS?(B|H)?(pcrel|T|i8|i12|pci|pci_pic|s)?$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2488 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3NegRegOffPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1I_1L];
  string NAME = ?;
}
def anonymous_2489 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L];
  string NAME = ?;
}
def anonymous_249 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "t";
  string NAME = ?;
}
def anonymous_2490 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteLdrAm3];
  dag Instrs = (instregex "LDR(H|SH|SB)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2491 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3NegRegOffPredX2;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1I_1L];
  string NAME = ?;
}
def anonymous_2492 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteLdrAm3X2, A57WriteLdrAm3X2];
  dag Instrs = (instregex "LDRD$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2493 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L, A57Write_4cyc_1L];
  dag Instrs = (instregex "t2LDRDi8");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2494 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoScaledNotOptimalPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1I_1L];
  string NAME = ?;
}
def anonymous_2495 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoMinusRegPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1I_1L];
  string NAME = ?;
}
def anonymous_2496 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteLdrAmLDSTSO];
  dag Instrs = (instregex "LDRrs", "LDRBrs");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2497 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L_1I, A57WrBackOne];
  dag Instrs = (instregex "LDR_PRE_IMM", "LDRB_PRE_IMM", "t2LDRB_PRE");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2498 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoScaledNotOptimalPredX2;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1I_1L];
  string NAME = ?;
}
def anonymous_2499 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I];
  string NAME = ?;
}
def anonymous_25 {	// LLVMType LLVMAnyPointerType
  ValueType VT = iPTRAny;
  int isAny = 1;
  LLVMType ElTy = llvm_double_ty;
  string NAME = ?;
}
def anonymous_250 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "t";
  string NAME = ?;
}
def anonymous_2500 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteLdrAmLDSTSOPre, A57WrBackTwo];
  dag Instrs = (instregex "LDR_PRE_REG", "LDRB_PRE_REG");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2501 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3RegOffPredX2;
  list<SchedReadWrite> Selected = [A57WrBackTwo];
  string NAME = ?;
}
def anonymous_2502 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57WrBackOne];
  string NAME = ?;
}
def anonymous_2503 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L, A57WriteLdrAm3PreWrBack];
  dag Instrs = (instregex "LDR(H|SH|SB)_PRE");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2504 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L, A57WrBackOne];
  dag Instrs = (instregex "t2LDR(H|SH|SB)?_PRE");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2505 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3RegOffPredX3;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1I_1L];
  string NAME = ?;
}
def anonymous_2506 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3RegOffPredX3;
  list<SchedReadWrite> Selected = [A57WrBackTwo];
  string NAME = ?;
}
def anonymous_2507 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteLdrDAm3Pre, A57WriteLdrDAm3Pre, A57WriteLdrDAm3PreWrBack];
  dag Instrs = (instregex "LDRD_PRE");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2508 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57WrBackOne];
  dag Instrs = (instregex "t2LDRD_PRE");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2509 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L_1I, A57WrBackOne];
  dag Instrs = (instregex "LDR(T?)_POST_IMM", "LDRB(T?)_POST_IMM", "LDR(SB|H|SH)Ti", "t2LDRB_POST");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_251 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2510 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3RegOffPred;
  list<SchedReadWrite> Selected = [A57WrBackTwo];
  string NAME = ?;
}
def anonymous_2511 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L_1I, A57WriteLdrAm3PostWrBack];
  dag Instrs = (instregex "LDR(H|SH|SB)_POST");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2512 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L, A57WrBackOne];
  dag Instrs = (instregex "t2LDR(H|SH|SB)?_POST");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2513 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L_1I, A57WrBackTwo];
  dag Instrs = (instregex "LDR_POST_REG", "LDRB_POST_REG", "LDR(B?)T_POST$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2514 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm2ScaledPred;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1I_1L_1M];
  string NAME = ?;
}
def anonymous_2515 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm2ScaledPred;
  list<SchedReadWrite> Selected = [A57WrBackThree];
  string NAME = ?;
}
def anonymous_2516 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57WrBackTwo];
  string NAME = ?;
}
def anonymous_2517 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteLdrTRegPost, A57WriteLdrTRegPostWrBack];
  dag Instrs = (instregex "LDRT_POST_REG", "LDRBT_POST_REG");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2518 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L_1I, A57WrBackTwo];
  dag Instrs = (instregex "LDR(SB|H|SH)Tr");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2519 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57WriteLdrAm3PostWrBackX3];
  dag Instrs = (instregex "LDRD_POST");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_252 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75];
  string NAME = ?;
}
def anonymous_2520 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57WrBackOne];
  dag Instrs = (instregex "t2LDRD_POST");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2521 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1L];
  dag Instrs = (instregex "(t2)?PLDi12", "(t2)?PLDWi12", "t2PLDW?(i8|pci|s)", "(t2)?PLI");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2522 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoScaledNotOptimalPredX0;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1I_1L];
  string NAME = ?;
}
def anonymous_2523 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoMinusRegPredX0;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1I_1L];
  string NAME = ?;
}
def anonymous_2524 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WritePLD];
  dag Instrs = (instregex "PLDrs", "PLDWrs");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2525 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1L, A57Write_3cyc_1L];
  string NAME = ?;
}
def anonymous_2526 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1L, A57Write_3cyc_1L, A57Write_4cyc_1L, A57Write_4cyc_1L];
  string NAME = ?;
}
def anonymous_2527 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1L, A57Write_3cyc_1L, A57Write_4cyc_1L, A57Write_4cyc_1L, A57Write_5cyc_1L, A57Write_5cyc_1L];
  string NAME = ?;
}
def anonymous_2528 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1L, A57Write_3cyc_1L, A57Write_4cyc_1L, A57Write_4cyc_1L, A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L];
  string NAME = ?;
}
def anonymous_2529 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1L, A57Write_3cyc_1L, A57Write_4cyc_1L, A57Write_4cyc_1L, A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L];
  string NAME = ?;
}
def anonymous_253 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2530 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1L, A57Write_3cyc_1L, A57Write_4cyc_1L, A57Write_4cyc_1L, A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L];
  string NAME = ?;
}
def anonymous_2531 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1L, A57Write_3cyc_1L, A57Write_4cyc_1L, A57Write_4cyc_1L, A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L];
  string NAME = ?;
}
def anonymous_2532 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1L, A57Write_3cyc_1L, A57Write_4cyc_1L, A57Write_4cyc_1L, A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_10cyc_1L];
  string NAME = ?;
}
def anonymous_2533 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1L, A57Write_3cyc_1L, A57Write_4cyc_1L, A57Write_4cyc_1L, A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_10cyc_1L];
  string NAME = ?;
}
def anonymous_2534 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2535 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2536 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2537 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2538 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2539 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I];
  string NAME = ?;
}
def anonymous_254 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75];
  string NAME = ?;
}
def anonymous_2540 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2541 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_11cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2542 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_11cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2543 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2544 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2545 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2546 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2547 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2548 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2549 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I];
  string NAME = ?;
}
def anonymous_255 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2550 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2551 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57WrBackOne, A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2552 {	// SchedVar
  SchedPredicate Predicate = IsLdmBaseRegInList;
  list<SchedReadWrite> Selected = [A57WriteLDMreginlist];
  string NAME = ?;
}
def anonymous_2553 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57WriteLDMnoreginlist];
  string NAME = ?;
}
def anonymous_2554 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteLDM];
  dag Instrs = (instregex "(t|t2|sys)?LDM(IA|DA|DB|IB)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2555 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteLDM_Upd];
  dag Instrs = (instregex "(t|t2|sys)?LDM(IA_UPD|DA_UPD|DB_UPD|IB_UPD|IA_RET)", "tPOP");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2556 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1L];
  dag Instrs = (instregex "VLLDM");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2557 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1S];
  dag Instrs = (instregex "STRi12", "STRBi12", "PICSTR", "t2STR(B?)(T|i12|i8|s)", "t2STRDi8", "t2STRH(i12|i8|s)", "tSTR");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2558 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoScaledNotOptimalPred;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1I_1S];
  string NAME = ?;
}
def anonymous_2559 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoMinusRegPred;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1I_1S];
  string NAME = ?;
}
def anonymous_256 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75];
  string NAME = ?;
}
def anonymous_2560 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_1cyc_1S];
  string NAME = ?;
}
def anonymous_2561 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteStrAmLDSTSO];
  dag Instrs = (instregex "STRrs", "STRBrs");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2562 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3NegRegOffPred;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1I_1S];
  string NAME = ?;
}
def anonymous_2563 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteStrAm3];
  dag Instrs = (instregex "STRH$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2564 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3NegRegOffPredX2;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1I_1S];
  string NAME = ?;
}
def anonymous_2565 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteStrAm3X2];
  dag Instrs = (instregex "STRD$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2566 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_1cyc_1S_1I];
  dag Instrs = (instregex "STR_PRE_IMM", "STRB_PRE_IMM", "STR(B)?(r|i)_preidx", "(t2)?STRH_(preidx|PRE)", "t2STR(B?)_(PRE|preidx)", "t2STRD_PRE");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2567 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoScaledNotOptimalPredX2;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1I_1S];
  string NAME = ?;
}
def anonymous_2568 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoMinusRegPredX2;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1I_1S];
  string NAME = ?;
}
def anonymous_2569 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoScaledPredX2;
  list<SchedReadWrite> Selected = [A57Write_1cyc_1S_1M];
  string NAME = ?;
}
def anonymous_257 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_2570 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_1cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2571 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoScaledPredX2;
  list<SchedReadWrite> Selected = [A57WrBackTwo];
  string NAME = ?;
}
def anonymous_2572 {	// SchedVar
  SchedPredicate Predicate = IsLdstsoMinusRegPredX2;
  list<SchedReadWrite> Selected = [A57WrBackTwo];
  string NAME = ?;
}
def anonymous_2573 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteStrAmLDSTSOPreWrBack, A57WriteStrAmLDSTSOPre];
  dag Instrs = (instregex "STR_PRE_REG", "STRB_PRE_REG");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2574 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3NegRegOffPredX2;
  list<SchedReadWrite> Selected = [A57WrBackTwo];
  string NAME = ?;
}
def anonymous_2575 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteStrAm3PreWrBackX2, A57WriteStrAm3PreX2];
  dag Instrs = (instregex "STRH_PRE");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2576 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3NegRegOffPredX3;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1I_1S];
  string NAME = ?;
}
def anonymous_2577 {	// SchedVar
  SchedPredicate Predicate = IsLdrAm3NegRegOffPredX3;
  list<SchedReadWrite> Selected = [A57WrBackTwo];
  string NAME = ?;
}
def anonymous_2578 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteStrAm3PreWrBackX3, A57WriteStrAm3PreX3];
  dag Instrs = (instregex "STRD_PRE");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2579 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_1cyc_1S_1I];
  dag Instrs = (instregex "STR(T?)_POST_IMM", "STRB(T?)_POST_IMM", "t2STR(B?)_POST");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_258 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_163];
  string NAME = ?;
}
def anonymous_2580 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackTwo, A57Write_1cyc_1S_1M];
  dag Instrs = (instregex "STR(T?)_POST_REG", "STRB(T?)_POST_REG", "STR(B?)T_POST$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2581 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_1cyc_1S_1I];
  dag Instrs = (instregex "(t2)?STR(H|D)_POST", "STRHT(i|r)", "t2STRHT");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2582 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_1cyc_1S];
  string NAME = ?;
}
def anonymous_2583 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1S];
  string NAME = ?;
}
def anonymous_2584 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1S];
  string NAME = ?;
}
def anonymous_2585 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1S];
  string NAME = ?;
}
def anonymous_2586 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1S];
  string NAME = ?;
}
def anonymous_2587 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_6cyc_1S];
  string NAME = ?;
}
def anonymous_2588 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_7cyc_1S];
  string NAME = ?;
}
def anonymous_2589 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_8cyc_1S];
  string NAME = ?;
}
def anonymous_259 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_163];
  string NAME = ?;
}
def anonymous_2590 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1S];
  string NAME = ?;
}
def anonymous_2591 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_1cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2592 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2593 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2594 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2595 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2596 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_6cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2597 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_7cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2598 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_8cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2599 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1S_1I];
  string NAME = ?;
}
def anonymous_26 {	// LLVMType LLVMAnyPointerType
  ValueType VT = iPTRAny;
  int isAny = 1;
  LLVMType ElTy = llvm_i32_ty;
  string NAME = ?;
}
def anonymous_260 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_2600 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteSTM];
  dag Instrs = (instregex "(t2|sys|t)?STM(IA|DA|DB|IB)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2601 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57WriteSTM_Upd];
  dag Instrs = (instregex "(t2|sys|t)?STM(IA_UPD|DA_UPD|DB_UPD|IB_UPD)", "tPUSH");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2602 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1S];
  dag Instrs = (instregex "VLSTM");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2603 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPALU32;
  SchedReadWrite AliasRW = A57Write_5cyc_1V;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2604 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPALU64;
  SchedReadWrite AliasRW = A57Write_5cyc_1V;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2605 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VABS(S|D|H)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2606 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [A57Write_6cyc_1V_1X];
  string NAME = ?;
}
def anonymous_2607 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_3cyc_1X];
  string NAME = ?;
}
def anonymous_2608 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVcmp];
  dag Instrs = (instregex "VCMP(D|S|H|ZD|ZS|ZH)$", "VCMPE(D|S|H|ZD|ZS|ZH)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2609 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VCVT(A|N|P|M)(SH|UH|SS|US|SD|UD)", "VCVT(BDH|THD|TDH)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_261 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_163];
  string NAME = ?;
}
def anonymous_2610 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VTOSLS", "VTOUHS", "VTOULS");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2611 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPCVT;
  SchedReadWrite AliasRW = A57Write_5cyc_1V;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2612 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VJCVT");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2613 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VRINT(A|N|P|M|Z|R|X)(H|S|D)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2614 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPDIV32;
  SchedReadWrite AliasRW = A57Write_17cyc_1W;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2615 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPDIV64;
  SchedReadWrite AliasRW = A57Write_32cyc_1W;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2616 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPSQRT32;
  SchedReadWrite AliasRW = A57Write_17cyc_1W;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2617 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPSQRT64;
  SchedReadWrite AliasRW = A57Write_32cyc_1W;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2618 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_17cyc_1W];
  dag Instrs = (instregex "VSQRTH");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2619 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VMAX", "VMIN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_262 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_2620 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMUL32;
  SchedReadWrite AliasRW = A57WriteVMUL;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2621 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMUL64;
  SchedReadWrite AliasRW = A57WriteVMUL;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2622 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedRead ReadType = ReadFPMUL;
  string NAME = ?;
}
def anonymous_2623 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMAC32;
  SchedReadWrite AliasRW = A57WriteVFMA;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2624 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMAC64;
  SchedReadWrite AliasRW = A57WriteVFMA;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2625 {	// SchedAlias
  SchedReadWrite MatchRW = ReadFPMAC;
  SchedReadWrite AliasRW = A57ReadVFMA5;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2626 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVFMA, A57ReadVFMA5, ReadFPMUL, ReadFPMUL];
  dag Instrs = (instregex "VMLAH", "VMLSH", "VNMLAH", "VNMLSH");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2627 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVMUL];
  dag Instrs = (instregex "VUDOTD", "VSDOTD", "VUDOTQ", "VSDOTQ");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2628 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VNEG");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2629 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VSEL");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_263 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_163];
  string NAME = ?;
}
def anonymous_2630 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "FCONST(D|S|H)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2631 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VMOV(D|S|H)(cc)?$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2632 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VINSH");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2633 {	// SchedAlias
  SchedReadWrite MatchRW = WriteFPMOV;
  SchedReadWrite AliasRW = A57Write_5cyc_1L;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2634 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1L, A57Write_5cyc_1L];
  dag Instrs = (instregex "VMOV(RRS|RRD)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2635 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1I];
  dag Instrs = (instregex "VMOVDRR");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2636 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1L];
  dag Instrs = (instregex "VLDR(D|S|H)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2637 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1L];
  dag Instrs = (instregex "VLDMQIA$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2638 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_5cyc_1L];
  string NAME = ?;
}
def anonymous_2639 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L];
  string NAME = ?;
}
def anonymous_264 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_2640 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L];
  string NAME = ?;
}
def anonymous_2641 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L];
  string NAME = ?;
}
def anonymous_2642 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L];
  string NAME = ?;
}
def anonymous_2643 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_10cyc_1L];
  string NAME = ?;
}
def anonymous_2644 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_11cyc_1L];
  string NAME = ?;
}
def anonymous_2645 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L, A57Write_12cyc_1L];
  string NAME = ?;
}
def anonymous_2646 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L, A57Write_12cyc_1L];
  string NAME = ?;
}
def anonymous_2647 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_6cyc_1L];
  string NAME = ?;
}
def anonymous_2648 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L];
  string NAME = ?;
}
def anonymous_2649 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L];
  string NAME = ?;
}
def anonymous_265 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_163];
  string NAME = ?;
}
def anonymous_2650 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L];
  string NAME = ?;
}
def anonymous_2651 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L, A57Write_13cyc_1L, A57Write_14cyc_1L];
  string NAME = ?;
}
def anonymous_2652 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L, A57Write_13cyc_1L, A57Write_14cyc_1L, A57Write_15cyc_1L, A57Write_16cyc_1L];
  string NAME = ?;
}
def anonymous_2653 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L, A57Write_13cyc_1L, A57Write_14cyc_1L, A57Write_15cyc_1L, A57Write_16cyc_1L, A57Write_17cyc_1L, A57Write_18cyc_1L];
  string NAME = ?;
}
def anonymous_2654 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L, A57Write_13cyc_1L, A57Write_14cyc_1L, A57Write_15cyc_1L, A57Write_16cyc_1L, A57Write_17cyc_1L, A57Write_18cyc_1L, A57Write_19cyc_1L, A57Write_20cyc_1L];
  string NAME = ?;
}
def anonymous_2655 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L, A57Write_6cyc_1L, A57Write_7cyc_1L, A57Write_8cyc_1L, A57Write_9cyc_1L, A57Write_10cyc_1L, A57Write_11cyc_1L, A57Write_12cyc_1L, A57Write_13cyc_1L, A57Write_14cyc_1L, A57Write_15cyc_1L, A57Write_16cyc_1L, A57Write_17cyc_1L, A57Write_18cyc_1L, A57Write_19cyc_1L, A57Write_20cyc_1L];
  string NAME = ?;
}
def anonymous_2656 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [A57WriteVLDMcond];
  string NAME = ?;
}
def anonymous_2657 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57WriteVLDMuncond];
  string NAME = ?;
}
def anonymous_2658 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVLDM];
  dag Instrs = (instregex "VLDM(DIA|SIA)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2659 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I];
  string NAME = ?;
}
def anonymous_266 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2660 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2661 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2662 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2663 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2664 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2665 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_11cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2666 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I, A57Write_12cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2667 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I, A57Write_12cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2668 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2669 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I];
  string NAME = ?;
}
def anonymous_267 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_269];
  string NAME = ?;
}
def anonymous_2670 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2671 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2672 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I, A57Write_13cyc_1L_1I, A57Write_14cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2673 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I, A57Write_13cyc_1L_1I, A57Write_14cyc_1L_1I, A57Write_15cyc_1L_1I, A57Write_16cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2674 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I, A57Write_13cyc_1L_1I, A57Write_14cyc_1L_1I, A57Write_15cyc_1L_1I, A57Write_16cyc_1L_1I, A57Write_17cyc_1L_1I, A57Write_18cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2675 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I, A57Write_13cyc_1L_1I, A57Write_14cyc_1L_1I, A57Write_15cyc_1L_1I, A57Write_16cyc_1L_1I, A57Write_17cyc_1L_1I, A57Write_18cyc_1L_1I, A57Write_19cyc_1L_1I, A57Write_20cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2676 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I, A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I, A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I, A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I, A57Write_13cyc_1L_1I, A57Write_14cyc_1L_1I, A57Write_15cyc_1L_1I, A57Write_16cyc_1L_1I, A57Write_17cyc_1L_1I, A57Write_18cyc_1L_1I, A57Write_19cyc_1L_1I, A57Write_20cyc_1L_1I];
  string NAME = ?;
}
def anonymous_2677 {	// SchedVar
  SchedPredicate Predicate = IsPredicatedPred;
  list<SchedReadWrite> Selected = [A57WriteVLDMcond_UPD];
  string NAME = ?;
}
def anonymous_2678 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57WriteVLDMuncond_UPD];
  string NAME = ?;
}
def anonymous_2679 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57WriteVLDM_UPD];
  dag Instrs = (instregex "VLDM(DIA_UPD|DDB_UPD|SIA_UPD|SDB_UPD)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_268 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_269];
  string NAME = ?;
}
def anonymous_2680 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1S];
  dag Instrs = (instregex "VSTR(D|S|H)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2681 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1S];
  dag Instrs = (instregex "VSTMQIA$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2682 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1S];
  string NAME = ?;
}
def anonymous_2683 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1S];
  string NAME = ?;
}
def anonymous_2684 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_6cyc_1S];
  string NAME = ?;
}
def anonymous_2685 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_8cyc_1S];
  string NAME = ?;
}
def anonymous_2686 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_10cyc_1S];
  string NAME = ?;
}
def anonymous_2687 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_12cyc_1S];
  string NAME = ?;
}
def anonymous_2688 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_14cyc_1S];
  string NAME = ?;
}
def anonymous_2689 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_16cyc_1S];
  string NAME = ?;
}
def anonymous_269 {	// AMDGPUArg
  LLVMType Type = anonymous_191;
  string Name = "t";
  string NAME = ?;
}
def anonymous_2690 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1S];
  string NAME = ?;
}
def anonymous_2691 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred1;
  list<SchedReadWrite> Selected = [A57Write_2cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2692 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred2;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2693 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred3;
  list<SchedReadWrite> Selected = [A57Write_6cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2694 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred4;
  list<SchedReadWrite> Selected = [A57Write_8cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2695 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred5;
  list<SchedReadWrite> Selected = [A57Write_10cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2696 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred6;
  list<SchedReadWrite> Selected = [A57Write_12cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2697 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred7;
  list<SchedReadWrite> Selected = [A57Write_14cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2698 {	// SchedVar
  SchedPredicate Predicate = A57LMAddrPred8;
  list<SchedReadWrite> Selected = [A57Write_16cyc_1S_1I];
  string NAME = ?;
}
def anonymous_2699 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVSTMs];
  dag Instrs = (instregex "VSTMSIA$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_27 {	// LLVMType LLVMQualPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = llvm_i8_ty;
  int AddrSpace = 7;
  string NAME = ?;
}
def anonymous_270 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2700 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVSTMd];
  dag Instrs = (instregex "VSTMDIA$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2701 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57WriteVSTMs_Upd];
  dag Instrs = (instregex "VSTM(SIA_UPD|SDB_UPD)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2702 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57WriteVSTMd_Upd];
  dag Instrs = (instregex "VSTM(DIA_UPD|DDB_UPD)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2703 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VABD(s|u)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2704 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVABAD, A57ReadVABAD];
  dag Instrs = (instregex "VABA(s|u)(v8i8|v4i16|v2i32)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2705 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVABAQ, A57ReadVABAQ];
  dag Instrs = (instregex "VABA(s|u)(v16i8|v8i16|v4i32)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2706 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVABAL, A57ReadVABAL];
  dag Instrs = (instregex "VABAL(s|u)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2707 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VABDL(s|u)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2708 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VADDv", "VADDL", "VADDW", "VNEG(s8d|s16d|s32d|s8q|s16q|s32q|d|q)", "VPADDi", "VPADDL", "VSUBv", "VSUBL", "VSUBW");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2709 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VABS", "VADDHN", "VHADD", "VHSUB", "VQABS", "VQADD", "VQNEG", "VQSUB", "VRADDHN", "VRHADD", "VRSUBHN", "VSUBHN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_271 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_269];
  string NAME = ?;
}
def anonymous_2710 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VCEQ", "VCGE", "VCGT", "VCLE", "VTST", "VCLT");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2711 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VAND", "VBIC", "VMVN", "VORR", "VORN", "VEOR");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2712 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "(VMAX|VMIN)(s|u)", "(VPMAX|VPMIN)(s8|s16|s32|u8|u16|u32)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2713 {	// SchedVar
  SchedPredicate Predicate = IsR1P0AndLaterPred;
  list<SchedReadWrite> Selected = [A57Write_4cyc_1W];
  string NAME = ?;
}
def anonymous_2714 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1W];
  string NAME = ?;
}
def anonymous_2715 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVMULD_VecInt];
  dag Instrs = (instregex "VMUL(v8i8|v4i16|v2i32|pd)", "VMULsl(v4i16|v2i32)", "VQDMULH(sl)?(v4i16|v2i32)", "VQRDMULH(sl)?(v4i16|v2i32)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2716 {	// SchedVar
  SchedPredicate Predicate = IsR1P0AndLaterPred;
  list<SchedReadWrite> Selected = [A57Write_5cyc_1W];
  string NAME = ?;
}
def anonymous_2717 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [A57Write_6cyc_1W];
  string NAME = ?;
}
def anonymous_2718 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVMULQ_VecInt];
  dag Instrs = (instregex "VMUL(v16i8|v8i16|v4i32|pq)", "VMULsl(v8i16|v4i32)", "VQDMULH(sl)?(v8i16|v4i32)", "VQRDMULH(sl)?(v8i16|v4i32)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2719 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [A57WriteVMLAD_VecInt];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_272 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2720 {	// SchedVar
  SchedPredicate Predicate = IsR1P0AndLaterPred;
  list<SchedReadWrite> Selected = [anonymous_2719];
  string NAME = ?;
}
def anonymous_2721 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 4;
  list<SchedWrite> ValidWrites = [A57WriteVMLAD_VecInt];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_2722 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [anonymous_2721];
  string NAME = ?;
}
def anonymous_2723 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVMLAD_VecInt, A57ReadVMLAD_VecInt];
  dag Instrs = (instregex "VMLA(sl)?(v8i8|v4i16|v2i32)", "VMLS(sl)?(v8i8|v4i16|v2i32)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2724 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [A57WriteVMLAQ_VecInt];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_2725 {	// SchedVar
  SchedPredicate Predicate = IsR1P0AndLaterPred;
  list<SchedReadWrite> Selected = [anonymous_2724];
  string NAME = ?;
}
def anonymous_2726 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 4;
  list<SchedWrite> ValidWrites = [A57WriteVMLAQ_VecInt];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_2727 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [anonymous_2726];
  string NAME = ?;
}
def anonymous_2728 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVMLAQ_VecInt, A57ReadVMLAQ_VecInt];
  dag Instrs = (instregex "VMLA(sl)?(v16i8|v8i16|v4i32)", "VMLS(sl)?(v16i8|v8i16|v4i32)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2729 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [A57WriteVMLAL_VecInt];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_273 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_269];
  string NAME = ?;
}
def anonymous_2730 {	// SchedVar
  SchedPredicate Predicate = IsR1P0AndLaterPred;
  list<SchedReadWrite> Selected = [anonymous_2729];
  string NAME = ?;
}
def anonymous_2731 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 4;
  list<SchedWrite> ValidWrites = [A57WriteVMLAL_VecInt];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_2732 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [anonymous_2731];
  string NAME = ?;
}
def anonymous_2733 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVMLAL_VecInt, A57ReadVMLAL_VecInt];
  dag Instrs = (instregex "VMLAL(s|u)", "VMLSL(s|u)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2734 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 2;
  list<SchedWrite> ValidWrites = [A57WriteVQDMLAL_VecInt];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_2735 {	// SchedVar
  SchedPredicate Predicate = IsR1P0AndLaterPred;
  list<SchedReadWrite> Selected = [anonymous_2734];
  string NAME = ?;
}
def anonymous_2736 {	// SchedReadWrite SchedRead ProcReadAdvance SchedReadAdvance
  int Cycles = 3;
  list<SchedWrite> ValidWrites = [A57WriteVQDMLAL_VecInt];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = ?;
  string NAME = ?;
}
def anonymous_2737 {	// SchedVar
  SchedPredicate Predicate = NoSchedPred;
  list<SchedReadWrite> Selected = [anonymous_2736];
  string NAME = ?;
}
def anonymous_2738 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVQDMLAL_VecInt, A57ReadVQDMLAL_VecInt];
  dag Instrs = (instregex "VQDMLAL", "VQDMLSL");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2739 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVQDMLAL_VecInt, A57ReadVQDMLAL_VecInt];
  dag Instrs = (instregex "VQRDMLAH", "VQRDMLSH");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_274 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2740 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVMULL_VecInt];
  dag Instrs = (instregex "VMULL(s|u|p8|sls|slu)", "VQDMULL");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2741 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVPADAL, A57ReadVPADAL];
  dag Instrs = (instregex "VPADAL(s|u)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2742 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVSRA, A57ReadVSRA];
  dag Instrs = (instregex "VSRA", "VRSRA");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2743 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1X];
  dag Instrs = (instregex "VMOVL", "VSHLi", "VSHLL", "VSHR(s|u)", "VSHRN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2744 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1X];
  dag Instrs = (instregex "VQRSHRN", "VQRSHRUN", "VQSHL(si|ui|su)", "VQSHRN", "VQSHRUN", "VRSHR(s|u)", "VRSHRN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2745 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1X];
  dag Instrs = (instregex "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2746 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1X];
  dag Instrs = (instregex "VSLI(v16i8|v8i16|v4i32|v2i64)", "VSRI(v16i8|v8i16|v4i32|v2i64)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2747 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1X];
  dag Instrs = (instregex "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2748 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1X];
  dag Instrs = (instregex "VSHL(s|u)(v16i8|v8i16|v4i32|v2i64)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2749 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1X];
  dag Instrs = (instregex "VQRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)", "VQSHL(s|u)(v8i8|v4i16|v2i32|v1i64)", "VRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_275 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269];
  string NAME = ?;
}
def anonymous_2750 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1X];
  dag Instrs = (instregex "VQRSHL(s|u)(v16i8|v8i16|v4i32|v2i64)", "VQSHL(s|u)(v16i8|v8i16|v4i32|v2i64)", "VRSHL(s|u)(v16i8|v8i16|v4i32|v2i64)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2751 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VABS(fd|fq|hd|hq)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2752 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VABD(fd|fq|hd|hq)", "VADD(fd|fq|hd|hq)", "VPADD(f|h)", "VSUB(fd|fq|hd|hq)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2753 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VCADD", "VCMLA");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2754 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VAC(GE|GT|LE|LT)", "VC(EQ|GE|GT|LE)(fd|fq|hd|hq)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2755 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VCVT(f2sd|f2ud|s2fd|u2fd|f2sq|f2uq|s2fq|u2fq|f2xsd|f2xud|xs2fd|xu2fd)", "VCVT(f2xsq|f2xuq|xs2fq|xu2fq)", "VCVT(AN|MN|NN|PN)(SDf|SQf|UDf|UQf|SDh|SQh|UDh|UQh)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2756 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1V];
  dag Instrs = (instregex "VCVT(h2sd|h2ud|s2hd|u2hd|h2sq|h2uq|s2hq|u2hq|h2xsd|h2xud|xs2hd|xu2hd)", "VCVT(h2xsq|h2xuq|xs2hq|xu2hq)", "VCVT(f2h|h2f)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2757 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "(VMAX|VMIN)(fd|fq|hd|hq)", "(VPMAX|VPMIN)(f|h)", "VMAXNM", "VMINNM");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2758 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVMUL_VecFP];
  dag Instrs = (instregex "VMUL(sl)?(fd|fq|hd|hq)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2759 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WriteVMLA_VecFP, A57ReadVMLA_VecFP];
  dag Instrs = (instregex "(VMLA|VMLS)(sl)?(fd|fq|hd|hq)", "(VFMA|VFMS)(fd|fq|hd|hq)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_276 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_2760 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VNEG(fd|f32q|hd|hq)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2761 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VRINT(AN|MN|NN|PN|XN|ZN)(Df|Qf|Dh|Qh)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2762 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VBIF", "VBIT", "VBSL");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2763 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VCLS", "VCLZ", "VCNT");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2764 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V];
  dag Instrs = (instregex "VDUP(8|16|32)(d|q)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2765 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VDUPLN(8|16|32)(d|q)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2766 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VEXT(d|q)(8|16|32|64)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2767 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VMOV(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v1i64|v2i64|v2f32|v4f32)", "VMOVD0", "VMOVQ0");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2768 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VMOVN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2769 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1X];
  dag Instrs = (instregex "VQMOVN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_277 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_269, anonymous_192];
  string NAME = ?;
}
def anonymous_2770 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1V];
  dag Instrs = (instregex "VRECPE", "VRSQRTE");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2771 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1V];
  dag Instrs = (instregex "VRECPS", "VRSQRTS");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2772 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V];
  dag Instrs = (instregex "VREV", "VSWP", "VTB(L|X)(1|2)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2773 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_6cyc_1V];
  dag Instrs = (instregex "VTBL(3|4)", "VTBX(3|4)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2774 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_6cyc_1L_1I];
  dag Instrs = (instregex "VGETLN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2775 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V];
  dag Instrs = (instregex "VSETLN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2776 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V, A57Write_3cyc_1V];
  dag Instrs = (instregex "VTRN");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2777 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1V, A57Write_3cyc_1V];
  dag Instrs = (instregex "VUZPd", "VZIPd");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2778 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_6cyc_1V, A57Write_6cyc_1V];
  dag Instrs = (instregex "VUZPq", "VZIPq");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2779 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedWrite WriteType = WriteVLD1;
  string NAME = ?;
}
def anonymous_278 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_269, anonymous_192];
  string NAME = ?;
}
def anonymous_2780 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedWrite WriteType = WriteVLD2;
  string NAME = ?;
}
def anonymous_2781 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedWrite WriteType = WriteVLD3;
  string NAME = ?;
}
def anonymous_2782 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedWrite WriteType = WriteVLD4;
  string NAME = ?;
}
def anonymous_2783 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedWrite WriteType = WriteVST1;
  string NAME = ?;
}
def anonymous_2784 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedWrite WriteType = WriteVST2;
  string NAME = ?;
}
def anonymous_2785 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedWrite WriteType = WriteVST3;
  string NAME = ?;
}
def anonymous_2786 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 1;
  int NumMicroOps = 1;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedWrite WriteType = WriteVST4;
  string NAME = ?;
}
def anonymous_2787 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1L];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2788 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_5cyc_1L_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)wb");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2789 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_6cyc_1L];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)(T|Q)$", "VLD1d64(T|Q)Pseudo");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_279 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_2790 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_6cyc_1L_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD1(d|q)(8|16|32|64)(T|Q)wb");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2791 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V];
  dag Instrs = (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2792 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)", "VLD1LNq(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2793 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V];
  dag Instrs = (instregex "VLD2(d|q)(8|16|32)$", "VLD2q(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2794 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD2(d|q)(8|16|32)wb", "VLD2q(8|16|32)PseudoWB");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2795 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V];
  dag Instrs = (instregex "VLD2b(8|16|32)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2796 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD2b(8|16|32)wb");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2797 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V];
  dag Instrs = (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$", "VLD2LN(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2798 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V, A57WrBackOne];
  dag Instrs = (instregex "VLD2LN(d|q)(8|16|32)_UPD$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2799 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD2DUPd(8|16|32|8x2|16x2|32x2)wb", "VLD2LN(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_28 {	// LLVMType LLVMQualPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = llvm_i8_ty;
  int AddrSpace = 4;
  string NAME = ?;
}
def anonymous_280 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_192];
  string NAME = ?;
}
def anonymous_2800 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V];
  dag Instrs = (instregex "VLD3(d|q)(8|16|32)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2801 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V];
  dag Instrs = (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2802 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD3(d|q)(8|16|32)_UPD$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2803 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2804 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V];
  dag Instrs = (instregex "VLD3LN(d|q)32$", "VLD3LN(d|q)32Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2805 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD3LN(d|q)32_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2806 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD3LN(d|q)32Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2807 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V];
  dag Instrs = (instregex "VLD3LN(d|q)(8|16)$", "VLD3LN(d|q)(8|16)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2808 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD3LN(d|q)(8|16)_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2809 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD3LN(d|q)(8|16)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_281 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_2810 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V];
  dag Instrs = (instregex "VLD3DUP(d|q)(8|16|32)$", "VLD3DUP(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2811 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD3DUP(d|q)(8|16|32)_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2812 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD3DUP(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2813 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V];
  dag Instrs = (instregex "VLD4(d|q)(8|16|32)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2814 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V];
  dag Instrs = (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2815 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD4(d|q)(8|16|32)_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2816 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2817 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V];
  dag Instrs = (instregex "VLD4LN(d|q)32$", "VLD4LN(d|q)32Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2818 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD4LN(d|q)32_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2819 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD4LN(d|q)32Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_282 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_192];
  string NAME = ?;
}
def anonymous_2820 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V];
  dag Instrs = (instregex "VLD4LN(d|q)(8|16)$", "VLD4LN(d|q)(8|16)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2821 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD4LN(d|q)(8|16)_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2822 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_9cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD4LN(d|q)(8|16)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2823 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V];
  dag Instrs = (instregex "VLD4DUP(d|q)(8|16|32)$", "VLD4DUP(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2824 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD4DUP(d|q)(8|16|32)_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2825 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_8cyc_1L_1V_1I, A57WrBackOne];
  dag Instrs = (instregex "VLD4DUP(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2826 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_1cyc_1S];
  dag Instrs = (instregex "VST1d(8|16|32|64)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2827 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_1cyc_1S_1I];
  dag Instrs = (instregex "VST1d(8|16|32|64)wb");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2828 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_2cyc_1S];
  dag Instrs = (instregex "VST1q(8|16|32|64)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2829 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_2cyc_1S_1I];
  dag Instrs = (instregex "VST1q(8|16|32|64)wb");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_283 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_2830 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1S];
  dag Instrs = (instregex "VST1d(8|16|32|64)T$", "VST1d64TPseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2831 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_3cyc_1S_1I];
  dag Instrs = (instregex "VST1d(8|16|32|64)Twb", "VST1d64TPseudoWB");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2832 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1S];
  dag Instrs = (instregex "VST1d(8|16|32|64)(Q|QPseudo)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2833 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_4cyc_1S_1I];
  dag Instrs = (instregex "VST1d(8|16|32|64)(Qwb|QPseudoWB)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2834 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1S_1V];
  dag Instrs = (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2835 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_3cyc_1S_1V_1I];
  dag Instrs = (instregex "VST1LNd(8|16|32)_UPD", "VST1LNq(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2836 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1S_1V];
  dag Instrs = (instregex "VST2(d|b)(8|16|32)$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2837 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_3cyc_1S_1V_1I];
  dag Instrs = (instregex "VST2(b|d)(8|16|32)wb");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2838 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1S_1V];
  dag Instrs = (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2839 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_4cyc_1S_1V_1I];
  dag Instrs = (instregex "VST2q(8|16|32)wb", "VST2q(8|16|32)PseudoWB");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_284 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_192];
  string NAME = ?;
}
def anonymous_2840 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1S_1V];
  dag Instrs = (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2841 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_3cyc_1S_1V_1I];
  dag Instrs = (instregex "VST2LN(d|q)(8|16|32)_UPD", "VST2LN(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2842 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1S_1V];
  dag Instrs = (instregex "VST3(d|q)(8|16|32)$", "VST3(d|q)(8|16|32)(oddP|P)seudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2843 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_3cyc_1S_1V_1I];
  dag Instrs = (instregex "VST3(d|q)(8|16|32)_UPD", "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2844 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1S_1V];
  dag Instrs = (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2845 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_3cyc_1S_1V_1I];
  dag Instrs = (instregex "VST3LN(d|q)(8|16|32)_UPD", "VST3LN(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2846 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_4cyc_1S_1V];
  dag Instrs = (instregex "VST4(d|q)(8|16|32)$", "VST4(d|q)(8|16|32)(oddP|P)seudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2847 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_4cyc_1S_1V_1I];
  dag Instrs = (instregex "VST4(d|q)(8|16|32)_UPD", "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2848 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1S_1V];
  dag Instrs = (instregex "VST4LN(d|q)(8|16|32)$", "VST4LN(d|q)(8|16|32)Pseudo$");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2849 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57WrBackOne, A57Write_3cyc_1S_1V_1I];
  dag Instrs = (instregex "VST4LN(d|q)(8|16|32)_UPD", "VST4LN(d|q)(8|16|32)Pseudo_UPD");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_285 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_205];
  string NAME = ?;
}
def anonymous_2850 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1W];
  dag Instrs = (instregex "^AES");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2851 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1W];
  dag Instrs = (instregex "^VMULLp64");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2852 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_6cyc_2V];
  dag Instrs = (instregex "^SHA1SU0");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2853 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1W];
  dag Instrs = (instregex "^SHA1(H|SU1)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2854 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_6cyc_2W];
  dag Instrs = (instregex "^SHA1[CMP]");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2855 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1W];
  dag Instrs = (instregex "^SHA256SU0");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2856 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_6cyc_2W];
  dag Instrs = (instregex "^SHA256(H|H2|SU1)");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2857 {	// InstRW
  list<SchedReadWrite> OperandReadWrites = [A57Write_3cyc_1W];
  dag Instrs = (instregex "^(t2)?CRC32");
  SchedMachineModel SchedModel = CortexA57Model;
  bit Unsupported = 0;
  string NAME = ?;
}
def anonymous_2858 {	// ProcWriteResources WriteRes
  list<ProcResourceKind> ProcResources = [];
  list<int> ResourceCycles = [];
  int Latency = 0;
  int NumMicroOps = 0;
  bit BeginGroup = 0;
  bit EndGroup = 0;
  bit Unsupported = 0;
  bit SingleIssue = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedWrite WriteType = WriteNoop;
  string NAME = ?;
}
def anonymous_2859 {	// SchedAlias
  SchedReadWrite MatchRW = WriteALU;
  SchedReadWrite AliasRW = A57Write_1cyc_1I;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_286 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_203];
  string NAME = ?;
}
def anonymous_2860 {	// SchedAlias
  SchedReadWrite MatchRW = WriteBr;
  SchedReadWrite AliasRW = A57Write_1cyc_1B;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2861 {	// SchedAlias
  SchedReadWrite MatchRW = WriteBrL;
  SchedReadWrite AliasRW = A57Write_1cyc_1B_1I;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2862 {	// SchedAlias
  SchedReadWrite MatchRW = WriteBrTbl;
  SchedReadWrite AliasRW = A57Write_1cyc_1B_1I;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2863 {	// SchedAlias
  SchedReadWrite MatchRW = WritePreLd;
  SchedReadWrite AliasRW = A57Write_4cyc_1L;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2864 {	// SchedAlias
  SchedReadWrite MatchRW = WriteLd;
  SchedReadWrite AliasRW = A57Write_4cyc_1L;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2865 {	// SchedAlias
  SchedReadWrite MatchRW = WriteST;
  SchedReadWrite AliasRW = A57Write_1cyc_1S;
  SchedMachineModel SchedModel = CortexA57Model;
  string NAME = ?;
}
def anonymous_2866 {	// ProcReadAdvance ReadAdvance
  int Cycles = 0;
  list<SchedWrite> ValidWrites = [];
  bit Unsupported = 0;
  SchedMachineModel SchedModel = CortexA57Model;
  SchedRead ReadType = ReadALU;
  string NAME = ?;
}
def anonymous_2867 {	// Processor ProcessorModel
  string Name = "generic";
  SchedMachineModel SchedModel = CortexA8Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [];
  string NAME = ?;
}
def anonymous_2868 {	// Processor ProcNoItin
  string Name = "arm8";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4];
  string NAME = ?;
}
def anonymous_2869 {	// Processor ProcNoItin
  string Name = "arm810";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4];
  string NAME = ?;
}
def anonymous_287 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_203];
  string NAME = ?;
}
def anonymous_2870 {	// Processor ProcNoItin
  string Name = "strongarm";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4];
  string NAME = ?;
}
def anonymous_2871 {	// Processor ProcNoItin
  string Name = "strongarm110";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4];
  string NAME = ?;
}
def anonymous_2872 {	// Processor ProcNoItin
  string Name = "strongarm1100";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4];
  string NAME = ?;
}
def anonymous_2873 {	// Processor ProcNoItin
  string Name = "strongarm1110";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4];
  string NAME = ?;
}
def anonymous_2874 {	// Processor ProcNoItin
  string Name = "arm7tdmi";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2875 {	// Processor ProcNoItin
  string Name = "arm7tdmi-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2876 {	// Processor ProcNoItin
  string Name = "arm710t";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2877 {	// Processor ProcNoItin
  string Name = "arm720t";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2878 {	// Processor ProcNoItin
  string Name = "arm9";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2879 {	// Processor ProcNoItin
  string Name = "arm9tdmi";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_288 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_205];
  string NAME = ?;
}
def anonymous_2880 {	// Processor ProcNoItin
  string Name = "arm920";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2881 {	// Processor ProcNoItin
  string Name = "arm920t";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2882 {	// Processor ProcNoItin
  string Name = "arm922t";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2883 {	// Processor ProcNoItin
  string Name = "arm940t";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2884 {	// Processor ProcNoItin
  string Name = "ep9312";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv4t];
  string NAME = ?;
}
def anonymous_2885 {	// Processor ProcNoItin
  string Name = "arm10tdmi";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5t];
  string NAME = ?;
}
def anonymous_2886 {	// Processor ProcNoItin
  string Name = "arm1020t";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5t];
  string NAME = ?;
}
def anonymous_2887 {	// Processor ProcNoItin
  string Name = "arm9e";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_2888 {	// Processor ProcNoItin
  string Name = "arm926ej-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_2889 {	// Processor ProcNoItin
  string Name = "arm946e-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_289 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_203];
  string NAME = ?;
}
def anonymous_2890 {	// Processor ProcNoItin
  string Name = "arm966e-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_2891 {	// Processor ProcNoItin
  string Name = "arm968e-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_2892 {	// Processor ProcNoItin
  string Name = "arm10e";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_2893 {	// Processor ProcNoItin
  string Name = "arm1020e";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_2894 {	// Processor ProcNoItin
  string Name = "arm1022e";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_2895 {	// Processor ProcNoItin
  string Name = "xscale";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_2896 {	// Processor ProcNoItin
  string Name = "iwmmxt";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv5te];
  string NAME = ?;
}
def anonymous_2897 {	// Processor
  string Name = "arm1136j-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6];
  string NAME = ?;
}
def anonymous_2898 {	// Processor
  string Name = "arm1136jf-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6, FeatureVFP2, FeatureHasSlowFPVMLx];
  string NAME = ?;
}
def anonymous_2899 {	// Processor
  string Name = "cortex-m0";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6m];
  string NAME = ?;
}
def anonymous_29 {	// LLVMType LLVMQualPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = llvm_float_ty;
  int AddrSpace = 3;
  string NAME = ?;
}
def anonymous_290 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_205];
  string NAME = ?;
}
def anonymous_2900 {	// Processor
  string Name = "cortex-m0plus";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6m];
  string NAME = ?;
}
def anonymous_2901 {	// Processor
  string Name = "cortex-m1";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6m];
  string NAME = ?;
}
def anonymous_2902 {	// Processor
  string Name = "sc000";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6m];
  string NAME = ?;
}
def anonymous_2903 {	// Processor
  string Name = "arm1176j-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6kz];
  string NAME = ?;
}
def anonymous_2904 {	// Processor
  string Name = "arm1176jz-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6kz];
  string NAME = ?;
}
def anonymous_2905 {	// Processor
  string Name = "arm1176jzf-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6kz, FeatureVFP2, FeatureHasSlowFPVMLx];
  string NAME = ?;
}
def anonymous_2906 {	// Processor
  string Name = "mpcorenovfp";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6k];
  string NAME = ?;
}
def anonymous_2907 {	// Processor
  string Name = "mpcore";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6k, FeatureVFP2, FeatureHasSlowFPVMLx];
  string NAME = ?;
}
def anonymous_2908 {	// Processor
  string Name = "arm1156t2-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6t2];
  string NAME = ?;
}
def anonymous_2909 {	// Processor
  string Name = "arm1156t2f-s";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = ARMV6Itineraries;
  list<SubtargetFeature> Features = [ARMv6t2, FeatureVFP2, FeatureHasSlowFPVMLx];
  string NAME = ?;
}
def anonymous_291 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_203];
  string NAME = ?;
}
def anonymous_2910 {	// Processor ProcessorModel
  string Name = "cortex-a5";
  SchedMachineModel SchedModel = CortexA8Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7a, ProcA5, FeatureHasRetAddrStack, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, FeatureVMLxForwarding, FeatureMP, FeatureVFP4];
  string NAME = ?;
}
def anonymous_2911 {	// Processor ProcessorModel
  string Name = "cortex-a7";
  SchedMachineModel SchedModel = CortexA8Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7a, ProcA7, FeatureHasRetAddrStack, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasVMLxHazards, FeatureHasSlowFPVMLx, FeatureVMLxForwarding, FeatureMP, FeatureVFP4, FeatureVirtualization];
  string NAME = ?;
}
def anonymous_2912 {	// Processor ProcessorModel
  string Name = "cortex-a8";
  SchedMachineModel SchedModel = CortexA8Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7a, ProcA8, FeatureHasRetAddrStack, FeatureNonpipelinedVFP, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasVMLxHazards, FeatureHasSlowFPVMLx, FeatureVMLxForwarding];
  string NAME = ?;
}
def anonymous_2913 {	// Processor ProcessorModel
  string Name = "cortex-a9";
  SchedMachineModel SchedModel = CortexA9Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7a, ProcA9, FeatureHasRetAddrStack, FeatureTrustZone, FeatureHasVMLxHazards, FeatureVMLxForwarding, FeatureFP16, FeatureAvoidPartialCPSR, FeatureExpandMLx, FeaturePreferVMOVSR, FeatureMuxedUnits, FeatureNEONForFPMovs, FeatureCheckVLDnAlign, FeatureMP];
  string NAME = ?;
}
def anonymous_2914 {	// Processor ProcessorModel
  string Name = "cortex-a12";
  SchedMachineModel SchedModel = CortexA9Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7a, ProcA12, FeatureHasRetAddrStack, FeatureTrustZone, FeatureVMLxForwarding, FeatureVFP4, FeatureAvoidPartialCPSR, FeatureVirtualization, FeatureMP];
  string NAME = ?;
}
def anonymous_2915 {	// Processor ProcessorModel
  string Name = "cortex-a15";
  SchedMachineModel SchedModel = CortexA9Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7a, ProcA15, FeatureDontWidenVMOVS, FeatureHasRetAddrStack, FeatureMuxedUnits, FeatureTrustZone, FeatureVFP4, FeatureMP, FeatureCheckVLDnAlign, FeatureAvoidPartialCPSR, FeatureVirtualization];
  string NAME = ?;
}
def anonymous_2916 {	// Processor ProcessorModel
  string Name = "cortex-a17";
  SchedMachineModel SchedModel = CortexA9Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7a, ProcA17, FeatureHasRetAddrStack, FeatureTrustZone, FeatureMP, FeatureVMLxForwarding, FeatureVFP4, FeatureAvoidPartialCPSR, FeatureVirtualization];
  string NAME = ?;
}
def anonymous_2917 {	// Processor ProcessorModel
  string Name = "krait";
  SchedMachineModel SchedModel = CortexA9Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7a, ProcKrait, FeatureHasRetAddrStack, FeatureMuxedUnits, FeatureCheckVLDnAlign, FeatureVMLxForwarding, FeatureFP16, FeatureAvoidPartialCPSR, FeatureVFP4, FeatureHWDivThumb, FeatureHWDivARM];
  string NAME = ?;
}
def anonymous_2918 {	// Processor ProcessorModel
  string Name = "swift";
  SchedMachineModel SchedModel = SwiftModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx, FeatureHasVMLxHazards, FeatureProfUnpredicate, FeaturePrefISHSTBarrier, FeatureSlowOddRegister, FeatureSlowLoadDSubreg, FeatureSlowVGETLNi32, FeatureSlowVDUP32, FeatureUseMISched, FeatureNoPostRASched];
  string NAME = ?;
}
def anonymous_2919 {	// Processor ProcessorModel
  string Name = "cortex-r4";
  SchedMachineModel SchedModel = CortexA8Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7r, ProcR4, FeatureHasRetAddrStack, FeatureAvoidPartialCPSR];
  string NAME = ?;
}
def anonymous_292 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_205];
  string NAME = ?;
}
def anonymous_2920 {	// Processor ProcessorModel
  string Name = "cortex-r4f";
  SchedMachineModel SchedModel = CortexA8Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7r, ProcR4, FeatureHasRetAddrStack, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, FeatureVFP3, FeatureD16, FeatureAvoidPartialCPSR];
  string NAME = ?;
}
def anonymous_2921 {	// Processor ProcessorModel
  string Name = "cortex-r5";
  SchedMachineModel SchedModel = CortexA8Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7r, ProcR5, FeatureHasRetAddrStack, FeatureVFP3, FeatureD16, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR];
  string NAME = ?;
}
def anonymous_2922 {	// Processor ProcessorModel
  string Name = "cortex-r7";
  SchedMachineModel SchedModel = CortexA8Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7r, ProcR7, FeatureHasRetAddrStack, FeatureVFP3, FeatureD16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR];
  string NAME = ?;
}
def anonymous_2923 {	// Processor ProcessorModel
  string Name = "cortex-r8";
  SchedMachineModel SchedModel = CortexA8Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7r, FeatureHasRetAddrStack, FeatureVFP3, FeatureD16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR];
  string NAME = ?;
}
def anonymous_2924 {	// Processor ProcessorModel
  string Name = "cortex-m3";
  SchedMachineModel SchedModel = CortexM3Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7m, ProcM3, FeatureHasNoBranchPredictor];
  string NAME = ?;
}
def anonymous_2925 {	// Processor ProcessorModel
  string Name = "sc300";
  SchedMachineModel SchedModel = CortexM3Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7m, ProcM3, FeatureHasNoBranchPredictor];
  string NAME = ?;
}
def anonymous_2926 {	// Processor ProcessorModel
  string Name = "cortex-m4";
  SchedMachineModel SchedModel = CortexM3Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7em, FeatureVFP4, FeatureVFPOnlySP, FeatureD16, FeatureHasNoBranchPredictor];
  string NAME = ?;
}
def anonymous_2927 {	// Processor ProcNoItin
  string Name = "cortex-m7";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv7em, FeatureFPARMv8, FeatureD16];
  string NAME = ?;
}
def anonymous_2928 {	// Processor ProcNoItin
  string Name = "cortex-m23";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8mBaseline, FeatureNoMovt];
  string NAME = ?;
}
def anonymous_2929 {	// Processor ProcessorModel
  string Name = "cortex-m33";
  SchedMachineModel SchedModel = CortexM3Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8mMainline, FeatureDSP, FeatureFPARMv8, FeatureD16, FeatureVFPOnlySP, FeatureHasNoBranchPredictor];
  string NAME = ?;
}
def anonymous_293 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_203];
  string NAME = ?;
}
def anonymous_2930 {	// Processor ProcNoItin
  string Name = "cortex-a32";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def anonymous_2931 {	// Processor ProcNoItin
  string Name = "cortex-a35";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcA35, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def anonymous_2932 {	// Processor ProcNoItin
  string Name = "cortex-a53";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcA53, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFPAO];
  string NAME = ?;
}
def anonymous_2933 {	// Processor ProcNoItin
  string Name = "cortex-a55";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv82a, ProcA55, FeatureHWDivThumb, FeatureHWDivARM, FeatureDotProd];
  string NAME = ?;
}
def anonymous_2934 {	// Processor ProcessorModel
  string Name = "cortex-a57";
  SchedMachineModel SchedModel = CortexA57Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcA57, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFPAO, FeatureAvoidPartialCPSR, FeatureCheapPredicableCPSR];
  string NAME = ?;
}
def anonymous_2935 {	// Processor ProcNoItin
  string Name = "cortex-a72";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcA72, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def anonymous_2936 {	// Processor ProcNoItin
  string Name = "cortex-a73";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcA73, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def anonymous_2937 {	// Processor ProcNoItin
  string Name = "cortex-a75";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv82a, ProcA75, FeatureHWDivThumb, FeatureHWDivARM, FeatureDotProd];
  string NAME = ?;
}
def anonymous_2938 {	// Processor ProcessorModel
  string Name = "cyclone";
  SchedMachineModel SchedModel = SwiftModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx, FeatureCrypto, FeatureUseMISched, FeatureZCZeroing, FeatureNoPostRASched];
  string NAME = ?;
}
def anonymous_2939 {	// Processor ProcNoItin
  string Name = "exynos-m1";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def anonymous_294 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2940 {	// Processor ProcNoItin
  string Name = "exynos-m2";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def anonymous_2941 {	// Processor ProcNoItin
  string Name = "exynos-m3";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def anonymous_2942 {	// Processor ProcNoItin
  string Name = "kryo";
  SchedMachineModel SchedModel = NoSchedModel;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8a, ProcKryo, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC];
  string NAME = ?;
}
def anonymous_2943 {	// Processor ProcessorModel
  string Name = "cortex-r52";
  SchedMachineModel SchedModel = CortexR52Model;
  ProcessorItineraries ProcItin = NoItineraries;
  list<SubtargetFeature> Features = [ARMv8r, ProcR52, FeatureUseMISched, FeatureFPAO];
  string NAME = ?;
}
def anonymous_2944 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "apsr_g";
  bits<13> M1Encoding12 = { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bits<10> M2M3Encoding8 = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bits<12> Encoding = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  code Requires = [{ {ARM::FeatureDSP} }];
  string NAME = ?;
}
def anonymous_2945 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "apsr_nzcvqg";
  bits<13> M1Encoding12 = { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bits<10> M2M3Encoding8 = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  bits<12> Encoding = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  code Requires = [{ {ARM::FeatureDSP} }];
  string NAME = ?;
}
def anonymous_2946 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "iapsr_g";
  bits<13> M1Encoding12 = { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bits<10> M2M3Encoding8 = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bits<12> Encoding = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  code Requires = [{ {ARM::FeatureDSP} }];
  string NAME = ?;
}
def anonymous_2947 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "iapsr_nzcvqg";
  bits<13> M1Encoding12 = { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bits<10> M2M3Encoding8 = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  bits<12> Encoding = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  code Requires = [{ {ARM::FeatureDSP} }];
  string NAME = ?;
}
def anonymous_2948 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "eapsr_g";
  bits<13> M1Encoding12 = { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bits<10> M2M3Encoding8 = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bits<12> Encoding = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  code Requires = [{ {ARM::FeatureDSP} }];
  string NAME = ?;
}
def anonymous_2949 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "eapsr_nzcvqg";
  bits<13> M1Encoding12 = { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bits<10> M2M3Encoding8 = { 1, 1, 0, 0, 0, 0, 0, 0, 1, 0 };
  bits<12> Encoding = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  code Requires = [{ {ARM::FeatureDSP} }];
  string NAME = ?;
}
def anonymous_295 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2950 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "xpsr_g";
  bits<13> M1Encoding12 = { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bits<10> M2M3Encoding8 = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bits<12> Encoding = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  code Requires = [{ {ARM::FeatureDSP} }];
  string NAME = ?;
}
def anonymous_2951 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "xpsr_nzcvqg";
  bits<13> M1Encoding12 = { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bits<10> M2M3Encoding8 = { 1, 1, 0, 0, 0, 0, 0, 0, 1, 1 };
  bits<12> Encoding = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  code Requires = [{ {ARM::FeatureDSP} }];
  string NAME = ?;
}
def anonymous_2952 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "apsr";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2953 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "apsr_nzcvq";
  bits<13> M1Encoding12 = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bits<10> M2M3Encoding8 = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2954 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "iapsr";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2955 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "iapsr_nzcvq";
  bits<13> M1Encoding12 = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bits<10> M2M3Encoding8 = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2956 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "eapsr";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 0, 0, 1, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2957 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "eapsr_nzcvq";
  bits<13> M1Encoding12 = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bits<10> M2M3Encoding8 = { 1, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2958 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "xpsr";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 0, 0, 1, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2959 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "xpsr_nzcvq";
  bits<13> M1Encoding12 = { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bits<10> M2M3Encoding8 = { 1, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_296 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2960 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "ipsr";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 0, 1, 0, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2961 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "epsr";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 0, 1, 1, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2962 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "iepsr";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 0, 1, 1, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2963 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "msp";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 1, 0, 0, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2964 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "psp";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 1, 0, 0, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2965 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "msplim";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 1, 0, 1, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0 };
  code Requires = [{ {ARM::HasV8MBaselineOps} }];
  string NAME = ?;
}
def anonymous_2966 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "psplim";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 0, 1, 0, 1, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1 };
  code Requires = [{ {ARM::HasV8MBaselineOps} }];
  string NAME = ?;
}
def anonymous_2967 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "primask";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 1, 0, 0, 0, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2968 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "basepri";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 1, 0, 0, 0, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1 };
  code Requires = [{ {ARM::HasV7Ops} }];
  string NAME = ?;
}
def anonymous_2969 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "basepri_max";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 1, 0, 0, 1, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0 };
  code Requires = [{ {ARM::HasV7Ops} }];
  string NAME = ?;
}
def anonymous_297 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2970 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "faultmask";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 1, 0, 0, 1, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1 };
  code Requires = [{ {ARM::HasV7Ops} }];
  string NAME = ?;
}
def anonymous_2971 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "control";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 0, 0, 0, 1, 0, 1, 0, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2972 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "msp_ns";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 1, 0, 0, 0, 1, 0, 0, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 };
  code Requires = [{ {ARM::Feature8MSecExt} }];
  string NAME = ?;
}
def anonymous_2973 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "psp_ns";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 1, 0, 0, 0, 1, 0, 0, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1 };
  code Requires = [{ {ARM::Feature8MSecExt} }];
  string NAME = ?;
}
def anonymous_2974 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "msplim_ns";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 1, 0, 0, 0, 1, 0, 1, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0 };
  code Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }];
  string NAME = ?;
}
def anonymous_2975 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "psplim_ns";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 1, 0, 0, 0, 1, 0, 1, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  code Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }];
  string NAME = ?;
}
def anonymous_2976 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "primask_ns";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 1, 0, 0, 1, 0, 0, 0, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0 };
  code Requires = [{ {} }];
  string NAME = ?;
}
def anonymous_2977 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "basepri_ns";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 1, 0, 0, 1, 0, 0, 0, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 1 };
  code Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }];
  string NAME = ?;
}
def anonymous_2978 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "faultmask_ns";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 1 };
  bits<10> M2M3Encoding8 = { 0, 1, 1, 0, 0, 1, 0, 0, 1, 1 };
  bits<12> Encoding = { 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 1 };
  code Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }];
  string NAME = ?;
}
def anonymous_2979 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "control_ns";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 1, 0, 0, 1, 0, 1, 0, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0 };
  code Requires = [{ {ARM::Feature8MSecExt} }];
  string NAME = ?;
}
def anonymous_298 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_2980 {	// SearchableTable MClassSysReg
  list<string> SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = "Encoding";
  string Name = "sp_ns";
  bits<13> M1Encoding12 = { 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0 };
  bits<10> M2M3Encoding8 = { 0, 1, 1, 0, 0, 1, 1, 0, 0, 0 };
  bits<12> Encoding = { 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0 };
  code Requires = [{ {ARM::Feature8MSecExt} }];
  string NAME = ?;
}
def anonymous_2981 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r8_usr";
  bits<8> Encoding = { 0, 0, 0, 0, 0, 0, 0, 0 };
  string NAME = ?;
}
def anonymous_2982 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r9_usr";
  bits<8> Encoding = { 0, 0, 0, 0, 0, 0, 0, 1 };
  string NAME = ?;
}
def anonymous_2983 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r10_usr";
  bits<8> Encoding = { 0, 0, 0, 0, 0, 0, 1, 0 };
  string NAME = ?;
}
def anonymous_2984 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r11_usr";
  bits<8> Encoding = { 0, 0, 0, 0, 0, 0, 1, 1 };
  string NAME = ?;
}
def anonymous_2985 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r12_usr";
  bits<8> Encoding = { 0, 0, 0, 0, 0, 1, 0, 0 };
  string NAME = ?;
}
def anonymous_2986 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "sp_usr";
  bits<8> Encoding = { 0, 0, 0, 0, 0, 1, 0, 1 };
  string NAME = ?;
}
def anonymous_2987 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "lr_usr";
  bits<8> Encoding = { 0, 0, 0, 0, 0, 1, 1, 0 };
  string NAME = ?;
}
def anonymous_2988 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r8_fiq";
  bits<8> Encoding = { 0, 0, 0, 0, 1, 0, 0, 0 };
  string NAME = ?;
}
def anonymous_2989 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r9_fiq";
  bits<8> Encoding = { 0, 0, 0, 0, 1, 0, 0, 1 };
  string NAME = ?;
}
def anonymous_299 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  string NAME = ?;
}
def anonymous_2990 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r10_fiq";
  bits<8> Encoding = { 0, 0, 0, 0, 1, 0, 1, 0 };
  string NAME = ?;
}
def anonymous_2991 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r11_fiq";
  bits<8> Encoding = { 0, 0, 0, 0, 1, 0, 1, 1 };
  string NAME = ?;
}
def anonymous_2992 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "r12_fiq";
  bits<8> Encoding = { 0, 0, 0, 0, 1, 1, 0, 0 };
  string NAME = ?;
}
def anonymous_2993 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "sp_fiq";
  bits<8> Encoding = { 0, 0, 0, 0, 1, 1, 0, 1 };
  string NAME = ?;
}
def anonymous_2994 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "lr_fiq";
  bits<8> Encoding = { 0, 0, 0, 0, 1, 1, 1, 0 };
  string NAME = ?;
}
def anonymous_2995 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "lr_irq";
  bits<8> Encoding = { 0, 0, 0, 1, 0, 0, 0, 0 };
  string NAME = ?;
}
def anonymous_2996 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "sp_irq";
  bits<8> Encoding = { 0, 0, 0, 1, 0, 0, 0, 1 };
  string NAME = ?;
}
def anonymous_2997 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "lr_svc";
  bits<8> Encoding = { 0, 0, 0, 1, 0, 0, 1, 0 };
  string NAME = ?;
}
def anonymous_2998 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "sp_svc";
  bits<8> Encoding = { 0, 0, 0, 1, 0, 0, 1, 1 };
  string NAME = ?;
}
def anonymous_2999 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "lr_abt";
  bits<8> Encoding = { 0, 0, 0, 1, 0, 1, 0, 0 };
  string NAME = ?;
}
def anonymous_3 {	// IntrinsicProperty NoCapture
  int ArgNo = 0;
  string NAME = ?;
}
def anonymous_30 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_31];
  string NAME = ?;
}
def anonymous_300 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_219, anonymous_302];
  string NAME = ?;
}
def anonymous_3000 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "sp_abt";
  bits<8> Encoding = { 0, 0, 0, 1, 0, 1, 0, 1 };
  string NAME = ?;
}
def anonymous_3001 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "lr_und";
  bits<8> Encoding = { 0, 0, 0, 1, 0, 1, 1, 0 };
  string NAME = ?;
}
def anonymous_3002 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "sp_und";
  bits<8> Encoding = { 0, 0, 0, 1, 0, 1, 1, 1 };
  string NAME = ?;
}
def anonymous_3003 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "lr_mon";
  bits<8> Encoding = { 0, 0, 0, 1, 1, 1, 0, 0 };
  string NAME = ?;
}
def anonymous_3004 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "sp_mon";
  bits<8> Encoding = { 0, 0, 0, 1, 1, 1, 0, 1 };
  string NAME = ?;
}
def anonymous_3005 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "elr_hyp";
  bits<8> Encoding = { 0, 0, 0, 1, 1, 1, 1, 0 };
  string NAME = ?;
}
def anonymous_3006 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "sp_hyp";
  bits<8> Encoding = { 0, 0, 0, 1, 1, 1, 1, 1 };
  string NAME = ?;
}
def anonymous_3007 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "spsr_fiq";
  bits<8> Encoding = { 0, 0, 1, 0, 1, 1, 1, 0 };
  string NAME = ?;
}
def anonymous_3008 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "spsr_irq";
  bits<8> Encoding = { 0, 0, 1, 1, 0, 0, 0, 0 };
  string NAME = ?;
}
def anonymous_3009 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "spsr_svc";
  bits<8> Encoding = { 0, 0, 1, 1, 0, 0, 1, 0 };
  string NAME = ?;
}
def anonymous_301 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "dtdh";
  string NAME = ?;
}
def anonymous_3010 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "spsr_abt";
  bits<8> Encoding = { 0, 0, 1, 1, 0, 1, 0, 0 };
  string NAME = ?;
}
def anonymous_3011 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "spsr_und";
  bits<8> Encoding = { 0, 0, 1, 1, 0, 1, 1, 0 };
  string NAME = ?;
}
def anonymous_3012 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "spsr_mon";
  bits<8> Encoding = { 0, 0, 1, 1, 1, 1, 0, 0 };
  string NAME = ?;
}
def anonymous_3013 {	// SearchableTable BankedReg
  list<string> SearchableFields = ["Name", "Encoding"];
  string EnumNameField = "Name";
  string EnumValueField = ?;
  string Name = "spsr_hyp";
  bits<8> Encoding = { 0, 0, 1, 1, 1, 1, 1, 0 };
  string NAME = ?;
}
def anonymous_3014 {	// CCAction CCPassByVal
  int Size = 4;
  int Align = 4;
  string NAME = ?;
}
def anonymous_3015 {	// CCAction CCPredicateAction CCIf CCIfByVal
  CCAction SubAction = anonymous_3014;
  string Predicate = "ArgFlags.isByVal()";
  string NAME = ?;
}
def anonymous_3016 {	// CCAction CCPromoteToType
  ValueType DestTy = i32;
  string NAME = ?;
}
def anonymous_3017 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3016;
  list<ValueType> VTs = [i1, i8, i16];
  string NAME = ?;
}
def anonymous_3018 {	// CCAction CCAssignToReg
  list<Register> RegList = [R10];
  string NAME = ?;
}
def anonymous_3019 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3018;
  list<ValueType> VTs = [i32];
  string NAME = ?;
}
def anonymous_302 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "dtdv";
  string NAME = ?;
}
def anonymous_3020 {	// CCAction CCPredicateAction CCIf CCIfSwiftSelf
  CCAction SubAction = anonymous_3019;
  string Predicate = "ArgFlags.isSwiftSelf()";
  string NAME = ?;
}
def anonymous_3021 {	// CCAction CCAssignToReg
  list<Register> RegList = [R8];
  string NAME = ?;
}
def anonymous_3022 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3021;
  list<ValueType> VTs = [i32];
  string NAME = ?;
}
def anonymous_3023 {	// CCAction CCPredicateAction CCIf CCIfSwiftError
  CCAction SubAction = anonymous_3022;
  string Predicate = "ArgFlags.isSwiftError()";
  string NAME = ?;
}
def anonymous_3024 {	// CCAction CCBitConvertToType
  ValueType DestTy = f64;
  string NAME = ?;
}
def anonymous_3025 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3024;
  list<ValueType> VTs = [v1i64, v2i32, v4i16, v8i8, v2f32];
  string NAME = ?;
}
def anonymous_3026 {	// CCAction CCBitConvertToType
  ValueType DestTy = v2f64;
  string NAME = ?;
}
def anonymous_3027 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3026;
  list<ValueType> VTs = [v2i64, v4i32, v8i16, v16i8, v4f32];
  string NAME = ?;
}
def anonymous_3028 {	// CCAction CCCustom
  string FuncName = "CC_ARM_APCS_Custom_f64";
  string NAME = ?;
}
def anonymous_3029 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3028;
  list<ValueType> VTs = [f64, v2f64];
  string NAME = ?;
}
def anonymous_303 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "dtdh";
  string NAME = ?;
}
def anonymous_3030 {	// CCAction CCBitConvertToType
  ValueType DestTy = i32;
  string NAME = ?;
}
def anonymous_3031 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3030;
  list<ValueType> VTs = [f32];
  string NAME = ?;
}
def anonymous_3032 {	// CCAction CCAssignToReg
  list<Register> RegList = [R0, R1, R2, R3];
  string NAME = ?;
}
def anonymous_3033 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3032;
  list<ValueType> VTs = [i32];
  string NAME = ?;
}
def anonymous_3034 {	// CCAction CCAssignToStack
  int Size = 4;
  int Align = 4;
  string NAME = ?;
}
def anonymous_3035 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3034;
  list<ValueType> VTs = [i32];
  string NAME = ?;
}
def anonymous_3036 {	// CCAction CCAssignToStack
  int Size = 8;
  int Align = 4;
  string NAME = ?;
}
def anonymous_3037 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3036;
  list<ValueType> VTs = [f64];
  string NAME = ?;
}
def anonymous_3038 {	// CCAction CCAssignToStack
  int Size = 16;
  int Align = 4;
  string NAME = ?;
}
def anonymous_3039 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3038;
  list<ValueType> VTs = [v2f64];
  string NAME = ?;
}
def anonymous_304 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "dtdv";
  string NAME = ?;
}
def anonymous_3040 {	// CCAction CCCustom
  string FuncName = "RetCC_ARM_APCS_Custom_f64";
  string NAME = ?;
}
def anonymous_3041 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3040;
  list<ValueType> VTs = [f64, v2f64];
  string NAME = ?;
}
def anonymous_3042 {	// CCAction CCAssignToRegWithShadow
  list<Register> RegList = [R0, R2];
  list<Register> ShadowRegList = [R1, R3];
  string NAME = ?;
}
def anonymous_3043 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3042;
  list<ValueType> VTs = [i64];
  string NAME = ?;
}
def anonymous_3044 {	// CCAction CCAssignToReg
  list<Register> RegList = [Q0, Q1, Q2, Q3];
  string NAME = ?;
}
def anonymous_3045 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3044;
  list<ValueType> VTs = [v2f64];
  string NAME = ?;
}
def anonymous_3046 {	// CCAction CCAssignToReg
  list<Register> RegList = [D0, D1, D2, D3, D4, D5, D6, D7];
  string NAME = ?;
}
def anonymous_3047 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3046;
  list<ValueType> VTs = [f64];
  string NAME = ?;
}
def anonymous_3048 {	// CCAction CCAssignToReg
  list<Register> RegList = [S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15];
  string NAME = ?;
}
def anonymous_3049 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3048;
  list<ValueType> VTs = [f32];
  string NAME = ?;
}
def anonymous_305 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "dtdh";
  string NAME = ?;
}
def anonymous_3050 {	// CCAction CCAssignToStackWithShadow
  int Size = 4;
  int Align = 4;
  list<Register> ShadowRegList = [Q0, Q1, Q2, Q3];
  string NAME = ?;
}
def anonymous_3051 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3050;
  list<ValueType> VTs = [f32];
  string NAME = ?;
}
def anonymous_3052 {	// CCAction CCAssignToStackWithShadow
  int Size = 8;
  int Align = 4;
  list<Register> ShadowRegList = [Q0, Q1, Q2, Q3];
  string NAME = ?;
}
def anonymous_3053 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3052;
  list<ValueType> VTs = [f64];
  string NAME = ?;
}
def anonymous_3054 {	// CCAction CCAssignToStackWithShadow
  int Size = 16;
  int Align = 4;
  list<Register> ShadowRegList = [Q0, Q1, Q2, Q3];
  string NAME = ?;
}
def anonymous_3055 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3054;
  list<ValueType> VTs = [v2f64];
  string NAME = ?;
}
def anonymous_3056 {	// CCAction CCDelegateTo
  CallingConv CC = CC_ARM_APCS;
  string NAME = ?;
}
def anonymous_3057 {	// CCAction CCDelegateTo
  CallingConv CC = RetCC_ARM_APCS;
  string NAME = ?;
}
def anonymous_3058 {	// CCAction CCAssignToReg
  list<Register> RegList = [Q4, Q5];
  string NAME = ?;
}
def anonymous_3059 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3058;
  list<ValueType> VTs = [v2f64];
  string NAME = ?;
}
def anonymous_306 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "dtdv";
  string NAME = ?;
}
def anonymous_3060 {	// CCAction CCAssignToReg
  list<Register> RegList = [D8, D9, D10, D11];
  string NAME = ?;
}
def anonymous_3061 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3060;
  list<ValueType> VTs = [f64];
  string NAME = ?;
}
def anonymous_3062 {	// CCAction CCAssignToReg
  list<Register> RegList = [S16, S17, S18, S19, S20, S21, S22, S23];
  string NAME = ?;
}
def anonymous_3063 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3062;
  list<ValueType> VTs = [f32];
  string NAME = ?;
}
def anonymous_3064 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3016;
  list<ValueType> VTs = [i8, i16];
  string NAME = ?;
}
def anonymous_3065 {	// CCAction CCAssignToReg
  list<Register> RegList = [R4, R5, R6, R7, R8, R9, R10, R11];
  string NAME = ?;
}
def anonymous_3066 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3065;
  list<ValueType> VTs = [i32];
  string NAME = ?;
}
def anonymous_3067 {	// CCAction CCAssignToRegWithShadow
  list<Register> RegList = [R0, R2];
  list<Register> ShadowRegList = [R0, R1];
  string NAME = ?;
}
def anonymous_3068 {	// CCAction CCPredicateAction CCIf CCIfAlign
  CCAction SubAction = anonymous_3067;
  string Predicate = "ArgFlags.getOrigAlign() == 8";
  string NAME = ?;
}
def anonymous_3069 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3068;
  list<ValueType> VTs = [i32];
  string NAME = ?;
}
def anonymous_307 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_3070 {	// CCAction CCPredicateAction CCIf
  CCAction SubAction = anonymous_3032;
  string Predicate = "ArgFlags.getOrigAlign() != 8";
  string NAME = ?;
}
def anonymous_3071 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3070;
  list<ValueType> VTs = [i32];
  string NAME = ?;
}
def anonymous_3072 {	// CCAction CCAssignToStackWithShadow
  int Size = 4;
  int Align = 8;
  list<Register> ShadowRegList = [R0, R1, R2, R3];
  string NAME = ?;
}
def anonymous_3073 {	// CCAction CCPredicateAction CCIf CCIfAlign
  CCAction SubAction = anonymous_3072;
  string Predicate = "ArgFlags.getOrigAlign() == 8";
  string NAME = ?;
}
def anonymous_3074 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3073;
  list<ValueType> VTs = [i32];
  string NAME = ?;
}
def anonymous_3075 {	// CCAction CCAssignToStackWithShadow
  int Size = 4;
  int Align = 4;
  list<Register> ShadowRegList = [R0, R1, R2, R3];
  string NAME = ?;
}
def anonymous_3076 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3075;
  list<ValueType> VTs = [i32];
  string NAME = ?;
}
def anonymous_3077 {	// CCAction CCAssignToStackWithShadow
  int Size = 8;
  int Align = 8;
  list<Register> ShadowRegList = [Q0, Q1, Q2, Q3];
  string NAME = ?;
}
def anonymous_3078 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3077;
  list<ValueType> VTs = [f64];
  string NAME = ?;
}
def anonymous_3079 {	// CCAction CCAssignToStackWithShadow
  int Size = 16;
  int Align = 16;
  list<Register> ShadowRegList = [Q0, Q1, Q2, Q3];
  string NAME = ?;
}
def anonymous_308 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  string NAME = ?;
}
def anonymous_3080 {	// CCAction CCPredicateAction CCIf CCIfAlign
  CCAction SubAction = anonymous_3079;
  string Predicate = "ArgFlags.getOrigAlign() == 16";
  string NAME = ?;
}
def anonymous_3081 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3080;
  list<ValueType> VTs = [v2f64];
  string NAME = ?;
}
def anonymous_3082 {	// CCAction CCAssignToStackWithShadow
  int Size = 16;
  int Align = 8;
  list<Register> ShadowRegList = [Q0, Q1, Q2, Q3];
  string NAME = ?;
}
def anonymous_3083 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3082;
  list<ValueType> VTs = [v2f64];
  string NAME = ?;
}
def anonymous_3084 {	// CCAction CCAssignToReg
  list<Register> RegList = [R12];
  string NAME = ?;
}
def anonymous_3085 {	// CCAction CCPredicateAction CCIf CCIfNest
  CCAction SubAction = anonymous_3084;
  string Predicate = "ArgFlags.isNest()";
  string NAME = ?;
}
def anonymous_3086 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3024;
  list<ValueType> VTs = [v1i64, v2i32, v4i16, v4f16, v8i8, v2f32];
  string NAME = ?;
}
def anonymous_3087 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3026;
  list<ValueType> VTs = [v2i64, v4i32, v8i16, v8f16, v16i8, v4f32];
  string NAME = ?;
}
def anonymous_3088 {	// CCAction CCCustom
  string FuncName = "CC_ARM_AAPCS_Custom_f64";
  string NAME = ?;
}
def anonymous_3089 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3088;
  list<ValueType> VTs = [f64, v2f64];
  string NAME = ?;
}
def anonymous_309 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_3090 {	// CCAction CCDelegateTo
  CallingConv CC = CC_ARM_AAPCS_Common;
  string NAME = ?;
}
def anonymous_3091 {	// CCAction CCCustom
  string FuncName = "RetCC_ARM_AAPCS_Custom_f64";
  string NAME = ?;
}
def anonymous_3092 {	// CCAction CCPredicateAction CCIfType
  CCAction SubAction = anonymous_3091;
  list<ValueType> VTs = [f64, v2f64];
  string NAME = ?;
}
def anonymous_3093 {	// CCAction CCDelegateTo
  CallingConv CC = RetCC_ARM_AAPCS_Common;
  string NAME = ?;
}
def anonymous_3094 {	// CCAction CCCustom
  string FuncName = "CC_ARM_AAPCS_Custom_Aggregate";
  string NAME = ?;
}
def anonymous_3095 {	// CCAction CCPredicateAction CCIf CCIfConsecutiveRegs
  CCAction SubAction = anonymous_3094;
  string Predicate = "ArgFlags.isInConsecutiveRegs()";
  string NAME = ?;
}
def anonymous_3096 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 0;
  ValueType VT = i32;
  string NAME = ?;
}
def anonymous_3097 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 1;
  ValueType VT = i32;
  string NAME = ?;
}
def anonymous_3098 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 2;
  ValueType VT = i32;
  string NAME = ?;
}
def anonymous_3099 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 3;
  ValueType VT = i32;
  string NAME = ?;
}
def anonymous_31 {	// AMDGPUArg
  LLVMType Type = llvm_anyfloat_ty;
  string Name = "s";
  string NAME = ?;
}
def anonymous_310 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  string NAME = ?;
}
def anonymous_3100 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 4;
  ValueType VT = i32;
  string NAME = ?;
}
def anonymous_3101 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 0;
  int OtherOperandNum = 5;
  string NAME = ?;
}
def anonymous_311 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_3110 {	// AsmOperandClass ComplexRotationOperand
  string Name = "ComplexRotationEven";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isComplexRotation<90, 0>";
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "complex rotation must be 0, 90, 180 or 270";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_3111 {	// AsmOperandClass ComplexRotationOperand
  string Name = "ComplexRotationOdd";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isComplexRotation<180, 90>";
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "complex rotation must be 90 or 270";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_3112 {	// TokenAlias
  string FromToken = ".s8";
  string ToToken = ".i8";
  string NAME = ?;
}
def anonymous_3113 {	// TokenAlias
  string FromToken = ".u8";
  string ToToken = ".i8";
  string NAME = ?;
}
def anonymous_3114 {	// TokenAlias
  string FromToken = ".s16";
  string ToToken = ".i16";
  string NAME = ?;
}
def anonymous_3115 {	// TokenAlias
  string FromToken = ".u16";
  string ToToken = ".i16";
  string NAME = ?;
}
def anonymous_3116 {	// TokenAlias
  string FromToken = ".s32";
  string ToToken = ".i32";
  string NAME = ?;
}
def anonymous_3117 {	// TokenAlias
  string FromToken = ".u32";
  string ToToken = ".i32";
  string NAME = ?;
}
def anonymous_3118 {	// TokenAlias
  string FromToken = ".s64";
  string ToToken = ".i64";
  string NAME = ?;
}
def anonymous_3119 {	// TokenAlias
  string FromToken = ".u64";
  string ToToken = ".i64";
  string NAME = ?;
}
def anonymous_312 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  string NAME = ?;
}
def anonymous_3120 {	// TokenAlias
  string FromToken = ".i8";
  string ToToken = ".8";
  string NAME = ?;
}
def anonymous_3121 {	// TokenAlias
  string FromToken = ".i16";
  string ToToken = ".16";
  string NAME = ?;
}
def anonymous_3122 {	// TokenAlias
  string FromToken = ".i32";
  string ToToken = ".32";
  string NAME = ?;
}
def anonymous_3123 {	// TokenAlias
  string FromToken = ".i64";
  string ToToken = ".64";
  string NAME = ?;
}
def anonymous_3124 {	// TokenAlias
  string FromToken = ".p8";
  string ToToken = ".8";
  string NAME = ?;
}
def anonymous_3125 {	// TokenAlias
  string FromToken = ".p16";
  string ToToken = ".16";
  string NAME = ?;
}
def anonymous_3126 {	// TokenAlias
  string FromToken = ".f32";
  string ToToken = ".32";
  string NAME = ?;
}
def anonymous_3127 {	// TokenAlias
  string FromToken = ".f64";
  string ToToken = ".64";
  string NAME = ?;
}
def anonymous_3128 {	// TokenAlias
  string FromToken = ".f";
  string ToToken = ".f32";
  string NAME = ?;
}
def anonymous_3129 {	// TokenAlias
  string FromToken = ".d";
  string ToToken = ".f64";
  string NAME = ?;
}
def anonymous_313 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_3130 {	// InstAlias Requires
  string AsmString = "nop$p";
  dag ResultInst = (HINT 0, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, HasV6K];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3131 {	// InstAlias Requires
  string AsmString = "yield$p";
  dag ResultInst = (HINT 1, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, HasV6K];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3132 {	// InstAlias Requires
  string AsmString = "wfe$p";
  dag ResultInst = (HINT 2, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, HasV6K];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3133 {	// InstAlias Requires
  string AsmString = "wfi$p";
  dag ResultInst = (HINT 3, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, HasV6K];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3134 {	// InstAlias Requires
  string AsmString = "sev$p";
  dag ResultInst = (HINT 4, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, HasV6K];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3135 {	// InstAlias Requires
  string AsmString = "sevl$p";
  dag ResultInst = (HINT 5, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, HasV8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3136 {	// InstAlias Requires
  string AsmString = "esb$p";
  dag ResultInst = (HINT 16, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, HasRAS];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3137 {	// InstAlias Requires
  string AsmString = "csdb$p";
  dag ResultInst = (HINT 20, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, HasV6K];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3138 {	// InstAlias Requires
  string AsmString = "bkpt";
  dag ResultInst = (BKPT 0);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3139 {	// MnemonicAlias
  string FromMnemonic = "smi";
  string ToMnemonic = "smc";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_314 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  string NAME = ?;
}
def anonymous_3140 {	// InstAlias Requires ARMInstAlias
  string AsmString = "srsda $mode";
  dag ResultInst = (SRSDA imm0_31:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3141 {	// InstAlias Requires ARMInstAlias
  string AsmString = "srsda $mode!";
  dag ResultInst = (SRSDA_UPD imm0_31:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3142 {	// InstAlias Requires ARMInstAlias
  string AsmString = "srsdb $mode";
  dag ResultInst = (SRSDB imm0_31:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3143 {	// InstAlias Requires ARMInstAlias
  string AsmString = "srsdb $mode!";
  dag ResultInst = (SRSDB_UPD imm0_31:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3144 {	// InstAlias Requires ARMInstAlias
  string AsmString = "srsia $mode";
  dag ResultInst = (SRSIA imm0_31:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3145 {	// InstAlias Requires ARMInstAlias
  string AsmString = "srsia $mode!";
  dag ResultInst = (SRSIA_UPD imm0_31:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3146 {	// InstAlias Requires ARMInstAlias
  string AsmString = "srsib $mode";
  dag ResultInst = (SRSIB imm0_31:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3147 {	// InstAlias Requires ARMInstAlias
  string AsmString = "srsib $mode!";
  dag ResultInst = (SRSIB_UPD imm0_31:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3148 {	// Pattern Pat ARMPat
  dag PatternToMatch = (post_store GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset);
  list<dag> ResultInstrs = [(STR_POST_REG GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3149 {	// Pattern Pat ARMPat
  dag PatternToMatch = (post_store GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset);
  list<dag> ResultInstrs = [(STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_315 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_3150 {	// Pattern Pat ARMPat
  dag PatternToMatch = (post_truncsti8 GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset);
  list<dag> ResultInstrs = [(STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3151 {	// Pattern Pat ARMPat
  dag PatternToMatch = (post_truncsti8 GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset);
  list<dag> ResultInstrs = [(STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3152 {	// InstAlias Requires
  string AsmString = "mov${p} $Rd, $imm";
  dag ResultInst = (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, HasV6T2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3153 {	// Pattern Pat ARMPat Requires
  dag PatternToMatch = (or GPR:$src, 4294901760);
  list<dag> ResultInstrs = [(MOVTi16 GPR:$src, 65535)];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3154 {	// SDPatternOperator PatFrag UnOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$Src);
  dag Fragment = (sext_inreg node:$Src, i8);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3155 {	// SDPatternOperator PatFrag UnOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$Src);
  dag Fragment = (sext_inreg node:$Src, i16);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3156 {	// SDPatternOperator PatFrag BinOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (add node:$LHS, (sext_inreg node:$RHS, i8));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3157 {	// SDPatternOperator PatFrag BinOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (add node:$LHS, (sext_inreg node:$RHS, i16));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3158 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8));
  list<dag> ResultInstrs = [(SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3159 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), i16));
  list<dag> ResultInstrs = [(SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_316 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  string NAME = ?;
}
def anonymous_3160 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_sxtb16 GPR:$Src);
  list<dag> ResultInstrs = [(SXTB16 GPR:$Src, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3161 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_sxtab16 GPR:$LHS, GPR:$RHS);
  list<dag> ResultInstrs = [(SXTAB16 GPR:$LHS, GPR:$RHS, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3162 {	// SDPatternOperator PatFrag UnOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$Src);
  dag Fragment = (and node:$Src, 255);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3163 {	// SDPatternOperator PatFrag UnOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$Src);
  dag Fragment = (and node:$Src, 65535);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3164 {	// SDPatternOperator PatFrag UnOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$Src);
  dag Fragment = (and node:$Src, 16711935);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3165 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (and (srl GPR:$Src, (i32 8)), 16711935);
  list<dag> ResultInstrs = [(UXTB16 GPR:$Src, 1)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3166 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_uxtb16 GPR:$Src);
  list<dag> ResultInstrs = [(UXTB16 GPR:$Src, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3167 {	// SDPatternOperator PatFrag BinOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (add node:$LHS, (and node:$RHS, 255));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3168 {	// SDPatternOperator PatFrag BinOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (add node:$LHS, (and node:$RHS, 65535));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3169 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 255));
  list<dag> ResultInstrs = [(UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_317 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_3170 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 65535));
  list<dag> ResultInstrs = [(UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3171 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_uxtab16 GPR:$LHS, GPR:$RHS);
  list<dag> ResultInstrs = [(UXTAB16 GPR:$LHS, GPR:$RHS, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3172 {	// Pattern Pat ARMPat
  dag PatternToMatch = (add GPR:$src, mod_imm_neg:$imm);
  list<dag> ResultInstrs = [(SUBri GPR:$src, mod_imm_neg:$imm)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3173 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMaddc GPR:$src, mod_imm_neg:$imm);
  list<dag> ResultInstrs = [(SUBSri GPR:$src, mod_imm_neg:$imm)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3174 {	// Pattern Pat ARMPat Requires
  dag PatternToMatch = (add GPR:$src, imm0_65535_neg:$imm);
  list<dag> ResultInstrs = [(SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3175 {	// Pattern Pat ARMPat Requires
  dag PatternToMatch = (ARMaddc GPR:$src, imm0_65535_neg:$imm);
  list<dag> ResultInstrs = [(SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3176 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMadde GPR:$src, mod_imm_not:$imm, CPSR);
  list<dag> ResultInstrs = [(SBCri GPR:$src, mod_imm_not:$imm)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3177 {	// Pattern Pat ARMPat Requires
  dag PatternToMatch = (ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR);
  list<dag> ResultInstrs = [(SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3178 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_ssat GPRnopc:$a, imm1_32:$pos);
  list<dag> ResultInstrs = [(SSAT imm1_32:$pos, GPRnopc:$a, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3179 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_usat GPRnopc:$a, imm0_31:$pos);
  list<dag> ResultInstrs = [(USAT imm0_31:$pos, GPRnopc:$a, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_318 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  string NAME = ?;
}
def anonymous_3180 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm);
  list<dag> ResultInstrs = [(SSAT imm0_31:$imm, GPRnopc:$Rn, 0)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3181 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm);
  list<dag> ResultInstrs = [(USAT imm0_31:$imm, GPRnopc:$Rn, 0)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3182 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_ssat16 GPRnopc:$a, imm1_16:$pos);
  list<dag> ResultInstrs = [(SSAT16 imm1_16:$pos, GPRnopc:$a)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3183 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_usat16 GPRnopc:$a, imm0_15:$pos);
  list<dag> ResultInstrs = [(USAT16 imm0_15:$pos, GPRnopc:$a)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3184 {	// SDPatternOperator PatFrag BinOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (and node:$LHS, (not node:$RHS));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3185 {	// Pattern Pat ARMPat
  dag PatternToMatch = (and GPR:$src, mod_imm_not:$imm);
  list<dag> ResultInstrs = [(BICri GPR:$src, mod_imm_not:$imm)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 1;
  string NAME = ?;
}
def anonymous_3186 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi);
  list<dag> ResultInstrs = [(SMLALBB ?:$Rn, ?:$Rm, ?:$RLo, ?:$RHi)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3187 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi);
  list<dag> ResultInstrs = [(SMLALBT ?:$Rn, ?:$Rm, ?:$RLo, ?:$RHi)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3188 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi);
  list<dag> ResultInstrs = [(SMLALTB ?:$Rn, ?:$Rm, ?:$RLo, ?:$RHi)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3189 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi);
  list<dag> ResultInstrs = [(SMLALTT ?:$Rn, ?:$Rm, ?:$RLo, ?:$RHi)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_319 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_3190 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra);
  list<dag> ResultInstrs = [(SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3191 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra);
  list<dag> ResultInstrs = [(SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3192 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra);
  list<dag> ResultInstrs = [(SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3193 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra);
  list<dag> ResultInstrs = [(SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3194 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi);
  list<dag> ResultInstrs = [(SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3195 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi);
  list<dag> ResultInstrs = [(SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3196 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi);
  list<dag> ResultInstrs = [(SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3197 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi);
  list<dag> ResultInstrs = [(SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3198 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm);
  list<dag> ResultInstrs = [(SMUAD GPRnopc:$Rn, GPRnopc:$Rm)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3199 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm);
  list<dag> ResultInstrs = [(SMUADX GPRnopc:$Rn, GPRnopc:$Rm)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_32 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_33];
  string NAME = ?;
}
def anonymous_320 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  string NAME = ?;
}
def anonymous_3200 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm);
  list<dag> ResultInstrs = [(SMUSD GPRnopc:$Rn, GPRnopc:$Rm)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3201 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm);
  list<dag> ResultInstrs = [(SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3202 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (srl (bswap (extloadi16 addrmode3:$addr)), (i32 16));
  list<dag> ResultInstrs = [(REV16 (LDRH addrmode3:$addr))];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3203 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr);
  list<dag> ResultInstrs = [(STRH (REV16 GPR:$Rn), addrmode3:$addr)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3204 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), (and (srl GPR:$Rm, (i32 8)), 255));
  list<dag> ResultInstrs = [(REVSH GPR:$Rm)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3205 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (or (and GPRnopc:$Rn, 65535), (and GPRnopc:$Rm, 4294901760));
  list<dag> ResultInstrs = [(PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3206 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (or (and GPRnopc:$Rn, 65535), (shl GPRnopc:$Rm, imm16_31:$sh));
  list<dag> ResultInstrs = [(PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3207 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (or (and GPRnopc:$src1, 4294901760), (srl GPRnopc:$src2, imm16:$sh));
  list<dag> ResultInstrs = [(PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3208 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (or (and GPRnopc:$src1, 4294901760), (sra GPRnopc:$src2, imm16_31:$sh));
  list<dag> ResultInstrs = [(PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3209 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (or (and GPRnopc:$src1, 4294901760), (and (srl GPRnopc:$src2, imm1_15:$sh), 65535));
  list<dag> ResultInstrs = [(PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_321 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_3210 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMcmpZ GPR:$src, mod_imm:$imm);
  list<dag> ResultInstrs = [(CMPri GPR:$src, mod_imm:$imm)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3211 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMcmpZ GPR:$src, GPR:$rhs);
  list<dag> ResultInstrs = [(CMPrr GPR:$src, GPR:$rhs)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3212 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMcmpZ GPR:$src, so_reg_imm:$rhs);
  list<dag> ResultInstrs = [(CMPrsi GPR:$src, so_reg_imm:$rhs)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3213 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMcmpZ GPR:$src, so_reg_reg:$rhs);
  list<dag> ResultInstrs = [(CMPrsr GPR:$src, so_reg_reg:$rhs)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3214 {	// SDPatternOperator PatFrag BinOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (ARMcmpZ node:$LHS, (ineg node:$RHS));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3215 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMcmp GPR:$src, mod_imm_neg:$imm);
  list<dag> ResultInstrs = [(CMNri GPR:$src, mod_imm_neg:$imm)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3216 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMcmpZ GPR:$src, mod_imm_neg:$imm);
  list<dag> ResultInstrs = [(CMNri GPR:$src, mod_imm_neg:$imm)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3217 {	// SDPatternOperator PatFrag BinOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (ARMcmpZ (and_su node:$LHS, node:$RHS), 0);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3218 {	// SDPatternOperator PatFrag BinOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (ARMcmpZ (xor_su node:$LHS, node:$RHS), 0);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3219 {	// Pattern Pat ARMPat
  dag PatternToMatch = (strex_1 (and GPR:$Rt, 255), addr_offset_none:$addr);
  list<dag> ResultInstrs = [(STREXB GPR:$Rt, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_322 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_3220 {	// Pattern Pat ARMPat
  dag PatternToMatch = (strex_2 (and GPR:$Rt, 65535), addr_offset_none:$addr);
  list<dag> ResultInstrs = [(STREXH GPR:$Rt, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3221 {	// Pattern Pat ARMPat
  dag PatternToMatch = (stlex_1 (and GPR:$Rt, 255), addr_offset_none:$addr);
  list<dag> ResultInstrs = [(STLEXB GPR:$Rt, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3222 {	// Pattern Pat ARMPat
  dag PatternToMatch = (stlex_2 (and GPR:$Rt, 65535), addr_offset_none:$addr);
  list<dag> ResultInstrs = [(STLEXH GPR:$Rt, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3223 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_load_acquire_8 addr_offset_none:$addr);
  list<dag> ResultInstrs = [(LDAB addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3224 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_load_acquire_16 addr_offset_none:$addr);
  list<dag> ResultInstrs = [(LDAH addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3225 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_load_acquire_32 addr_offset_none:$addr);
  list<dag> ResultInstrs = [(LDA addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3226 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_store_release_8 addr_offset_none:$addr, GPR:$val);
  list<dag> ResultInstrs = [(STLB GPR:$val, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3227 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_store_release_16 addr_offset_none:$addr, GPR:$val);
  list<dag> ResultInstrs = [(STLH GPR:$val, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3228 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_store_release_32 addr_offset_none:$addr, GPR:$val);
  list<dag> ResultInstrs = [(STL GPR:$val, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3229 {	// InstAlias Requires ARMInstAlias
  string AsmString = "mcr${p} $cop, $opc1, $Rt, $CRn, $CRm";
  dag ResultInst = (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_323 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_3230 {	// InstAlias Requires ARMInstAlias
  string AsmString = "mrc${p} $cop, $opc1, $Rt, $CRn, $CRm";
  dag ResultInst = (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3231 {	// Pattern Pat ARMPat
  dag PatternToMatch = (int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2);
  list<dag> ResultInstrs = [(MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3232 {	// InstAlias Requires ARMInstAlias
  string AsmString = "mcr2 $cop, $opc1, $Rt, $CRn, $CRm";
  dag ResultInst = (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3233 {	// InstAlias Requires ARMInstAlias
  string AsmString = "mrc2 $cop, $opc1, $Rt, $CRn, $CRm";
  dag ResultInst = (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3234 {	// Pattern Pat ARMV5TPat
  dag PatternToMatch = (int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2);
  list<dag> ResultInstrs = [(MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Predicate> Predicates = [IsARM, HasV5T];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3235 {	// InstAlias Requires
  string AsmString = "mrs${p} $Rd, cpsr";
  dag ResultInst = (MRS GPRnopc:$Rd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3236 {	// Pattern Pat ARMPat Requires
  dag PatternToMatch = (ARMthread_pointer);
  list<dag> ResultInstrs = [(MRC 15, 0, 13, 0, 3)];
  list<Predicate> Predicates = [IsARM, IsReadTPHard];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3237 {	// Pattern Pat ARMPat Requires
  dag PatternToMatch = (ARMWrapper tglobaltlsaddr:$dst);
  list<dag> ResultInstrs = [(MOVi32imm tglobaltlsaddr:$dst)];
  list<Predicate> Predicates = [IsARM, UseMovt];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3238 {	// Pattern Pat Requires
  dag PatternToMatch = (ARMWrapper tglobaltlsaddr:$src);
  list<dag> ResultInstrs = [(LDRLIT_ga_abs tglobaltlsaddr:$src)];
  list<Predicate> Predicates = [IsARM, DontUseMovt];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3239 {	// Pattern Pat Requires
  dag PatternToMatch = (ARMWrapperPIC tglobaltlsaddr:$addr);
  list<dag> ResultInstrs = [(MOV_ga_pcrel tglobaltlsaddr:$addr)];
  list<Predicate> Predicates = [IsARM, UseMovtInPic];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_324 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_3240 {	// Pattern Pat Requires
  dag PatternToMatch = (ARMWrapperPIC tglobaltlsaddr:$addr);
  list<dag> ResultInstrs = [(LDRLIT_ga_pcrel tglobaltlsaddr:$addr)];
  list<Predicate> Predicates = [IsARM, DontUseMovtInPic];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3241 {	// Pattern Pat Requires
  dag PatternToMatch = (load (ARMWrapperPIC tglobaltlsaddr:$addr));
  list<dag> ResultInstrs = [(MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)];
  list<Predicate> Predicates = [IsARM, UseMovtInPic];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_3242 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMWrapper tconstpool:$dst);
  list<dag> ResultInstrs = [(LEApcrel tconstpool:$dst)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3243 {	// Pattern Pat ARMPat Requires
  dag PatternToMatch = (ARMWrapper tglobaladdr:$dst);
  list<dag> ResultInstrs = [(MOVi32imm tglobaladdr:$dst)];
  list<Predicate> Predicates = [IsARM, UseMovt];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3244 {	// Pattern Pat ARMPat Requires
  dag PatternToMatch = (ARMWrapper texternalsym:$dst);
  list<dag> ResultInstrs = [(MOVi32imm texternalsym:$dst)];
  list<Predicate> Predicates = [IsARM, UseMovt];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3245 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMWrapperJT tjumptable:$dst);
  list<dag> ResultInstrs = [(LEApcrelJT tjumptable:$dst)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3246 {	// Pattern Pat
  dag PatternToMatch = (ARMtcret tcGPR:$dst);
  list<dag> ResultInstrs = [(TCRETURNri tcGPR:$dst)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3247 {	// Pattern Pat
  dag PatternToMatch = (ARMtcret (i32 tglobaladdr:$dst));
  list<dag> ResultInstrs = [(TCRETURNdi texternalsym:$dst)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3248 {	// Pattern Pat
  dag PatternToMatch = (ARMtcret (i32 texternalsym:$dst));
  list<dag> ResultInstrs = [(TCRETURNdi texternalsym:$dst)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3249 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMcall texternalsym:$func);
  list<dag> ResultInstrs = [(BL texternalsym:$func)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_325 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_3250 {	// Pattern Pat ARMPat
  dag PatternToMatch = (ARMcall_nolink texternalsym:$func);
  list<dag> ResultInstrs = [(BMOVPCB_CALL texternalsym:$func)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3251 {	// Pattern Pat ARMPat
  dag PatternToMatch = (zextloadi1 addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(LDRBi12 addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3252 {	// Pattern Pat ARMPat
  dag PatternToMatch = (zextloadi1 ldst_so_reg:$addr);
  list<dag> ResultInstrs = [(LDRBrs ldst_so_reg:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3253 {	// Pattern Pat ARMPat
  dag PatternToMatch = (extloadi1 addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(LDRBi12 addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3254 {	// Pattern Pat ARMPat
  dag PatternToMatch = (extloadi1 ldst_so_reg:$addr);
  list<dag> ResultInstrs = [(LDRBrs ldst_so_reg:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3255 {	// Pattern Pat ARMPat
  dag PatternToMatch = (extloadi8 addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(LDRBi12 addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3256 {	// Pattern Pat ARMPat
  dag PatternToMatch = (extloadi8 ldst_so_reg:$addr);
  list<dag> ResultInstrs = [(LDRBrs ldst_so_reg:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3257 {	// Pattern Pat ARMPat
  dag PatternToMatch = (extloadi16 addrmode3:$addr);
  list<dag> ResultInstrs = [(LDRH addrmode3:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3258 {	// Pattern Pat ARMPat
  dag PatternToMatch = (extloadi8 addrmodepc:$addr);
  list<dag> ResultInstrs = [(PICLDRB addrmodepc:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3259 {	// Pattern Pat ARMPat
  dag PatternToMatch = (extloadi16 addrmodepc:$addr);
  list<dag> ResultInstrs = [(PICLDRH addrmodepc:$addr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_326 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_3260 {	// Pattern Pat ARMV5TEPat Sched
  dag PatternToMatch = (mul sext_16_node:$a, sext_16_node:$b);
  list<dag> ResultInstrs = [(SMULBB GPR:$a, GPR:$b)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string NAME = ?;
}
def anonymous_3261 {	// Pattern Pat ARMV5TEPat Sched
  dag PatternToMatch = (mul sext_16_node:$a, (sra GPR:$b, (i32 16)));
  list<dag> ResultInstrs = [(SMULBT GPR:$a, GPR:$b)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string NAME = ?;
}
def anonymous_3262 {	// Pattern Pat ARMV5TEPat Sched
  dag PatternToMatch = (mul (sra GPR:$a, (i32 16)), sext_16_node:$b);
  list<dag> ResultInstrs = [(SMULTB GPR:$a, GPR:$b)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string NAME = ?;
}
def anonymous_3263 {	// Pattern Pat ARMV5MOPat Sched
  dag PatternToMatch = (add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b));
  list<dag> ResultInstrs = [(SMLABB GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int AddedComplexity = 0;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string NAME = ?;
}
def anonymous_3264 {	// Pattern Pat ARMV5MOPat Sched
  dag PatternToMatch = (add GPR:$acc, (mul sext_16_node:$a, (sra GPR:$b, (i32 16))));
  list<dag> ResultInstrs = [(SMLABT GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int AddedComplexity = 0;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string NAME = ?;
}
def anonymous_3265 {	// Pattern Pat ARMV5MOPat Sched
  dag PatternToMatch = (add GPR:$acc, (mul (sra GPR:$a, (i32 16)), sext_16_node:$b));
  list<dag> ResultInstrs = [(SMLATB GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
  int AddedComplexity = 0;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string NAME = ?;
}
def anonymous_3266 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smulbb GPR:$a, GPR:$b);
  list<dag> ResultInstrs = [(SMULBB GPR:$a, GPR:$b)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3267 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smulbt GPR:$a, GPR:$b);
  list<dag> ResultInstrs = [(SMULBT GPR:$a, GPR:$b)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3268 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smultb GPR:$a, GPR:$b);
  list<dag> ResultInstrs = [(SMULTB GPR:$a, GPR:$b)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3269 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smultt GPR:$a, GPR:$b);
  list<dag> ResultInstrs = [(SMULTT GPR:$a, GPR:$b)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_327 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_3270 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smulwb GPR:$a, GPR:$b);
  list<dag> ResultInstrs = [(SMULWB GPR:$a, GPR:$b)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3271 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smulwt GPR:$a, GPR:$b);
  list<dag> ResultInstrs = [(SMULWT GPR:$a, GPR:$b)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3272 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(SMLABB GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3273 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(SMLABT GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3274 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(SMLATB GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3275 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(SMLATT GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3276 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(SMLAWB GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3277 {	// Pattern Pat ARMV5TEPat
  dag PatternToMatch = (int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(SMLAWT GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsARM, HasV5TE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3278 {	// Pattern Pat ARMPat Requires
  dag PatternToMatch = (ARMMemBarrierMCR GPR:$zero);
  list<dag> ResultInstrs = [(MCR 15, 0, GPR:$zero, 7, 10, 5)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3279 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (and GPR:$Src, 255);
  list<dag> ResultInstrs = [(UXTB GPR:$Src, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_328 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "SAMPLE_C_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_3280 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (and GPR:$Src, 65535);
  list<dag> ResultInstrs = [(UXTH GPR:$Src, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3281 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (and GPR:$Src, 16711935);
  list<dag> ResultInstrs = [(UXTB16 GPR:$Src, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3282 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (add GPR:$Rn, (and GPR:$Rm, 255));
  list<dag> ResultInstrs = [(UXTAB GPR:$Rn, GPR:$Rm, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3283 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (add GPR:$Rn, (and GPR:$Rm, 65535));
  list<dag> ResultInstrs = [(UXTAH GPR:$Rn, GPR:$Rm, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3284 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (sext_inreg GPR:$Src, i8);
  list<dag> ResultInstrs = [(SXTB GPR:$Src, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3285 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (sext_inreg GPR:$Src, i16);
  list<dag> ResultInstrs = [(SXTH GPR:$Src, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3286 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8));
  list<dag> ResultInstrs = [(SXTAB GPR:$Rn, GPRnopc:$Rm, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3287 {	// Pattern Pat ARMV6Pat
  dag PatternToMatch = (add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16));
  list<dag> ResultInstrs = [(SXTAH GPR:$Rn, GPRnopc:$Rm, 0)];
  list<Predicate> Predicates = [IsARM, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3288 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_load_8 ldst_so_reg:$src);
  list<dag> ResultInstrs = [(LDRBrs ldst_so_reg:$src)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3289 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_load_8 addrmode_imm12:$src);
  list<dag> ResultInstrs = [(LDRBi12 addrmode_imm12:$src)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_329 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3290 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_load_16 addrmode3:$src);
  list<dag> ResultInstrs = [(LDRH addrmode3:$src)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3291 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_load_32 ldst_so_reg:$src);
  list<dag> ResultInstrs = [(LDRrs ldst_so_reg:$src)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3292 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_load_32 addrmode_imm12:$src);
  list<dag> ResultInstrs = [(LDRi12 addrmode_imm12:$src)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3293 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_store_8 ldst_so_reg:$ptr, GPR:$val);
  list<dag> ResultInstrs = [(STRBrs GPR:$val, ldst_so_reg:$ptr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3294 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_store_8 addrmode_imm12:$ptr, GPR:$val);
  list<dag> ResultInstrs = [(STRBi12 GPR:$val, addrmode_imm12:$ptr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3295 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_store_16 addrmode3:$ptr, GPR:$val);
  list<dag> ResultInstrs = [(STRH GPR:$val, addrmode3:$ptr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3296 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_store_32 ldst_so_reg:$ptr, GPR:$val);
  list<dag> ResultInstrs = [(STRrs GPR:$val, ldst_so_reg:$ptr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3297 {	// Pattern Pat ARMPat
  dag PatternToMatch = (atomic_store_32 addrmode_imm12:$ptr, GPR:$val);
  list<dag> ResultInstrs = [(STRi12 GPR:$val, addrmode_imm12:$ptr)];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3298 {	// InstAlias Requires tInstAlias tHintAlias
  string AsmString = "nop$p";
  dag ResultInst = (tHINT 0, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb, HasV6M];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3299 {	// InstAlias Requires tInstAlias tHintAlias
  string AsmString = "yield$p";
  dag ResultInst = (tHINT 1, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb, HasV6M];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_33 {	// AMDGPUArg
  LLVMType Type = llvm_anyint_ty;
  string Name = "s";
  string NAME = ?;
}
def anonymous_330 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_81];
  string NAME = ?;
}
def anonymous_3300 {	// InstAlias Requires tInstAlias tHintAlias
  string AsmString = "wfe$p";
  dag ResultInst = (tHINT 2, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb, HasV6M];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3301 {	// InstAlias Requires tInstAlias tHintAlias
  string AsmString = "wfi$p";
  dag ResultInst = (tHINT 3, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb, HasV6M];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3302 {	// InstAlias Requires tInstAlias tHintAlias
  string AsmString = "sev$p";
  dag ResultInst = (tHINT 4, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb, HasV6M];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3303 {	// InstAlias Requires tInstAlias
  string AsmString = "sevl$p";
  dag ResultInst = (tHINT 5, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2, HasV8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3304 {	// InstAlias Requires
  string AsmString = "bkpt";
  dag ResultInst = (tBKPT 0);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3305 {	// InstAlias Requires tInstSubst
  string AsmString = "add${p} sp, $imm";
  dag ResultInst = (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3306 {	// InstAlias Requires tInstSubst
  string AsmString = "add${p} sp, sp, $imm";
  dag ResultInst = (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3307 {	// InstAlias Requires tInstAlias
  string AsmString = "add${p} sp, sp, $imm";
  dag ResultInst = (tADDspi SP, t_imm0_508s4:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3308 {	// InstAlias Requires tInstAlias
  string AsmString = "sub${p} sp, sp, $imm";
  dag ResultInst = (tSUBspi SP, t_imm0_508s4:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3309 {	// InstAlias Requires
  string AsmString = "ldm${p} $Rn!, $regs";
  dag ResultInst = (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_331 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_81];
  string NAME = ?;
}
def anonymous_3310 {	// InstAlias Requires tInstAlias
  string AsmString = "add${s}${p} $Rdn, $Rm";
  dag ResultInst = (tADDrr tGPR:$Rdn, s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3311 {	// InstAlias Requires tInstSubst
  string AsmString = "sub${s}${p} $rd, $rn, $imm";
  dag ResultInst = (tADDi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3312 {	// InstAlias Requires tInstSubst
  string AsmString = "sub${s}${p} $rdn, $imm";
  dag ResultInst = (tADDi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3313 {	// InstAlias Requires tInstAlias
  string AsmString = "movs $Rdn, $imm";
  dag ResultInst = (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3314 {	// InstAlias Requires tInstAlias
  string AsmString = "mul${s}${p} $Rdm, $Rn";
  dag ResultInst = (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3315 {	// InstAlias Requires tInstSubst
  string AsmString = "add${s}${p} $rd, $rn, $imm";
  dag ResultInst = (tSUBi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3316 {	// InstAlias Requires tInstSubst
  string AsmString = "add${s}${p} $rdn, $imm";
  dag ResultInst = (tSUBi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3317 {	// InstAlias Requires tInstAlias
  string AsmString = "sub${s}${p} $Rdn, $Rm";
  dag ResultInst = (tSUBrr tGPR:$Rdn, s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3318 {	// Pattern Pat T1Pat
  dag PatternToMatch = (ARMcmpZ tGPR:$Rn, imm0_255:$imm8);
  list<dag> ResultInstrs = [(tCMPi8 tGPR:$Rn, imm0_255:$imm8)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3319 {	// Pattern Pat T1Pat
  dag PatternToMatch = (ARMcmpZ tGPR:$Rn, tGPR:$Rm);
  list<dag> ResultInstrs = [(tCMPr tGPR:$Rn, tGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_332 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "r";
  string NAME = ?;
}
def anonymous_3320 {	// Pattern Pat T1Pat
  dag PatternToMatch = (srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16));
  list<dag> ResultInstrs = [(tREV16 (tLDRHi t_addrmode_is2:$addr))];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3321 {	// Pattern Pat T1Pat
  dag PatternToMatch = (srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16));
  list<dag> ResultInstrs = [(tREV16 (tLDRHr t_addrmode_rr:$addr))];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3322 {	// Pattern Pat T1Pat
  dag PatternToMatch = (truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), t_addrmode_is2:$addr);
  list<dag> ResultInstrs = [(tSTRHi (tREV16 tGPR:$Rn), t_addrmode_is2:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3323 {	// Pattern Pat T1Pat
  dag PatternToMatch = (truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), t_addrmode_rr:$addr);
  list<dag> ResultInstrs = [(tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3324 {	// Pattern Pat T1Pat
  dag PatternToMatch = (ARMWrapper tconstpool:$dst);
  list<dag> ResultInstrs = [(tLEApcrel tconstpool:$dst)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3325 {	// Pattern Pat Requires
  dag PatternToMatch = (ARMWrapperPIC tglobaltlsaddr:$addr);
  list<dag> ResultInstrs = [(tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)];
  list<Predicate> Predicates = [IsThumb, DontUseMovtInPic];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3326 {	// Pattern Pat Requires
  dag PatternToMatch = (ARMWrapper tglobaltlsaddr:$addr);
  list<dag> ResultInstrs = [(tLDRLIT_ga_abs tglobaltlsaddr:$addr)];
  list<Predicate> Predicates = [IsThumb, DontUseMovt];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3327 {	// Pattern Pat T1Pat
  dag PatternToMatch = (ARMWrapperJT tjumptable:$dst);
  list<dag> ResultInstrs = [(tLEApcrelJT tjumptable:$dst)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3328 {	// Pattern Pat T1Pat Requires
  dag PatternToMatch = (ARMcall texternalsym:$func);
  list<dag> ResultInstrs = [(tBL texternalsym:$func)];
  list<Predicate> Predicates = [IsThumb];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3329 {	// Pattern Pat T1Pat
  dag PatternToMatch = (zextloadi1 t_addrmode_is1:$addr);
  list<dag> ResultInstrs = [(tLDRBi t_addrmode_is1:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_333 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "r";
  string NAME = ?;
}
def anonymous_3330 {	// Pattern Pat T1Pat
  dag PatternToMatch = (zextloadi1 t_addrmode_rr:$addr);
  list<dag> ResultInstrs = [(tLDRBr t_addrmode_rr:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3331 {	// Pattern Pat T1Pat Requires
  dag PatternToMatch = (extloadi1 t_addrmode_sp:$addr);
  list<dag> ResultInstrs = [(tLDRspi t_addrmode_sp:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3332 {	// Pattern Pat T1Pat Requires
  dag PatternToMatch = (extloadi8 t_addrmode_sp:$addr);
  list<dag> ResultInstrs = [(tLDRspi t_addrmode_sp:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3333 {	// Pattern Pat T1Pat Requires
  dag PatternToMatch = (extloadi16 t_addrmode_sp:$addr);
  list<dag> ResultInstrs = [(tLDRspi t_addrmode_sp:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3334 {	// Pattern Pat T1Pat
  dag PatternToMatch = (extloadi1 t_addrmode_is1:$addr);
  list<dag> ResultInstrs = [(tLDRBi t_addrmode_is1:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3335 {	// Pattern Pat T1Pat
  dag PatternToMatch = (extloadi1 t_addrmode_rr:$addr);
  list<dag> ResultInstrs = [(tLDRBr t_addrmode_rr:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3336 {	// Pattern Pat T1Pat
  dag PatternToMatch = (extloadi8 t_addrmode_is1:$addr);
  list<dag> ResultInstrs = [(tLDRBi t_addrmode_is1:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3337 {	// Pattern Pat T1Pat
  dag PatternToMatch = (extloadi8 t_addrmode_rr:$addr);
  list<dag> ResultInstrs = [(tLDRBr t_addrmode_rr:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3338 {	// Pattern Pat T1Pat
  dag PatternToMatch = (extloadi16 t_addrmode_is2:$addr);
  list<dag> ResultInstrs = [(tLDRHi t_addrmode_is2:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3339 {	// Pattern Pat T1Pat
  dag PatternToMatch = (extloadi16 t_addrmode_rr:$addr);
  list<dag> ResultInstrs = [(tLDRHr t_addrmode_rr:$addr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_334 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3340 {	// Pattern Pat T1Pat
  dag PatternToMatch = (post_store rGPR:$Rt, rGPR:$Rn, 4);
  list<dag> ResultInstrs = [(tSTMIA_UPD rGPR:$Rn, rGPR:$Rt)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3341 {	// Pattern Pat T1Pat Requires
  dag PatternToMatch = (sextloadi8 t_addrmode_is1:$addr);
  list<dag> ResultInstrs = [(tSXTB (tLDRBi t_addrmode_is1:$addr))];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3342 {	// Pattern Pat T1Pat Requires
  dag PatternToMatch = (sextloadi8 t_addrmode_rr:$addr);
  list<dag> ResultInstrs = [(tSXTB (tLDRBr t_addrmode_rr:$addr))];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3343 {	// Pattern Pat T1Pat Requires
  dag PatternToMatch = (sextloadi16 t_addrmode_is2:$addr);
  list<dag> ResultInstrs = [(tSXTH (tLDRHi t_addrmode_is2:$addr))];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3344 {	// Pattern Pat T1Pat Requires
  dag PatternToMatch = (sextloadi16 t_addrmode_rr:$addr);
  list<dag> ResultInstrs = [(tSXTH (tLDRHr t_addrmode_rr:$addr))];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3345 {	// Pattern Pat T1Pat
  dag PatternToMatch = (sextloadi8 t_addrmode_is1:$addr);
  list<dag> ResultInstrs = [(tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3346 {	// Pattern Pat T1Pat
  dag PatternToMatch = (sextloadi8 t_addrmode_rr:$addr);
  list<dag> ResultInstrs = [(tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3347 {	// Pattern Pat T1Pat
  dag PatternToMatch = (sextloadi16 t_addrmode_is2:$addr);
  list<dag> ResultInstrs = [(tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3348 {	// Pattern Pat T1Pat
  dag PatternToMatch = (sextloadi16 t_addrmode_rr:$addr);
  list<dag> ResultInstrs = [(tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3349 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_load_8 t_addrmode_is1:$src);
  list<dag> ResultInstrs = [(tLDRBi t_addrmode_is1:$src)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_335 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_81];
  string NAME = ?;
}
def anonymous_3350 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_load_8 t_addrmode_rr:$src);
  list<dag> ResultInstrs = [(tLDRBr t_addrmode_rr:$src)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3351 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_load_16 t_addrmode_is2:$src);
  list<dag> ResultInstrs = [(tLDRHi t_addrmode_is2:$src)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3352 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_load_16 t_addrmode_rr:$src);
  list<dag> ResultInstrs = [(tLDRHr t_addrmode_rr:$src)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3353 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_load_32 t_addrmode_is4:$src);
  list<dag> ResultInstrs = [(tLDRi t_addrmode_is4:$src)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3354 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_load_32 t_addrmode_rr:$src);
  list<dag> ResultInstrs = [(tLDRr t_addrmode_rr:$src)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3355 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val);
  list<dag> ResultInstrs = [(tSTRBi tGPR:$val, t_addrmode_is1:$ptr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3356 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val);
  list<dag> ResultInstrs = [(tSTRBr tGPR:$val, t_addrmode_rr:$ptr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3357 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val);
  list<dag> ResultInstrs = [(tSTRHi tGPR:$val, t_addrmode_is2:$ptr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3358 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val);
  list<dag> ResultInstrs = [(tSTRHr tGPR:$val, t_addrmode_rr:$ptr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3359 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val);
  list<dag> ResultInstrs = [(tSTRi tGPR:$val, t_addrmode_is4:$ptr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_336 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3360 {	// Pattern Pat T1Pat
  dag PatternToMatch = (atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val);
  list<dag> ResultInstrs = [(tSTRr tGPR:$val, t_addrmode_rr:$ptr)];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3361 {	// Pattern Pat T1Pat
  dag PatternToMatch = (i32 thumb_immshifted:$src);
  list<dag> ResultInstrs = [(tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), (thumb_immshifted_shamt imm:$src))];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3362 {	// Pattern Pat T1Pat
  dag PatternToMatch = (i32 imm0_255_comp:$src);
  list<dag> ResultInstrs = [(tMVN (tMOVi8 (imm_not_XFORM imm:$src)))];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3363 {	// Pattern Pat T1Pat
  dag PatternToMatch = (i32 imm256_510:$src);
  list<dag> ResultInstrs = [(tADDi8 (tMOVi8 255), (thumb_imm256_510_addend imm:$src))];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3364 {	// InstAlias Requires
  string AsmString = "nop";
  dag ResultInst = (tMOVr R8, R8, 14, 0);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3365 {	// InstAlias Requires tInstAlias
  string AsmString = "neg${s}${p} $Rd, $Rm";
  dag ResultInst = (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3366 {	// InstAlias Requires tInstAlias
  string AsmString = "lsl${s}${p} $Rdm, $imm";
  dag ResultInst = (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3367 {	// InstAlias Requires tInstAlias
  string AsmString = "lsr${s}${p} $Rdm, $imm";
  dag ResultInst = (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3368 {	// InstAlias Requires tInstAlias
  string AsmString = "asr${s}${p} $Rdm, $imm";
  dag ResultInst = (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_337 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_81];
  string NAME = ?;
}
def anonymous_338 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3386 {	// Pattern Pat T2Pat
  dag PatternToMatch = (zextloadi1 t2addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(t2LDRBi12 t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3387 {	// Pattern Pat T2Pat
  dag PatternToMatch = (zextloadi1 t2addrmode_negimm8:$addr);
  list<dag> ResultInstrs = [(t2LDRBi8 t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3388 {	// Pattern Pat T2Pat
  dag PatternToMatch = (zextloadi1 t2addrmode_so_reg:$addr);
  list<dag> ResultInstrs = [(t2LDRBs t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3389 {	// Pattern Pat T2Pat
  dag PatternToMatch = (zextloadi1 (ARMWrapper tconstpool:$addr));
  list<dag> ResultInstrs = [(t2LDRBpci tconstpool:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_339 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_81];
  string NAME = ?;
}
def anonymous_3390 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi1 t2addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(t2LDRBi12 t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3391 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi1 t2addrmode_negimm8:$addr);
  list<dag> ResultInstrs = [(t2LDRBi8 t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3392 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi1 t2addrmode_so_reg:$addr);
  list<dag> ResultInstrs = [(t2LDRBs t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3393 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi1 (ARMWrapper tconstpool:$addr));
  list<dag> ResultInstrs = [(t2LDRBpci tconstpool:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3394 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi8 t2addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(t2LDRBi12 t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3395 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi8 t2addrmode_negimm8:$addr);
  list<dag> ResultInstrs = [(t2LDRBi8 t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3396 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi8 t2addrmode_so_reg:$addr);
  list<dag> ResultInstrs = [(t2LDRBs t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3397 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi8 (ARMWrapper tconstpool:$addr));
  list<dag> ResultInstrs = [(t2LDRBpci tconstpool:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3398 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi16 t2addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(t2LDRHi12 t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3399 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi16 t2addrmode_negimm8:$addr);
  list<dag> ResultInstrs = [(t2LDRHi8 t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_34 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_35, anonymous_36];
  string NAME = ?;
}
def anonymous_340 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_81, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3400 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi16 t2addrmode_so_reg:$addr);
  list<dag> ResultInstrs = [(t2LDRHs t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3401 {	// Pattern Pat T2Pat
  dag PatternToMatch = (extloadi16 (ARMWrapper tconstpool:$addr));
  list<dag> ResultInstrs = [(t2LDRHpci tconstpool:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3402 {	// InstAlias Requires t2InstAlias
  string AsmString = "mov${p}.w $Rd, $Rm";
  dag ResultInst = (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, zero_reg);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3403 {	// InstAlias Requires t2InstAlias
  string AsmString = "movs${p}.w $Rd, $Rm";
  dag ResultInst = (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, CPSR);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3404 {	// InstAlias Requires t2InstAlias
  string AsmString = "movs${p} $Rd, $Rm";
  dag ResultInst = (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, CPSR);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3405 {	// InstAlias Requires t2InstAlias
  string AsmString = "movs${p}.w $Rd, $imm";
  dag ResultInst = (t2MOVi rGPR:$Rd, t2_so_imm:$imm, pred:$p, CPSR);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3406 {	// InstAlias Requires t2InstAlias
  string AsmString = "movs${p} $Rd, $imm";
  dag ResultInst = (t2MOVi rGPR:$Rd, t2_so_imm:$imm, pred:$p, CPSR);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3407 {	// InstAlias Requires t2InstAlias
  string AsmString = "mov${p}.w $Rd, $imm";
  dag ResultInst = (t2MOVi rGPR:$Rd, t2_so_imm:$imm, pred:$p, zero_reg);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3408 {	// InstAlias Requires t2InstAlias
  string AsmString = "mov${p} $Rd, $imm";
  dag ResultInst = (t2MOVi rGPR:$Rd, t2_so_imm:$imm, pred:$p, zero_reg);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3409 {	// InstAlias Requires Sched
  string AsmString = "mov${p} $Rd, $imm";
  dag ResultInst = (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  list<SchedReadWrite> SchedRW = [WriteALU];
  string NAME = ?;
}
def anonymous_341 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_81, anonymous_163];
  string NAME = ?;
}
def anonymous_3410 {	// Pattern Pat T2Pat
  dag PatternToMatch = (or rGPR:$src, 4294901760);
  list<dag> ResultInstrs = [(t2MOVTi16 rGPR:$src, 65535)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3411 {	// Pattern Pat T2Pat
  dag PatternToMatch = (sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8);
  list<dag> ResultInstrs = [(t2SXTB rGPR:$Rn, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3412 {	// Pattern Pat T2Pat
  dag PatternToMatch = (sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16);
  list<dag> ResultInstrs = [(t2SXTH rGPR:$Rn, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3413 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8));
  list<dag> ResultInstrs = [(t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3414 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16));
  list<dag> ResultInstrs = [(t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3415 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_sxtb16 rGPR:$Rn);
  list<dag> ResultInstrs = [(t2SXTB16 rGPR:$Rn, 0)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3416 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_sxtab16 rGPR:$Rn, rGPR:$Rm);
  list<dag> ResultInstrs = [(t2SXTAB16 rGPR:$Rn, rGPR:$Rm, 0)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3417 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8));
  list<dag> ResultInstrs = [(t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3418 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), i16));
  list<dag> ResultInstrs = [(t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3419 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg (rotr rGPR:$Rm, (i32 24)), i16));
  list<dag> ResultInstrs = [(t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_342 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_81, anonymous_163];
  string NAME = ?;
}
def anonymous_3420 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg (or (srl rGPR:$Rm, (i32 24)), (shl rGPR:$Rm, (i32 8))), i16));
  list<dag> ResultInstrs = [(t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3421 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (and (rotr rGPR:$Rm, rot_imm:$rot), 255);
  list<dag> ResultInstrs = [(t2UXTB rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3422 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (and (rotr rGPR:$Rm, rot_imm:$rot), 65535);
  list<dag> ResultInstrs = [(t2UXTH rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3423 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (and (rotr rGPR:$Rm, rot_imm:$rot), 16711935);
  list<dag> ResultInstrs = [(t2UXTB16 rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3424 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_uxtb16 rGPR:$Rm);
  list<dag> ResultInstrs = [(t2UXTB16 rGPR:$Rm, 0)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3425 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (and (srl rGPR:$Src, (i32 8)), 16711935);
  list<dag> ResultInstrs = [(t2UXTB16 rGPR:$Src, 1)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3426 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot), 255));
  list<dag> ResultInstrs = [(t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3427 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot), 65535));
  list<dag> ResultInstrs = [(t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3428 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 255));
  list<dag> ResultInstrs = [(t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3429 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 65535));
  list<dag> ResultInstrs = [(t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_343 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_81, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3430 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_uxtab16 rGPR:$Rn, rGPR:$Rm);
  list<dag> ResultInstrs = [(t2UXTAB16 rGPR:$Rn, rGPR:$Rm, 0)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3431 {	// InstAlias Requires t2InstSubst
  string AsmString = "adc${s}${p} $rd, $rn, $imm";
  dag ResultInst = (t2SBCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3432 {	// InstAlias Requires t2InstSubst
  string AsmString = "sbc${s}${p} $rd, $rn, $imm";
  dag ResultInst = (t2ADCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3433 {	// InstAlias Requires t2InstSubst
  string AsmString = "add${s}${p}.w $rd, $rn, $imm";
  dag ResultInst = (t2SUBri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3434 {	// InstAlias Requires t2InstSubst
  string AsmString = "addw${p} $rd, $rn, $imm";
  dag ResultInst = (t2SUBri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3435 {	// InstAlias Requires t2InstSubst
  string AsmString = "sub${s}${p}.w $rd, $rn, $imm";
  dag ResultInst = (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3436 {	// InstAlias Requires t2InstSubst
  string AsmString = "subw${p} $rd, $rn, $imm";
  dag ResultInst = (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3437 {	// Pattern Pat T2Pat
  dag PatternToMatch = (add GPR:$src, imm1_255_neg:$imm);
  list<dag> ResultInstrs = [(t2SUBri GPR:$src, imm1_255_neg:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 1;
  string NAME = ?;
}
def anonymous_3438 {	// Pattern Pat T2Pat
  dag PatternToMatch = (add GPR:$src, t2_so_imm_neg:$imm);
  list<dag> ResultInstrs = [(t2SUBri GPR:$src, t2_so_imm_neg:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3439 {	// Pattern Pat T2Pat
  dag PatternToMatch = (add GPR:$src, imm0_4095_neg:$imm);
  list<dag> ResultInstrs = [(t2SUBri12 GPR:$src, imm0_4095_neg:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_344 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_81, anonymous_163];
  string NAME = ?;
}
def anonymous_3440 {	// Pattern Pat T2Pat
  dag PatternToMatch = (add GPR:$src, imm0_65535_neg:$imm);
  list<dag> ResultInstrs = [(t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3441 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMaddc rGPR:$src, imm1_255_neg:$imm);
  list<dag> ResultInstrs = [(t2SUBSri rGPR:$src, imm1_255_neg:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 1;
  string NAME = ?;
}
def anonymous_3442 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMaddc rGPR:$src, t2_so_imm_neg:$imm);
  list<dag> ResultInstrs = [(t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3443 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMaddc rGPR:$src, imm0_65535_neg:$imm);
  list<dag> ResultInstrs = [(t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3444 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMadde rGPR:$src, imm0_255_not:$imm, CPSR);
  list<dag> ResultInstrs = [(t2SBCri rGPR:$src, imm0_255_not:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 1;
  string NAME = ?;
}
def anonymous_3445 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR);
  list<dag> ResultInstrs = [(t2SBCri rGPR:$src, t2_so_imm_not:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3446 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR);
  list<dag> ResultInstrs = [(t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3447 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_qadd rGPR:$Rm, rGPR:$Rn);
  list<dag> ResultInstrs = [(t2QADD rGPR:$Rm, rGPR:$Rn)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3448 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_qsub rGPR:$Rm, rGPR:$Rn);
  list<dag> ResultInstrs = [(t2QSUB rGPR:$Rm, rGPR:$Rn)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3449 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_qadd (int_arm_qadd rGPR:$Rm, rGPR:$Rm), rGPR:$Rn);
  list<dag> ResultInstrs = [(t2QDADD rGPR:$Rm, rGPR:$Rn)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_345 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_81, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3450 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_qsub rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn));
  list<dag> ResultInstrs = [(t2QDSUB rGPR:$Rm, rGPR:$Rn)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3451 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm);
  list<dag> ResultInstrs = [(t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3452 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm);
  list<dag> ResultInstrs = [(t2USAT imm0_31:$imm, GPRnopc:$Rn, 0)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3453 {	// Pattern Pat T2Pat
  dag PatternToMatch = (int_arm_ssat GPR:$a, imm1_32:$pos);
  list<dag> ResultInstrs = [(t2SSAT imm1_32:$pos, GPR:$a, 0)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3454 {	// Pattern Pat T2Pat
  dag PatternToMatch = (int_arm_usat GPR:$a, imm0_31:$pos);
  list<dag> ResultInstrs = [(t2USAT imm0_31:$pos, GPR:$a, 0)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3455 {	// Pattern Pat T2Pat
  dag PatternToMatch = (int_arm_ssat16 GPR:$a, imm1_16:$pos);
  list<dag> ResultInstrs = [(t2SSAT16 imm1_16:$pos, GPR:$a)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3456 {	// Pattern Pat T2Pat
  dag PatternToMatch = (int_arm_usat16 GPR:$a, imm0_15:$pos);
  list<dag> ResultInstrs = [(t2USAT16 imm0_15:$pos, GPR:$a)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3457 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsl${s}${p} $Rd, $Rm, #0";
  dag ResultInst = (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3458 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsl${s}${p}.w $Rd, $Rm, #0";
  dag ResultInst = (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3459 {	// Pattern Pat T2Pat
  dag PatternToMatch = (rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne));
  list<dag> ResultInstrs = [(t2RORrr rGPR:$lhs, rGPR:$rhs)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_346 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_81, anonymous_163];
  string NAME = ?;
}
def anonymous_3460 {	// SDPatternOperator PatFrag BinOpFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (or node:$LHS, (not node:$RHS));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_3461 {	// Pattern Pat T2Pat
  dag PatternToMatch = (and rGPR:$src, t2_so_imm_not:$imm);
  list<dag> ResultInstrs = [(t2BICri rGPR:$src, t2_so_imm_not:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 1;
  string NAME = ?;
}
def anonymous_3462 {	// Pattern Pat T2Pat
  dag PatternToMatch = (and top16Zero:$src, t2_so_imm_notSext:$imm);
  list<dag> ResultInstrs = [(t2BICri rGPR:$src, t2_so_imm_notSext:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3463 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (or rGPR:$src, t2_so_imm_not:$imm);
  list<dag> ResultInstrs = [(t2ORNri rGPR:$src, t2_so_imm_not:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3464 {	// Pattern Pat T2Pat
  dag PatternToMatch = (t2_so_imm_not:src);
  list<dag> ResultInstrs = [(t2MVNi t2_so_imm_not:$src)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3465 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (mul sext_16_node:$Rm, sext_16_node:$Rn);
  list<dag> ResultInstrs = [(t2SMULBB rGPR:$Rm, rGPR:$Rn)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3466 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16)));
  list<dag> ResultInstrs = [(t2SMULBT rGPR:$Rn, rGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3467 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm);
  list<dag> ResultInstrs = [(t2SMULTB rGPR:$Rn, rGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3468 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smulbb rGPR:$Rn, rGPR:$Rm);
  list<dag> ResultInstrs = [(t2SMULBB rGPR:$Rn, rGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3469 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smulbt rGPR:$Rn, rGPR:$Rm);
  list<dag> ResultInstrs = [(t2SMULBT rGPR:$Rn, rGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_347 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_81, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3470 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smultb rGPR:$Rn, rGPR:$Rm);
  list<dag> ResultInstrs = [(t2SMULTB rGPR:$Rn, rGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3471 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smultt rGPR:$Rn, rGPR:$Rm);
  list<dag> ResultInstrs = [(t2SMULTT rGPR:$Rn, rGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3472 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smulwb rGPR:$Rn, rGPR:$Rm);
  list<dag> ResultInstrs = [(t2SMULWB rGPR:$Rn, rGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3473 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smulwt rGPR:$Rn, rGPR:$Rm);
  list<dag> ResultInstrs = [(t2SMULWT rGPR:$Rn, rGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3474 {	// Pattern Pat Thumb2DSPMulPat
  dag PatternToMatch = (add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm));
  list<dag> ResultInstrs = [(t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)];
  list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3475 {	// Pattern Pat Thumb2DSPMulPat
  dag PatternToMatch = (add rGPR:$Ra, (mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16))));
  list<dag> ResultInstrs = [(t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)];
  list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3476 {	// Pattern Pat Thumb2DSPMulPat
  dag PatternToMatch = (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm));
  list<dag> ResultInstrs = [(t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)];
  list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3477 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(t2SMLABB GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3478 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(t2SMLABT GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3479 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(t2SMLATB GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_348 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_81, anonymous_163];
  string NAME = ?;
}
def anonymous_3480 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(t2SMLATT GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3481 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(t2SMLAWB GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3482 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc);
  list<dag> ResultInstrs = [(t2SMLAWT GPR:$a, GPR:$b, GPR:$acc)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3483 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi);
  list<dag> ResultInstrs = [(t2SMLALBB ?:$Rn, ?:$Rm, ?:$RLo, ?:$RHi)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3484 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi);
  list<dag> ResultInstrs = [(t2SMLALBT ?:$Rn, ?:$Rm, ?:$RLo, ?:$RHi)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3485 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi);
  list<dag> ResultInstrs = [(t2SMLALTB ?:$Rn, ?:$Rm, ?:$RLo, ?:$RHi)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3486 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi);
  list<dag> ResultInstrs = [(t2SMLALTT ?:$Rn, ?:$Rm, ?:$RLo, ?:$RHi)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3487 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (ARMSmlald rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi);
  list<dag> ResultInstrs = [(t2SMLALD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3488 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (ARMSmlaldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi);
  list<dag> ResultInstrs = [(t2SMLALDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3489 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (ARMSmlsld rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi);
  list<dag> ResultInstrs = [(t2SMLSLD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_349 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3490 {	// Pattern Pat Thumb2DSPPat
  dag PatternToMatch = (ARMSmlsldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi);
  list<dag> ResultInstrs = [(t2SMLSLDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3491 {	// Pattern Pat T2Pat
  dag PatternToMatch = (or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)), (and (srl rGPR:$Rm, (i32 8)), 255));
  list<dag> ResultInstrs = [(t2REVSH rGPR:$Rm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3492 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (or (and rGPR:$src1, 65535), (and rGPR:$src2, 4294901760));
  list<dag> ResultInstrs = [(t2PKHBT rGPR:$src1, rGPR:$src2, 0)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3493 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (or (and rGPR:$src1, 65535), (shl rGPR:$src2, imm16_31:$sh));
  list<dag> ResultInstrs = [(t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3494 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (or (and rGPR:$src1, 4294901760), (srl rGPR:$src2, imm16:$sh));
  list<dag> ResultInstrs = [(t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3495 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (or (and rGPR:$src1, 4294901760), (sra rGPR:$src2, imm16_31:$sh));
  list<dag> ResultInstrs = [(t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3496 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (or (and rGPR:$src1, 4294901760), (and (srl rGPR:$src2, imm1_15:$sh), 65535));
  list<dag> ResultInstrs = [(t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3497 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm);
  list<dag> ResultInstrs = [(t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3498 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMcmpZ GPRnopc:$lhs, rGPR:$rhs);
  list<dag> ResultInstrs = [(t2CMPrr GPRnopc:$lhs, rGPR:$rhs)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3499 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs);
  list<dag> ResultInstrs = [(t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_35 {	// AMDGPUArg
  LLVMType Type = llvm_anyfloat_ty;
  string Name = "dsdh";
  string NAME = ?;
}
def anonymous_350 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_269, anonymous_352];
  string NAME = ?;
}
def anonymous_3500 {	// InstAlias Requires t2InstAlias
  string AsmString = "cmn${p} $Rn, $imm";
  dag ResultInst = (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3501 {	// InstAlias Requires t2InstAlias
  string AsmString = "cmn${p} $Rn, $shift";
  dag ResultInst = (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3502 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMcmp GPR:$src, t2_so_imm_neg:$imm);
  list<dag> ResultInstrs = [(t2CMNri GPR:$src, t2_so_imm_neg:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3503 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm);
  list<dag> ResultInstrs = [(t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3504 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (and (ldrex_1 addr_offset_none:$addr), 255);
  list<dag> ResultInstrs = [(t2LDREXB addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3505 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (and (ldrex_2 addr_offset_none:$addr), 65535);
  list<dag> ResultInstrs = [(t2LDREXH addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3506 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (strex_1 (and GPR:$Rt, 255), addr_offset_none:$addr);
  list<dag> ResultInstrs = [(t2STREXB GPR:$Rt, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3507 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (strex_2 (and GPR:$Rt, 65535), addr_offset_none:$addr);
  list<dag> ResultInstrs = [(t2STREXH GPR:$Rt, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3508 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (and (ldaex_1 addr_offset_none:$addr), 255);
  list<dag> ResultInstrs = [(t2LDAEXB addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3509 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (and (ldaex_2 addr_offset_none:$addr), 65535);
  list<dag> ResultInstrs = [(t2LDAEXH addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_351 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_269, anonymous_352];
  string NAME = ?;
}
def anonymous_3510 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (stlex_1 (and GPR:$Rt, 255), addr_offset_none:$addr);
  list<dag> ResultInstrs = [(t2STLEXB GPR:$Rt, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3511 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (stlex_2 (and GPR:$Rt, 65535), addr_offset_none:$addr);
  list<dag> ResultInstrs = [(t2STLEXH GPR:$Rt, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3512 {	// InstAlias Requires t2InstAlias
  string AsmString = "cps$imod.w $iflags, $mode";
  dag ResultInst = (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3513 {	// InstAlias Requires t2InstAlias
  string AsmString = "cps.w $mode";
  dag ResultInst = (t2CPS1p imm0_31:$mode);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3514 {	// InstAlias Requires t2InstAlias
  string AsmString = "hint$p $imm";
  dag ResultInst = (t2HINT imm0_239:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3515 {	// InstAlias Requires t2InstAlias
  string AsmString = "nop$p.w";
  dag ResultInst = (t2HINT 0, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3516 {	// InstAlias Requires t2InstAlias
  string AsmString = "yield$p.w";
  dag ResultInst = (t2HINT 1, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3517 {	// InstAlias Requires t2InstAlias
  string AsmString = "wfe$p.w";
  dag ResultInst = (t2HINT 2, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3518 {	// InstAlias Requires t2InstAlias
  string AsmString = "wfi$p.w";
  dag ResultInst = (t2HINT 3, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3519 {	// InstAlias Requires t2InstAlias
  string AsmString = "sev$p.w";
  dag ResultInst = (t2HINT 4, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_352 {	// AMDGPUArg
  LLVMType Type = anonymous_191;
  string Name = "r";
  string NAME = ?;
}
def anonymous_3520 {	// InstAlias Requires t2InstAlias
  string AsmString = "sevl$p.w";
  dag ResultInst = (t2HINT 5, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2, HasV8];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3521 {	// InstAlias Requires t2InstAlias
  string AsmString = "esb$p.w";
  dag ResultInst = (t2HINT 16, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2, HasRAS];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3522 {	// InstAlias Requires t2InstAlias
  string AsmString = "esb$p";
  dag ResultInst = (t2HINT 16, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, HasRAS];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3523 {	// InstAlias Requires t2InstAlias
  string AsmString = "csdb$p.w";
  dag ResultInst = (t2HINT 20, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3524 {	// InstAlias Requires t2InstAlias
  string AsmString = "csdb$p";
  dag ResultInst = (t2HINT 20, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3525 {	// InstAlias Requires t2InstAlias
  string AsmString = "srsdb${p} $mode";
  dag ResultInst = (t2SRSDB imm0_31:$mode, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3526 {	// InstAlias Requires t2InstAlias
  string AsmString = "srsdb${p} $mode!";
  dag ResultInst = (t2SRSDB_UPD imm0_31:$mode, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3527 {	// InstAlias Requires t2InstAlias
  string AsmString = "srsia${p} $mode";
  dag ResultInst = (t2SRSIA imm0_31:$mode, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3528 {	// InstAlias Requires t2InstAlias
  string AsmString = "srsia${p} $mode!";
  dag ResultInst = (t2SRSIA_UPD imm0_31:$mode, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3529 {	// InstAlias Requires t2InstAlias
  string AsmString = "hvc	$imm16";
  dag ResultInst = (t2HVC imm0_65535:$imm16);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_353 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3530 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (ARMWrapperPIC tglobaltlsaddr:$dst);
  list<dag> ResultInstrs = [(t2MOV_ga_pcrel tglobaltlsaddr:$dst)];
  list<Predicate> Predicates = [IsThumb2, UseMovtInPic];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3531 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (ARMWrapper tglobaltlsaddr:$dst);
  list<dag> ResultInstrs = [(t2MOVi32imm tglobaltlsaddr:$dst)];
  list<Predicate> Predicates = [IsThumb2, UseMovt];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3532 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMWrapper tconstpool:$dst);
  list<dag> ResultInstrs = [(t2LEApcrel tconstpool:$dst)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3533 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (ARMWrapper texternalsym:$dst);
  list<dag> ResultInstrs = [(t2MOVi32imm texternalsym:$dst)];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline, UseMovt];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3534 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (ARMWrapper tglobaladdr:$dst);
  list<dag> ResultInstrs = [(t2MOVi32imm tglobaladdr:$dst)];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline, UseMovt];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3535 {	// Pattern Pat T2Pat
  dag PatternToMatch = (ARMWrapperJT tjumptable:$dst);
  list<dag> ResultInstrs = [(t2LEApcrelJT tjumptable:$dst)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3536 {	// InstAlias Requires t2InstAlias
  string AsmString = "mrs${p} $Rd, cpsr";
  dag ResultInst = (t2MRS_AR GPR:$Rd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3537 {	// InstAlias Requires t2InstAlias
  string AsmString = "mcr${p} $cop, $opc1, $Rt, $CRn, $CRm";
  dag ResultInst = (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3538 {	// InstAlias Requires t2InstAlias
  string AsmString = "mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm";
  dag ResultInst = (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3539 {	// InstAlias Requires t2InstAlias
  string AsmString = "mrc${p} $cop, $opc1, $Rt, $CRn, $CRm";
  dag ResultInst = (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_354 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_352];
  string NAME = ?;
}
def anonymous_3540 {	// InstAlias Requires t2InstAlias
  string AsmString = "mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm";
  dag ResultInst = (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3541 {	// Pattern Pat T2v6Pat
  dag PatternToMatch = (int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2);
  list<dag> ResultInstrs = [(t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Predicate> Predicates = [IsThumb2, HasV6T2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3542 {	// Pattern Pat T2v6Pat
  dag PatternToMatch = (int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2);
  list<dag> ResultInstrs = [(t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Predicate> Predicates = [IsThumb2, HasV6T2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3543 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (and rGPR:$Rm, 255);
  list<dag> ResultInstrs = [(t2UXTB rGPR:$Rm, 0)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3544 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (and rGPR:$Rm, 65535);
  list<dag> ResultInstrs = [(t2UXTH rGPR:$Rm, 0)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3545 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (and rGPR:$Rm, 16711935);
  list<dag> ResultInstrs = [(t2UXTB16 rGPR:$Rm, 0)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3546 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (add rGPR:$Rn, (and rGPR:$Rm, 255));
  list<dag> ResultInstrs = [(t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3547 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (add rGPR:$Rn, (and rGPR:$Rm, 65535));
  list<dag> ResultInstrs = [(t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 16;
  string NAME = ?;
}
def anonymous_3548 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (sext_inreg rGPR:$Src, i8);
  list<dag> ResultInstrs = [(t2SXTB rGPR:$Src, 0)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3549 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (sext_inreg rGPR:$Src, i16);
  list<dag> ResultInstrs = [(t2SXTH rGPR:$Src, 0)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_355 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3550 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8));
  list<dag> ResultInstrs = [(t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3551 {	// Pattern Pat T2Pat Requires
  dag PatternToMatch = (add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16));
  list<dag> ResultInstrs = [(t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3552 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_8 t2addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(t2LDRBi12 t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3553 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_8 t2addrmode_negimm8:$addr);
  list<dag> ResultInstrs = [(t2LDRBi8 t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3554 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_8 t2addrmode_so_reg:$addr);
  list<dag> ResultInstrs = [(t2LDRBs t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3555 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_16 t2addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(t2LDRHi12 t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3556 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_16 t2addrmode_negimm8:$addr);
  list<dag> ResultInstrs = [(t2LDRHi8 t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3557 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_16 t2addrmode_so_reg:$addr);
  list<dag> ResultInstrs = [(t2LDRHs t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3558 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_32 t2addrmode_imm12:$addr);
  list<dag> ResultInstrs = [(t2LDRi12 t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3559 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_32 t2addrmode_negimm8:$addr);
  list<dag> ResultInstrs = [(t2LDRi8 t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_356 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_352];
  string NAME = ?;
}
def anonymous_3560 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_32 t2addrmode_so_reg:$addr);
  list<dag> ResultInstrs = [(t2LDRs t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3561 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_8 t2addrmode_imm12:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3562 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3563 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STRBs GPR:$val, t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3564 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_16 t2addrmode_imm12:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3565 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3566 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STRHs GPR:$val, t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3567 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_32 t2addrmode_imm12:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STRi12 GPR:$val, t2addrmode_imm12:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3568 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3569 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STRs GPR:$val, t2addrmode_so_reg:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_357 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3570 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_acquire_8 addr_offset_none:$addr);
  list<dag> ResultInstrs = [(t2LDAB addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3571 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_acquire_16 addr_offset_none:$addr);
  list<dag> ResultInstrs = [(t2LDAH addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3572 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_load_acquire_32 addr_offset_none:$addr);
  list<dag> ResultInstrs = [(t2LDA addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3573 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_release_8 addr_offset_none:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STLB GPR:$val, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3574 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_release_16 addr_offset_none:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STLH GPR:$val, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3575 {	// Pattern Pat T2Pat
  dag PatternToMatch = (atomic_store_release_32 addr_offset_none:$addr, GPR:$val);
  list<dag> ResultInstrs = [(t2STL GPR:$val, addr_offset_none:$addr)];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 8;
  string NAME = ?;
}
def anonymous_3576 {	// InstAlias Requires t2InstAlias
  string AsmString = "adc${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3577 {	// InstAlias Requires t2InstAlias
  string AsmString = "adc${s}${p} $Rd, $Rn, $ShiftedRm";
  dag ResultInst = (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3578 {	// InstAlias Requires t2InstAlias
  string AsmString = "sbc${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3579 {	// InstAlias Requires t2InstAlias
  string AsmString = "sbc${s}${p} $Rd, $Rn, $ShiftedRm";
  dag ResultInst = (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_358 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_352];
  string NAME = ?;
}
def anonymous_3580 {	// InstAlias Requires t2InstAlias
  string AsmString = "add${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3581 {	// InstAlias Requires t2InstAlias
  string AsmString = "add${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3582 {	// InstAlias Requires t2InstAlias
  string AsmString = "add${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3583 {	// InstAlias Requires t2InstAlias
  string AsmString = "add${s}${p} $Rd, $Rn, $ShiftedRm";
  dag ResultInst = (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3584 {	// InstAlias Requires t2InstAlias
  string AsmString = "add${s}${p} $Rdn, $imm";
  dag ResultInst = (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3585 {	// InstAlias Requires t2InstAlias
  string AsmString = "add${p} $Rdn, $imm";
  dag ResultInst = (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3586 {	// InstAlias Requires t2InstAlias
  string AsmString = "add${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3587 {	// InstAlias Requires t2InstAlias
  string AsmString = "add${s}${p} $Rdn, $ShiftedRm";
  dag ResultInst = (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3588 {	// InstAlias Requires t2InstSubst
  string AsmString = "add${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3589 {	// InstAlias Requires t2InstSubst
  string AsmString = "add${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_359 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3590 {	// InstAlias Requires t2InstSubst
  string AsmString = "add${s}${p} $Rdn, $imm";
  dag ResultInst = (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3591 {	// InstAlias Requires t2InstSubst
  string AsmString = "add${p} $Rdn, $imm";
  dag ResultInst = (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3592 {	// InstAlias Requires t2InstSubst
  string AsmString = "add${s}${p}.w $Rd, $Rn, $imm";
  dag ResultInst = (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3593 {	// InstAlias Requires t2InstSubst
  string AsmString = "addw${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3594 {	// InstAlias Requires t2InstSubst
  string AsmString = "add${s}${p}.w $Rdn, $imm";
  dag ResultInst = (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3595 {	// InstAlias Requires t2InstSubst
  string AsmString = "addw${p} $Rdn, $imm";
  dag ResultInst = (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3596 {	// InstAlias Requires t2InstAlias
  string AsmString = "sub${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3597 {	// InstAlias Requires t2InstAlias
  string AsmString = "sub${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3598 {	// InstAlias Requires t2InstAlias
  string AsmString = "sub${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3599 {	// InstAlias Requires t2InstAlias
  string AsmString = "sub${s}${p} $Rd, $Rn, $ShiftedRm";
  dag ResultInst = (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_36 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "dsdv";
  string NAME = ?;
}
def anonymous_360 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  string NAME = ?;
}
def anonymous_3600 {	// InstAlias Requires t2InstAlias
  string AsmString = "sub${s}${p} $Rdn, $imm";
  dag ResultInst = (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3601 {	// InstAlias Requires t2InstAlias
  string AsmString = "sub${p} $Rdn, $imm";
  dag ResultInst = (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3602 {	// InstAlias Requires t2InstAlias
  string AsmString = "sub${s}${p}.w $Rdn, $Rm";
  dag ResultInst = (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3603 {	// InstAlias Requires t2InstAlias
  string AsmString = "sub${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3604 {	// InstAlias Requires t2InstAlias
  string AsmString = "sub${s}${p} $Rdn, $ShiftedRm";
  dag ResultInst = (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3605 {	// InstAlias Requires t2InstAlias
  string AsmString = "cmn${p} $Rn, $Rm";
  dag ResultInst = (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3606 {	// InstAlias Requires t2InstAlias
  string AsmString = "teq${p} $Rn, $Rm";
  dag ResultInst = (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3607 {	// InstAlias Requires t2InstAlias
  string AsmString = "tst${p} $Rn, $Rm";
  dag ResultInst = (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3608 {	// InstAlias Requires
  string AsmString = "dmb${p}";
  dag ResultInst = (t2DMB 15, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDB];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3609 {	// InstAlias Requires
  string AsmString = "dsb${p}";
  dag ResultInst = (t2DSB 15, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDB];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_361 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  string NAME = ?;
}
def anonymous_3610 {	// InstAlias Requires
  string AsmString = "isb${p}";
  dag ResultInst = (t2ISB 15, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDB];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3611 {	// InstAlias Requires
  string AsmString = "dfb${p}";
  dag ResultInst = (t2DSB 12, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [HasDFB];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3612 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldr${p} $Rt, $addr";
  dag ResultInst = (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3613 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrb${p} $Rt, $addr";
  dag ResultInst = (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3614 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrh${p} $Rt, $addr";
  dag ResultInst = (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3615 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrsb${p} $Rt, $addr";
  dag ResultInst = (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3616 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrsh${p} $Rt, $addr";
  dag ResultInst = (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3617 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldr${p} $Rt, $addr";
  dag ResultInst = (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3618 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrb${p} $Rt, $addr";
  dag ResultInst = (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3619 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrh${p} $Rt, $addr";
  dag ResultInst = (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_362 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3620 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrsb${p} $Rt, $addr";
  dag ResultInst = (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3621 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrsh${p} $Rt, $addr";
  dag ResultInst = (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3622 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldr${p} $Rt, $addr";
  dag ResultInst = (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3623 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrb${p} $Rt, $addr";
  dag ResultInst = (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3624 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrh${p} $Rt, $addr";
  dag ResultInst = (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3625 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrsb${p} $Rt, $addr";
  dag ResultInst = (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3626 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrsh${p} $Rt, $addr";
  dag ResultInst = (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3627 {	// InstAlias Requires t2InstAlias
  string AsmString = "mvn${s}${p}.w $Rd, $imm";
  dag ResultInst = (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3628 {	// InstAlias Requires t2InstAlias
  string AsmString = "mvn${s}${p} $Rd, $Rm";
  dag ResultInst = (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3629 {	// InstAlias Requires t2InstAlias
  string AsmString = "mvn${s}${p} $Rd, $ShiftedRm";
  dag ResultInst = (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_363 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  string NAME = ?;
}
def anonymous_3630 {	// InstAlias Requires
  string AsmString = "pkhbt${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3631 {	// InstAlias Requires
  string AsmString = "pkhtb${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3632 {	// InstAlias Requires t2InstAlias
  string AsmString = "push${p}.w $regs";
  dag ResultInst = (t2STMDB_UPD SP, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3633 {	// InstAlias Requires t2InstAlias
  string AsmString = "push${p} $regs";
  dag ResultInst = (t2STMDB_UPD SP, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3634 {	// InstAlias Requires t2InstAlias
  string AsmString = "pop${p}.w $regs";
  dag ResultInst = (t2LDMIA_UPD SP, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3635 {	// InstAlias Requires t2InstAlias
  string AsmString = "pop${p} $regs";
  dag ResultInst = (t2LDMIA_UPD SP, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3636 {	// InstAlias Requires t2InstAlias
  string AsmString = "stm${p} $Rn, $regs";
  dag ResultInst = (t2STMIA GPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3637 {	// InstAlias Requires t2InstAlias
  string AsmString = "stm${p} $Rn!, $regs";
  dag ResultInst = (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3638 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldm${p} $Rn, $regs";
  dag ResultInst = (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3639 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldm${p} $Rn!, $regs";
  dag ResultInst = (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_364 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3640 {	// InstAlias Requires t2InstAlias
  string AsmString = "stmdb${p}.w $Rn, $regs";
  dag ResultInst = (t2STMDB GPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3641 {	// InstAlias Requires t2InstAlias
  string AsmString = "stmdb${p}.w $Rn!, $regs";
  dag ResultInst = (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3642 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldmdb${p}.w $Rn, $regs";
  dag ResultInst = (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3643 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldmdb${p}.w $Rn!, $regs";
  dag ResultInst = (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3644 {	// InstAlias Requires t2InstAlias
  string AsmString = "rev${p} $Rd, $Rm";
  dag ResultInst = (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3645 {	// InstAlias Requires t2InstAlias
  string AsmString = "rev16${p} $Rd, $Rm";
  dag ResultInst = (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3646 {	// InstAlias Requires t2InstAlias
  string AsmString = "revsh${p} $Rd, $Rm";
  dag ResultInst = (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3647 {	// InstAlias Requires t2InstAlias
  string AsmString = "rsb${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3648 {	// InstAlias Requires t2InstAlias
  string AsmString = "rsb${s}${p} $Rdn, $imm";
  dag ResultInst = (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3649 {	// InstAlias Requires t2InstAlias
  string AsmString = "rsb${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_365 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  string NAME = ?;
}
def anonymous_3650 {	// InstAlias Requires t2InstAlias
  string AsmString = "rsb${s}${p} $Rdn, $ShiftedRm";
  dag ResultInst = (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3651 {	// InstAlias Requires t2InstAlias
  string AsmString = "ssat${p} $Rd, $sat_imm, $Rn";
  dag ResultInst = (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3652 {	// InstAlias Requires t2InstAlias
  string AsmString = "usat${p} $Rd, $sat_imm, $Rn";
  dag ResultInst = (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3653 {	// InstAlias Requires t2InstAlias
  string AsmString = "stm${p} $Rn, $regs";
  dag ResultInst = (t2STMIA GPR:$Rn, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3654 {	// InstAlias Requires t2InstAlias
  string AsmString = "str${p} $Rt, $addr";
  dag ResultInst = (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3655 {	// InstAlias Requires t2InstAlias
  string AsmString = "strb${p} $Rt, $addr";
  dag ResultInst = (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3656 {	// InstAlias Requires t2InstAlias
  string AsmString = "strh${p} $Rt, $addr";
  dag ResultInst = (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3657 {	// InstAlias Requires t2InstAlias
  string AsmString = "str${p} $Rt, $addr";
  dag ResultInst = (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3658 {	// InstAlias Requires t2InstAlias
  string AsmString = "strb${p} $Rt, $addr";
  dag ResultInst = (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3659 {	// InstAlias Requires t2InstAlias
  string AsmString = "strh${p} $Rt, $addr";
  dag ResultInst = (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_366 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3660 {	// InstAlias Requires
  string AsmString = "sxtab${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3661 {	// InstAlias Requires
  string AsmString = "sxtah${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3662 {	// InstAlias Requires
  string AsmString = "sxtab16${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3663 {	// InstAlias Requires
  string AsmString = "sxtb16${p} $Rd, $Rm";
  dag ResultInst = (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3664 {	// InstAlias Requires t2InstAlias
  string AsmString = "sxtb${p} $Rd, $Rm";
  dag ResultInst = (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3665 {	// InstAlias Requires t2InstAlias
  string AsmString = "sxth${p} $Rd, $Rm";
  dag ResultInst = (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3666 {	// InstAlias Requires t2InstAlias
  string AsmString = "sxtb${p}.w $Rd, $Rm";
  dag ResultInst = (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3667 {	// InstAlias Requires t2InstAlias
  string AsmString = "sxth${p}.w $Rd, $Rm";
  dag ResultInst = (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3668 {	// InstAlias Requires
  string AsmString = "uxtab${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3669 {	// InstAlias Requires
  string AsmString = "uxtah${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_367 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  string NAME = ?;
}
def anonymous_3670 {	// InstAlias Requires
  string AsmString = "uxtab16${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3671 {	// InstAlias Requires
  string AsmString = "uxtb16${p} $Rd, $Rm";
  dag ResultInst = (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3672 {	// InstAlias Requires t2InstAlias
  string AsmString = "uxtb${p} $Rd, $Rm";
  dag ResultInst = (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3673 {	// InstAlias Requires t2InstAlias
  string AsmString = "uxth${p} $Rd, $Rm";
  dag ResultInst = (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3674 {	// InstAlias Requires t2InstAlias
  string AsmString = "uxtb${p}.w $Rd, $Rm";
  dag ResultInst = (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3675 {	// InstAlias Requires t2InstAlias
  string AsmString = "uxth${p}.w $Rd, $Rm";
  dag ResultInst = (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3676 {	// InstAlias Requires t2InstAlias
  string AsmString = "uxtb${p} $Rd, $Rm$rot";
  dag ResultInst = (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3677 {	// InstAlias Requires
  string AsmString = "uxtb16${p} $Rd, $Rm$rot";
  dag ResultInst = (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3678 {	// InstAlias Requires t2InstAlias
  string AsmString = "uxth${p} $Rd, $Rm$rot";
  dag ResultInst = (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3679 {	// InstAlias Requires t2InstAlias
  string AsmString = "sxtb${p} $Rd, $Rm$rot";
  dag ResultInst = (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_368 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_81, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_332, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_333, anonymous_205];
  string NAME = ?;
}
def anonymous_3680 {	// InstAlias Requires
  string AsmString = "sxtb16${p} $Rd, $Rm$rot";
  dag ResultInst = (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3681 {	// InstAlias Requires t2InstAlias
  string AsmString = "sxth${p} $Rd, $Rm$rot";
  dag ResultInst = (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3682 {	// InstAlias Requires t2InstSubst
  string AsmString = "mov${p} $Rd, $imm";
  dag ResultInst = (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3683 {	// InstAlias Requires t2InstSubst
  string AsmString = "mvn${s}${p} $Rd, $imm";
  dag ResultInst = (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3684 {	// InstAlias Requires t2InstSubst
  string AsmString = "bic${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3685 {	// InstAlias Requires t2InstSubst
  string AsmString = "bic${s}${p} $Rdn, $imm";
  dag ResultInst = (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3686 {	// InstAlias Requires t2InstSubst
  string AsmString = "and${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3687 {	// InstAlias Requires t2InstSubst
  string AsmString = "and${s}${p} $Rdn, $imm";
  dag ResultInst = (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3688 {	// InstAlias Requires t2InstSubst
  string AsmString = "orn${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3689 {	// InstAlias Requires t2InstSubst
  string AsmString = "orn${s}${p} $Rdn, $imm";
  dag ResultInst = (t2ORRri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_369 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_81, anonymous_203];
  string NAME = ?;
}
def anonymous_3690 {	// InstAlias Requires t2InstSubst
  string AsmString = "orr${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3691 {	// InstAlias Requires t2InstSubst
  string AsmString = "orr${s}${p} $Rdn, $imm";
  dag ResultInst = (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3692 {	// InstAlias Requires t2InstSubst
  string AsmString = "add${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3693 {	// InstAlias Requires t2InstSubst
  string AsmString = "add${s}${p} $Rd, $imm";
  dag ResultInst = (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3694 {	// InstAlias Requires t2InstSubst
  string AsmString = "cmp${p} $Rd, $imm";
  dag ResultInst = (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3695 {	// InstAlias Requires t2InstSubst
  string AsmString = "cmn${p} $Rd, $imm";
  dag ResultInst = (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3696 {	// InstAlias Requires t2InstAlias
  string AsmString = "mul${p} $Rn, $Rm";
  dag ResultInst = (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3697 {	// InstAlias Requires t2InstAlias
  string AsmString = "neg${s}${p} $Rd, $Rm";
  dag ResultInst = (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3698 {	// InstAlias Requires t2InstAlias
  string AsmString = "mov${p}.w $Rd, $shift";
  dag ResultInst = (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3699 {	// InstAlias Requires t2InstAlias
  string AsmString = "movs${p}.w $Rd, $shift";
  dag ResultInst = (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_37 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_31, anonymous_38];
  string NAME = ?;
}
def anonymous_370 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_81, anonymous_203];
  string NAME = ?;
}
def anonymous_3700 {	// InstAlias Requires t2InstAlias
  string AsmString = "mov${p}.w $Rd, $shift";
  dag ResultInst = (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3701 {	// InstAlias Requires t2InstAlias
  string AsmString = "movs${p}.w $Rd, $shift";
  dag ResultInst = (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3702 {	// InstAlias Requires t2InstAlias
  string AsmString = "adr${p} $Rd, $addr";
  dag ResultInst = (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3703 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldr${p}.w $Rt, $addr";
  dag ResultInst = (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3704 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrb${p}.w $Rt, $addr";
  dag ResultInst = (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3705 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrh${p}.w $Rt, $addr";
  dag ResultInst = (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3706 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrsb${p}.w $Rt, $addr";
  dag ResultInst = (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3707 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldrsh${p}.w $Rt, $addr";
  dag ResultInst = (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3708 {	// InstAlias Requires t2InstAlias
  string AsmString = "add${p} $Rd, pc, $imm";
  dag ResultInst = (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3709 {	// InstAlias Requires t2InstAlias
  string AsmString = "ldr${p}.w $Rt, $immediate";
  dag ResultInst = (t2LDRConstPool GPRnopc:$Rt, const_pool_asm_imm:$immediate, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_371 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_81, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_332, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_333, anonymous_205];
  string NAME = ?;
}
def anonymous_3710 {	// InstAlias Requires t2InstAlias
  string AsmString = "pld${p} $addr";
  dag ResultInst = (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3711 {	// InstAlias Requires
  string AsmString = "pli${p} $addr";
  dag ResultInst = (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2, HasV7];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3712 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 0;
  ValueType VT = f64;
  string NAME = ?;
}
def anonymous_3713 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 2;
  ValueType VT = f64;
  string NAME = ?;
}
def anonymous_3714 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 0;
  ValueType VT = f32;
  string NAME = ?;
}
def anonymous_3715 {	// SDNodeXForm
  SDNode Opcode = fpimm;
  code XFormFunction = [{
      APFloat InVal = N->getValueAPF();
      uint32_t enc = ARM_AM::getFP16Imm(InVal);
      return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
    }];
  string NAME = ?;
}
def anonymous_3716 {	// SDNodeXForm
  SDNode Opcode = fpimm;
  code XFormFunction = [{
      APFloat InVal = N->getValueAPF();
      uint32_t enc = ARM_AM::getFP32Imm(InVal);
      return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
    }];
  string NAME = ?;
}
def anonymous_3717 {	// SDNodeXForm
  SDNode Opcode = fpimm;
  code XFormFunction = [{
      APFloat InVal = N->getValueAPF();
      uint32_t enc = ARM_AM::getFP64Imm(InVal);
      return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
    }];
  string NAME = ?;
}
def anonymous_3718 {	// MnemonicAlias
  string FromMnemonic = "vldm";
  string ToMnemonic = "vldmia";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_3719 {	// MnemonicAlias
  string FromMnemonic = "vstm";
  string ToMnemonic = "vstmia";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_372 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_81, anonymous_203];
  string NAME = ?;
}
def anonymous_3720 {	// InstAlias Requires
  string AsmString = "vpush${p} $r";
  dag ResultInst = (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3721 {	// InstAlias Requires
  string AsmString = "vpush${p} $r";
  dag ResultInst = (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3722 {	// InstAlias Requires
  string AsmString = "vpop${p} $r";
  dag ResultInst = (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3723 {	// InstAlias Requires
  string AsmString = "vpop${p} $r";
  dag ResultInst = (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3724anonymous_3102 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpush${p}.8	$r";
  dag ResultInst = (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3724anonymous_3103 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpush${p}.16	$r";
  dag ResultInst = (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3724anonymous_3104 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpush${p}.32	$r";
  dag ResultInst = (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3724anonymous_3105 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpush${p}.64	$r";
  dag ResultInst = (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3725anonymous_3102 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpush${p}.8	$r";
  dag ResultInst = (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3725anonymous_3103 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpush${p}.16	$r";
  dag ResultInst = (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3725anonymous_3104 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpush${p}.32	$r";
  dag ResultInst = (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3725anonymous_3105 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpush${p}.64	$r";
  dag ResultInst = (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3726anonymous_3102 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpop${p}.8	$r";
  dag ResultInst = (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3726anonymous_3103 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpop${p}.16	$r";
  dag ResultInst = (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3726anonymous_3104 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpop${p}.32	$r";
  dag ResultInst = (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3726anonymous_3105 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpop${p}.64	$r";
  dag ResultInst = (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3727anonymous_3102 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpop${p}.8	$r";
  dag ResultInst = (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3727anonymous_3103 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpop${p}.16	$r";
  dag ResultInst = (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3727anonymous_3104 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpop${p}.32	$r";
  dag ResultInst = (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3727anonymous_3105 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vpop${p}.64	$r";
  dag ResultInst = (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3728 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fldmeax";
  string ToMnemonic = "fldmdbx";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3729 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fldmfdx";
  string ToMnemonic = "fldmiax";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_373 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_81, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_332, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_333, anonymous_205];
  string NAME = ?;
}
def anonymous_3730 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fstmeax";
  string ToMnemonic = "fstmiax";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3731 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fstmfdx";
  string ToMnemonic = "fstmdbx";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3732 {	// Pattern Pat Requires
  dag PatternToMatch = (fmul (fneg DPR:$a), (f64 DPR:$b));
  list<dag> ResultInstrs = [(VNMULD DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [NoHonorSignDependentRounding, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3733 {	// Pattern Pat Requires
  dag PatternToMatch = (fmul (fneg SPR:$a), SPR:$b);
  list<dag> ResultInstrs = [(VNMULS SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [NoHonorSignDependentRounding];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3734 {	// Pattern Pat FullFP16Pat
  dag PatternToMatch = (f32 (fpextend HPR:$Sm));
  list<dag> ResultInstrs = [(VCVTBHS (COPY_TO_REGCLASS HPR:$Sm, SPR))];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3735 {	// Pattern Pat FP16Pat
  dag PatternToMatch = (f16_to_fp GPR:$a);
  list<dag> ResultInstrs = [(VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))];
  list<Predicate> Predicates = [HasFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3736 {	// Pattern Pat FullFP16Pat
  dag PatternToMatch = (f16 (fpround SPR:$Sm));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3737 {	// Pattern Pat FP16Pat
  dag PatternToMatch = (fp_to_f16 SPR:$a);
  list<dag> ResultInstrs = [(i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))];
  list<Predicate> Predicates = [HasFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3738 {	// Pattern Pat FullFP16Pat
  dag PatternToMatch = (f64 (fpextend HPR:$Sm));
  list<dag> ResultInstrs = [(VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3739 {	// Pattern Pat FP16Pat
  dag PatternToMatch = (f64 (f16_to_fp GPR:$a));
  list<dag> ResultInstrs = [(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))];
  list<Predicate> Predicates = [HasFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_374 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_81, anonymous_203];
  string NAME = ?;
}
def anonymous_3740 {	// Pattern Pat FullFP16Pat
  dag PatternToMatch = (f16 (fpround DPR:$Dm));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3741 {	// Pattern Pat FP16Pat
  dag PatternToMatch = (fp_to_f16 (f64 DPR:$a));
  list<dag> ResultInstrs = [(i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))];
  list<Predicate> Predicates = [HasFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_375 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_81, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_332, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_333, anonymous_205];
  string NAME = ?;
}
def anonymous_3753 {	// Pattern Pat Requires
  dag PatternToMatch = (arm_vmovsr GPR:$Rt);
  list<dag> ResultInstrs = [(VMOVSR GPR:$Rt)];
  list<Predicate> Predicates = [HasVFP2, UseVMOVSR];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3754 {	// Pattern Pat Requires
  dag PatternToMatch = (fabs (arm_fmdrr GPR:$Rl, GPR:$Rh));
  list<dag> ResultInstrs = [(VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 2147483647)))];
  list<Predicate> Predicates = [IsARM, HasV6T2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3755 {	// Pattern Pat Requires
  dag PatternToMatch = (fabs (arm_fmdrr GPR:$Rl, GPR:$Rh));
  list<dag> ResultInstrs = [(VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 2147483647)))];
  list<Predicate> Predicates = [IsThumb2, HasV6T2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3756 {	// Pattern Pat Requires
  dag PatternToMatch = (fneg (arm_fmdrr GPR:$Rl, GPR:$Rh));
  list<dag> ResultInstrs = [(VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 2147483648)))];
  list<Predicate> Predicates = [IsARM];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3757 {	// Pattern Pat Requires
  dag PatternToMatch = (fneg (arm_fmdrr GPR:$Rl, GPR:$Rh));
  list<dag> ResultInstrs = [(VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 2147483648)))];
  list<Predicate> Predicates = [IsThumb2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3758 {	// Pattern Pat VFPPat
  dag PatternToMatch = (f64 (sint_to_fp GPR:$a));
  list<dag> ResultInstrs = [(VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3759 {	// Pattern Pat VFPPat
  dag PatternToMatch = (f64 (sint_to_fp (i32 (alignedload32 addrmode5:$a))));
  list<dag> ResultInstrs = [(VSITOD (VLDRS addrmode5:$a))];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_376 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_81, anonymous_203];
  string NAME = ?;
}
def anonymous_3760 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (f32 (sint_to_fp GPR:$a));
  list<dag> ResultInstrs = [(VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3761 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a))));
  list<dag> ResultInstrs = [(VSITOS (VLDRS addrmode5:$a))];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3762 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (f16 (sint_to_fp GPR:$a));
  list<dag> ResultInstrs = [(VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3763 {	// Pattern Pat VFPPat
  dag PatternToMatch = (f64 (uint_to_fp GPR:$a));
  list<dag> ResultInstrs = [(VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3764 {	// Pattern Pat VFPPat
  dag PatternToMatch = (f64 (uint_to_fp (i32 (alignedload32 addrmode5:$a))));
  list<dag> ResultInstrs = [(VUITOD (VLDRS addrmode5:$a))];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3765 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (f32 (uint_to_fp GPR:$a));
  list<dag> ResultInstrs = [(VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3766 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a))));
  list<dag> ResultInstrs = [(VUITOS (VLDRS addrmode5:$a))];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3767 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (f16 (uint_to_fp GPR:$a));
  list<dag> ResultInstrs = [(VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3768 {	// Pattern Pat VFPPat
  dag PatternToMatch = (i32 (fp_to_sint (f64 DPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3769 {	// Pattern Pat VFPPat
  dag PatternToMatch = (alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr);
  list<dag> ResultInstrs = [(VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_377 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3770 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (i32 (fp_to_sint SPR:$a));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3771 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))), addrmode5:$ptr);
  list<dag> ResultInstrs = [(VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3772 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (i32 (fp_to_sint HPR:$a));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VTOSIZH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3773 {	// Pattern Pat VFPPat
  dag PatternToMatch = (i32 (fp_to_uint (f64 DPR:$a)));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3774 {	// Pattern Pat VFPPat
  dag PatternToMatch = (alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr);
  list<dag> ResultInstrs = [(VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3775 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (i32 (fp_to_uint SPR:$a));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3776 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))), addrmode5:$ptr);
  list<dag> ResultInstrs = [(VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3777 {	// Pattern Pat VFPNoNEONPat
  dag PatternToMatch = (i32 (fp_to_uint HPR:$a));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (VTOUIZH HPR:$a), GPR)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3778 {	// Pattern Pat Requires
  dag PatternToMatch = (fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b)));
  list<dag> ResultInstrs = [(VMLAD DPR:$dstin, DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3779 {	// Pattern Pat Requires
  dag PatternToMatch = (fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(VMLAS SPR:$dstin, SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_378 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3780 {	// Pattern Pat Requires
  dag PatternToMatch = (fadd_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b));
  list<dag> ResultInstrs = [(VMLAH HPR:$dstin, HPR:$a, HPR:$b)];
  list<Predicate> Predicates = [HasFullFP16, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3781 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b)));
  list<dag> ResultInstrs = [(VMLSD DPR:$dstin, DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3782 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(VMLSS SPR:$dstin, SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3783 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b));
  list<dag> ResultInstrs = [(VMLSH HPR:$dstin, HPR:$a, HPR:$b)];
  list<Predicate> Predicates = [HasFullFP16, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3784 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin);
  list<dag> ResultInstrs = [(VNMLAD DPR:$dstin, DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3785 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin);
  list<dag> ResultInstrs = [(VNMLAS SPR:$dstin, SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3786 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fneg (fmul_su HPR:$a, HPR:$b)), HPR:$dstin);
  list<dag> ResultInstrs = [(VNMLAH HPR:$dstin, HPR:$a, HPR:$b)];
  list<Predicate> Predicates = [HasFullFP16, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3787 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fneg DPR:$dstin), (fmul_su DPR:$a, (f64 DPR:$b)));
  list<dag> ResultInstrs = [(VNMLAD DPR:$dstin, DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3788 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(VNMLAS SPR:$dstin, SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3789 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fneg HPR:$dstin), (fmul_su HPR:$a, HPR:$b));
  list<dag> ResultInstrs = [(VNMLAH HPR:$dstin, HPR:$a, HPR:$b)];
  list<Predicate> Predicates = [HasFullFP16, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_379 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3790 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin);
  list<dag> ResultInstrs = [(VNMLSD DPR:$dstin, DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [HasVFP2, HasDPVFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3791 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin);
  list<dag> ResultInstrs = [(VNMLSS SPR:$dstin, SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3792 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fmul_su HPR:$a, HPR:$b), HPR:$dstin);
  list<dag> ResultInstrs = [(VNMLSH HPR:$dstin, HPR:$a, HPR:$b)];
  list<Predicate> Predicates = [HasFullFP16, DontUseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3793 {	// Pattern Pat Requires
  dag PatternToMatch = (fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b)));
  list<dag> ResultInstrs = [(VFMAD DPR:$dstin, DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3794 {	// Pattern Pat Requires
  dag PatternToMatch = (fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(VFMAS SPR:$dstin, SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [HasVFP4, DontUseNEONForFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3795 {	// Pattern Pat Requires
  dag PatternToMatch = (fadd_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b));
  list<dag> ResultInstrs = [(VFMAH HPR:$dstin, HPR:$a, HPR:$b)];
  list<Predicate> Predicates = [HasFullFP16, DontUseNEONForFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3796 {	// Pattern Pat Requires
  dag PatternToMatch = (f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin));
  list<dag> ResultInstrs = [(VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3797 {	// Pattern Pat Requires
  dag PatternToMatch = (f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin));
  list<dag> ResultInstrs = [(VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3798 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b)));
  list<dag> ResultInstrs = [(VFMSD DPR:$dstin, DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3799 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(VFMSS SPR:$dstin, SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [HasVFP4, DontUseNEONForFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_38 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "t";
  string NAME = ?;
}
def anonymous_380 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3800 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b));
  list<dag> ResultInstrs = [(VFMSH HPR:$dstin, HPR:$a, HPR:$b)];
  list<Predicate> Predicates = [HasFullFP16, DontUseNEONForFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3801 {	// Pattern Pat Requires
  dag PatternToMatch = (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin));
  list<dag> ResultInstrs = [(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3802 {	// Pattern Pat Requires
  dag PatternToMatch = (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin));
  list<dag> ResultInstrs = [(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3803 {	// Pattern Pat Requires
  dag PatternToMatch = (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin));
  list<dag> ResultInstrs = [(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3804 {	// Pattern Pat Requires
  dag PatternToMatch = (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin));
  list<dag> ResultInstrs = [(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3805 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin);
  list<dag> ResultInstrs = [(VFNMAD DPR:$dstin, DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3806 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin);
  list<dag> ResultInstrs = [(VFNMAS SPR:$dstin, SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [HasVFP4, DontUseNEONForFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3807 {	// Pattern Pat Requires
  dag PatternToMatch = (fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin)));
  list<dag> ResultInstrs = [(VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3808 {	// Pattern Pat Requires
  dag PatternToMatch = (fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin)));
  list<dag> ResultInstrs = [(VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3809 {	// Pattern Pat Requires
  dag PatternToMatch = (f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin)));
  list<dag> ResultInstrs = [(VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_381 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3810 {	// Pattern Pat Requires
  dag PatternToMatch = (f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin)));
  list<dag> ResultInstrs = [(VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3811 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin);
  list<dag> ResultInstrs = [(VFNMSD DPR:$dstin, DPR:$a, DPR:$b)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3812 {	// Pattern Pat Requires
  dag PatternToMatch = (fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin);
  list<dag> ResultInstrs = [(VFNMSS SPR:$dstin, SPR:$a, SPR:$b)];
  list<Predicate> Predicates = [HasVFP4, DontUseNEONForFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3813 {	// Pattern Pat Requires
  dag PatternToMatch = (f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin)));
  list<dag> ResultInstrs = [(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3814 {	// Pattern Pat Requires
  dag PatternToMatch = (f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin)));
  list<dag> ResultInstrs = [(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3815 {	// Pattern Pat Requires
  dag PatternToMatch = (fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)));
  list<dag> ResultInstrs = [(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3816 {	// Pattern Pat Requires
  dag PatternToMatch = (fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)));
  list<dag> ResultInstrs = [(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3817 {	// Pattern Pat Requires
  dag PatternToMatch = (fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)));
  list<dag> ResultInstrs = [(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)];
  list<Predicate> Predicates = [HasVFP4, HasDPVFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3818 {	// Pattern Pat Requires
  dag PatternToMatch = (fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)));
  list<dag> ResultInstrs = [(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3819 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "flds";
  string ToMnemonic = "vldr";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_382 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  string NAME = ?;
}
def anonymous_3820 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fldd";
  string ToMnemonic = "vldr";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3821 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmrs";
  string ToMnemonic = "vmov";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3822 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmsr";
  string ToMnemonic = "vmov";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3823 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fsqrts";
  string ToMnemonic = "vsqrt";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3824 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fsqrtd";
  string ToMnemonic = "vsqrt";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3825 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fadds";
  string ToMnemonic = "vadd.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3826 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "faddd";
  string ToMnemonic = "vadd.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3827 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmrdd";
  string ToMnemonic = "vmov";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3828 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmrds";
  string ToMnemonic = "vmov";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3829 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmrrd";
  string ToMnemonic = "vmov";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_383 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385];
  string NAME = ?;
}
def anonymous_3830 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmdrr";
  string ToMnemonic = "vmov";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3831 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmuls";
  string ToMnemonic = "vmul.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3832 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmuld";
  string ToMnemonic = "vmul.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3833 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fnegs";
  string ToMnemonic = "vneg.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3834 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fnegd";
  string ToMnemonic = "vneg.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3835 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "ftosizd";
  string ToMnemonic = "vcvt.s32.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3836 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "ftosid";
  string ToMnemonic = "vcvtr.s32.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3837 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "ftosizs";
  string ToMnemonic = "vcvt.s32.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3838 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "ftosis";
  string ToMnemonic = "vcvtr.s32.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3839 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "ftouizd";
  string ToMnemonic = "vcvt.u32.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_384 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "drdh";
  string NAME = ?;
}
def anonymous_3840 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "ftouid";
  string ToMnemonic = "vcvtr.u32.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3841 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "ftouizs";
  string ToMnemonic = "vcvt.u32.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3842 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "ftouis";
  string ToMnemonic = "vcvtr.u32.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3843 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fsitod";
  string ToMnemonic = "vcvt.f64.s32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3844 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fsitos";
  string ToMnemonic = "vcvt.f32.s32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3845 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fuitod";
  string ToMnemonic = "vcvt.f64.u32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3846 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fuitos";
  string ToMnemonic = "vcvt.f32.u32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3847 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fsts";
  string ToMnemonic = "vstr";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3848 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fstd";
  string ToMnemonic = "vstr";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3849 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmacd";
  string ToMnemonic = "vmla.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_385 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "drdv";
  string NAME = ?;
}
def anonymous_3850 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmacs";
  string ToMnemonic = "vmla.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3851 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fcpys";
  string ToMnemonic = "vmov.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3852 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fcpyd";
  string ToMnemonic = "vmov.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3853 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fcmps";
  string ToMnemonic = "vcmp.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3854 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fcmpd";
  string ToMnemonic = "vcmp.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3855 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fdivs";
  string ToMnemonic = "vdiv.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3856 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fdivd";
  string ToMnemonic = "vdiv.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3857 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmrx";
  string ToMnemonic = "vmrs";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3858 {	// MnemonicAlias Requires VFP2MnemonicAlias
  string FromMnemonic = "fmxr";
  string ToMnemonic = "vmsr";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasVFP2];
  string NAME = ?;
}
def anonymous_3859 {	// InstAlias Requires VFP2DPInstAlias
  string AsmString = "fcmpzd${p} $val";
  dag ResultInst = (VCMPZD DPR:$val, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_386 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "drdh";
  string NAME = ?;
}
def anonymous_3860 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "fcmpzs${p} $val";
  dag ResultInst = (VCMPZS SPR:$val, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3861 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "fmstat${p}";
  dag ResultInst = (FMSTAT pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3862 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "fadds${p} $Sd, $Sn, $Sm";
  dag ResultInst = (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3863 {	// InstAlias Requires VFP2DPInstAlias
  string AsmString = "faddd${p} $Dd, $Dn, $Dm";
  dag ResultInst = (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3864 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "fsubs${p} $Sd, $Sn, $Sm";
  dag ResultInst = (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3865 {	// InstAlias Requires VFP2DPInstAlias
  string AsmString = "fsubd${p} $Dd, $Dn, $Dm";
  dag ResultInst = (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3866 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vsqrt${p} $Sd, $Sm";
  dag ResultInst = (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3867 {	// InstAlias Requires VFP2DPInstAlias
  string AsmString = "vsqrt${p} $Dd, $Dm";
  dag ResultInst = (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2, HasDPVFP];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3868 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vldr${p}.32 $Sd, $addr";
  dag ResultInst = (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3869 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vstr${p}.32 $Sd, $addr";
  dag ResultInst = (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_387 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "drdv";
  string NAME = ?;
}
def anonymous_3870 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vldr${p}.64 $Dd, $addr";
  dag ResultInst = (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3871 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vstr${p}.64 $Dd, $addr";
  dag ResultInst = (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3872 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vmov${p}.8 $Rt, $Sn";
  dag ResultInst = (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3873 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vmov${p}.16 $Rt, $Sn";
  dag ResultInst = (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3874 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vmov${p}.32 $Rt, $Sn";
  dag ResultInst = (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3875 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vmov${p}.8 $Sn, $Rt";
  dag ResultInst = (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3876 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vmov${p}.16 $Sn, $Rt";
  dag ResultInst = (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3877 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vmov${p}.32 $Sn, $Rt";
  dag ResultInst = (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3878 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vmov${p}.f64 $Rt, $Rt2, $Dn";
  dag ResultInst = (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3879 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vmov${p}.f64 $Dn, $Rt, $Rt2";
  dag ResultInst = (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_388 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "drdh";
  string NAME = ?;
}
def anonymous_3880 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "vmov${p} $Sd, $Sm";
  dag ResultInst = (VMOVS SPR:$Sd, SPR:$Sm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3881 {	// InstAlias Requires VFP3InstAlias
  string AsmString = "fconstd${p} $Dd, $val";
  dag ResultInst = (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP3];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3882 {	// InstAlias Requires VFP3InstAlias
  string AsmString = "fconsts${p} $Sd, $val";
  dag ResultInst = (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP3];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3883 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_834, anonymous_835, anonymous_837];
  string NAME = ?;
}
def anonymous_3884 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [anonymous_846];
  string NAME = ?;
}
def anonymous_3885 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_846, anonymous_847, anonymous_3098];
  string NAME = ?;
}
def anonymous_3886 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 0;
  ValueType VT = v8i8;
  string NAME = ?;
}
def anonymous_3887 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 1;
  ValueType VT = v8i8;
  string NAME = ?;
}
def anonymous_3888 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 2;
  ValueType VT = v8i8;
  string NAME = ?;
}
def anonymous_3889 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 3;
  ValueType VT = v8i8;
  string NAME = ?;
}
def anonymous_389 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "drdv";
  string NAME = ?;
}
def anonymous_3890 {	// Pattern Pat
  dag PatternToMatch = (vector_insert (v2f32 DPR:$src), (f32 (load addrmode6:$addr)), imm:$lane);
  list<dag> ResultInstrs = [(VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3891 {	// Pattern Pat
  dag PatternToMatch = (vector_insert (v4f32 QPR:$src), (f32 (load addrmode6:$addr)), imm:$lane);
  list<dag> ResultInstrs = [(VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3892 {	// Pattern Pat
  dag PatternToMatch = (insert_subvector undef, (v1i64 DPR:$src), (i32 0));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), DPR:$src, dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3893 {	// Pattern Pat
  dag PatternToMatch = (insert_subvector undef, (v2i32 DPR:$src), (i32 0));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), DPR:$src, dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3894 {	// Pattern Pat
  dag PatternToMatch = (insert_subvector undef, (v2f32 DPR:$src), (i32 0));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), DPR:$src, dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3895 {	// Pattern Pat
  dag PatternToMatch = (insert_subvector undef, (v4i16 DPR:$src), (i32 0));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), DPR:$src, dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3896 {	// Pattern Pat
  dag PatternToMatch = (insert_subvector undef, (v4f16 DPR:$src), (i32 0));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), DPR:$src, dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3897 {	// Pattern Pat
  dag PatternToMatch = (insert_subvector (v16i8 undef), (v8i8 DPR:$src), (i32 0));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), DPR:$src, dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3898 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (NEONvdup (f32 (load addrmode6dup:$addr))));
  list<dag> ResultInstrs = [(VLD1DUPd32 addrmode6:$addr)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3899 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (NEONvdup (f32 (load addrmode6dup:$addr))));
  list<dag> ResultInstrs = [(VLD1DUPq32 addrmode6:$addr)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_39 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_33, anonymous_38];
  string NAME = ?;
}
def anonymous_390 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3900 {	// Pattern Pat
  dag PatternToMatch = (store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3901 {	// Pattern Pat
  dag PatternToMatch = (store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3902 {	// Pattern Pat Requires
  dag PatternToMatch = (f64 (hword_alignedload addrmode6:$addr));
  list<dag> ResultInstrs = [(VLD1d16 addrmode6:$addr)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3903 {	// Pattern Pat Requires
  dag PatternToMatch = (hword_alignedstore (f64 DPR:$value), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1d16 addrmode6:$addr, DPR:$value)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3904 {	// Pattern Pat Requires
  dag PatternToMatch = (f64 (byte_alignedload addrmode6:$addr));
  list<dag> ResultInstrs = [(VLD1d8 addrmode6:$addr)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3905 {	// Pattern Pat Requires
  dag PatternToMatch = (byte_alignedstore (f64 DPR:$value), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1d8 addrmode6:$addr, DPR:$value)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3906 {	// Pattern Pat Requires
  dag PatternToMatch = (f64 (non_word_alignedload addrmode6:$addr));
  list<dag> ResultInstrs = [(VLD1d64 addrmode6:$addr)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3907 {	// Pattern Pat Requires
  dag PatternToMatch = (non_word_alignedstore (f64 DPR:$value), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1d64 addrmode6:$addr, DPR:$value)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3908 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (dword_alignedload addrmode6:$addr));
  list<dag> ResultInstrs = [(VLD1q64 addrmode6:$addr)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3909 {	// Pattern Pat
  dag PatternToMatch = (dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1q64 addrmode6:$addr, QPR:$value)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_391 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  string NAME = ?;
}
def anonymous_3910 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f64 (word_alignedload addrmode6:$addr));
  list<dag> ResultInstrs = [(VLD1q32 addrmode6:$addr)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3911 {	// Pattern Pat Requires
  dag PatternToMatch = (word_alignedstore (v2f64 QPR:$value), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1q32 addrmode6:$addr, QPR:$value)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3912 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f64 (hword_alignedload addrmode6:$addr));
  list<dag> ResultInstrs = [(VLD1q16 addrmode6:$addr)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3913 {	// Pattern Pat Requires
  dag PatternToMatch = (hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1q16 addrmode6:$addr, QPR:$value)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3914 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f64 (byte_alignedload addrmode6:$addr));
  list<dag> ResultInstrs = [(VLD1q8 addrmode6:$addr)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3915 {	// Pattern Pat Requires
  dag PatternToMatch = (byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1q8 addrmode6:$addr, QPR:$value)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3916 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8)));
  list<dag> ResultInstrs = [(VADDHNv8i8 QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3917 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16)));
  list<dag> ResultInstrs = [(VADDHNv4i16 QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3918 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32)));
  list<dag> ResultInstrs = [(VADDHNv2i32 QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3919 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (mul (v8i16 QPR:$src1), (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane))));
  list<dag> ResultInstrs = [(v8i16 (VMULslv8i16 (v8i16 QPR:$src1), (v4i16 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_392 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3920 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (mul (v4i32 QPR:$src1), (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane))));
  list<dag> ResultInstrs = [(v4i32 (VMULslv4i32 (v4i32 QPR:$src1), (v2i32 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3921 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (fmul (v4f32 QPR:$src1), (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane))));
  list<dag> ResultInstrs = [(v4f32 (VMULslfq (v4f32 QPR:$src1), (v2f32 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3922 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm))));
  list<dag> ResultInstrs = [(VMULslfd DPR:$Rn, (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0), (i32 0))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3923 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm))));
  list<dag> ResultInstrs = [(VMULslfq QPR:$Rn, (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0), (i32 0))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3924 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1), (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane))));
  list<dag> ResultInstrs = [(v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1), (v4i16 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3925 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1), (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane))));
  list<dag> ResultInstrs = [(v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1), (v2i32 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3926 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1), (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane))));
  list<dag> ResultInstrs = [(v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1), (v4i16 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3927 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1), (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane))));
  list<dag> ResultInstrs = [(v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1), (v2i32 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3928 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (add (v8i16 QPR:$src1), (mul (v8i16 QPR:$src2), (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane)))));
  list<dag> ResultInstrs = [(v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), (v4i16 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3929 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (add (v4i32 QPR:$src1), (mul (v4i32 QPR:$src2), (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane)))));
  list<dag> ResultInstrs = [(v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_393 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  string NAME = ?;
}
def anonymous_3930 {	// Pattern Pat Requires
  dag PatternToMatch = (v4f32 (fadd_mlx (v4f32 QPR:$src1), (fmul_su (v4f32 QPR:$src2), (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane)))));
  list<dag> ResultInstrs = [(v4f32 (VMLAslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2), (v2f32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3931 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (int_arm_neon_vqadds (v4i16 DPR:$src1), (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))));
  list<dag> ResultInstrs = [(v4i16 (VQRDMLAHv4i16 DPR:$src1, DPR:$Vn, DPR:$Vm))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3932 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (int_arm_neon_vqadds (v2i32 DPR:$src1), (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))));
  list<dag> ResultInstrs = [(v2i32 (VQRDMLAHv2i32 DPR:$src1, DPR:$Vn, DPR:$Vm))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3933 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (int_arm_neon_vqadds (v8i16 QPR:$src1), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn), (v8i16 QPR:$Vm)))));
  list<dag> ResultInstrs = [(v8i16 (VQRDMLAHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3934 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn), (v4i32 QPR:$Vm)))));
  list<dag> ResultInstrs = [(v4i32 (VQRDMLAHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3935 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (int_arm_neon_vqadds (v4i16 DPR:$src1), (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane))))));
  list<dag> ResultInstrs = [(v4i16 (VQRDMLAHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3936 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (int_arm_neon_vqadds (v2i32 DPR:$src1), (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane))))));
  list<dag> ResultInstrs = [(v2i32 (VQRDMLAHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3937 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (int_arm_neon_vqadds (v8i16 QPR:$src1), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src2), (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))));
  list<dag> ResultInstrs = [(v8i16 (VQRDMLAHslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), (v4i16 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3938 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src2), (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))));
  list<dag> ResultInstrs = [(v4i32 (VQRDMLAHslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3939 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (int_arm_neon_vqsubs (v4i16 DPR:$src1), (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))));
  list<dag> ResultInstrs = [(v4i16 (VQRDMLSHv4i16 DPR:$src1, DPR:$Vn, DPR:$Vm))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_394 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_3940 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (int_arm_neon_vqsubs (v2i32 DPR:$src1), (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))));
  list<dag> ResultInstrs = [(v2i32 (VQRDMLSHv2i32 DPR:$src1, DPR:$Vn, DPR:$Vm))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3941 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (int_arm_neon_vqsubs (v8i16 QPR:$src1), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn), (v8i16 QPR:$Vm)))));
  list<dag> ResultInstrs = [(v8i16 (VQRDMLSHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3942 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn), (v4i32 QPR:$Vm)))));
  list<dag> ResultInstrs = [(v4i32 (VQRDMLSHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3943 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (int_arm_neon_vqsubs (v4i16 DPR:$src1), (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane))))));
  list<dag> ResultInstrs = [(v4i16 (VQRDMLSHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3944 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (int_arm_neon_vqsubs (v2i32 DPR:$src1), (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane))))));
  list<dag> ResultInstrs = [(v2i32 (VQRDMLSHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3945 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (int_arm_neon_vqsubs (v8i16 QPR:$src1), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src2), (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))));
  list<dag> ResultInstrs = [(v8i16 (VQRDMLSHslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), (v4i16 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3946 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src2), (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))));
  list<dag> ResultInstrs = [(v4i32 (VQRDMLSHslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [HasNEON, HasV8_1a];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3947 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))));
  list<dag> ResultInstrs = [(VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3948 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1), (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))));
  list<dag> ResultInstrs = [(VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3949 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane))))));
  list<dag> ResultInstrs = [(VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_395 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  string NAME = ?;
}
def anonymous_3950 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1), (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane))))));
  list<dag> ResultInstrs = [(VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3951 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (sub (v8i16 QPR:$src1), (mul (v8i16 QPR:$src2), (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane)))));
  list<dag> ResultInstrs = [(v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), (v4i16 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3952 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (sub (v4i32 QPR:$src1), (mul (v4i32 QPR:$src2), (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane)))));
  list<dag> ResultInstrs = [(v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3953 {	// Pattern Pat Requires
  dag PatternToMatch = (v4f32 (fsub_mlx (v4f32 QPR:$src1), (fmul_su (v4f32 QPR:$src2), (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane)))));
  list<dag> ResultInstrs = [(v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2), (v2f32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [HasNEON, UseFPVMLx];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3954 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)))));
  list<dag> ResultInstrs = [(VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3955 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1), (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)))));
  list<dag> ResultInstrs = [(VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3956 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane))))));
  list<dag> ResultInstrs = [(VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3957 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1), (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane))))));
  list<dag> ResultInstrs = [(VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3958 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1));
  list<dag> ResultInstrs = [(VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3959 {	// Pattern Pat Requires
  dag PatternToMatch = (v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1));
  list<dag> ResultInstrs = [(VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_396 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3960 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1));
  list<dag> ResultInstrs = [(VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3961 {	// Pattern Pat Requires
  dag PatternToMatch = (v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1));
  list<dag> ResultInstrs = [(VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [HasVFP4];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3963 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8)));
  list<dag> ResultInstrs = [(VSUBHNv8i8 QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3964 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16)));
  list<dag> ResultInstrs = [(VSUBHNv4i16 QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3965 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32)));
  list<dag> ResultInstrs = [(VSUBHNv2i32 QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3966 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vaclt${p}.f32 $Vd, $Vn, $Vm";
  dag ResultInst = (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3967 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vaclt${p}.f32 $Vd, $Vn, $Vm";
  dag ResultInst = (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3968 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vacle${p}.f32 $Vd, $Vn, $Vm";
  dag ResultInst = (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3969 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vacle${p}.f32 $Vd, $Vn, $Vm";
  dag ResultInst = (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_397 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  string NAME = ?;
}
def anonymous_3970 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vaclt${p}.f16 $Vd, $Vn, $Vm";
  dag ResultInst = (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3971 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vaclt${p}.f16 $Vd, $Vn, $Vm";
  dag ResultInst = (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3972 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vacle${p}.f16 $Vd, $Vn, $Vm";
  dag ResultInst = (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3973 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vacle${p}.f16 $Vd, $Vn, $Vm";
  dag ResultInst = (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3974 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vaclt${p}.f32 $Vd, $Vm";
  dag ResultInst = (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3975 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vaclt${p}.f32 $Vd, $Vm";
  dag ResultInst = (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3976 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vacle${p}.f32 $Vd, $Vm";
  dag ResultInst = (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3977 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vacle${p}.f32 $Vd, $Vm";
  dag ResultInst = (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3978 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vaclt${p}.f16 $Vd, $Vm";
  dag ResultInst = (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3979 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vaclt${p}.f16 $Vd, $Vm";
  dag ResultInst = (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_398 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_3980 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vacle${p}.f16 $Vd, $Vm";
  dag ResultInst = (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3981 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vacle${p}.f16 $Vd, $Vm";
  dag ResultInst = (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_3982 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (vnotd DPR:$src));
  list<dag> ResultInstrs = [(VMVNd DPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3983 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (vnotq QPR:$src));
  list<dag> ResultInstrs = [(VMVNq QPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3984 {	// Pattern Pat Requires
  dag PatternToMatch = (v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1), (v8i8 DPR:$Vn), (v8i8 DPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3985 {	// Pattern Pat Requires
  dag PatternToMatch = (v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1), (v4i16 DPR:$Vn), (v4i16 DPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3986 {	// Pattern Pat Requires
  dag PatternToMatch = (v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1), (v2i32 DPR:$Vn), (v2i32 DPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3987 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1), (v2f32 DPR:$Vn), (v2f32 DPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3988 {	// Pattern Pat Requires
  dag PatternToMatch = (v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1), (v1i64 DPR:$Vn), (v1i64 DPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3989 {	// Pattern Pat Requires
  dag PatternToMatch = (v2i32 (or (and DPR:$Vn, DPR:$Vd), (and DPR:$Vm, (vnotd DPR:$Vd))));
  list<dag> ResultInstrs = [(VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_399 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  string NAME = ?;
}
def anonymous_3990 {	// Pattern Pat Requires
  dag PatternToMatch = (v1i64 (or (and DPR:$Vn, DPR:$Vd), (and DPR:$Vm, (vnotd DPR:$Vd))));
  list<dag> ResultInstrs = [(VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3991 {	// Pattern Pat Requires
  dag PatternToMatch = (v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1), (v16i8 QPR:$Vn), (v16i8 QPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3992 {	// Pattern Pat Requires
  dag PatternToMatch = (v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1), (v8i16 QPR:$Vn), (v8i16 QPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3993 {	// Pattern Pat Requires
  dag PatternToMatch = (v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3994 {	// Pattern Pat Requires
  dag PatternToMatch = (v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1), (v4f32 QPR:$Vn), (v4f32 QPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3995 {	// Pattern Pat Requires
  dag PatternToMatch = (v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1), (v2i64 QPR:$Vn), (v2i64 QPR:$Vm)));
  list<dag> ResultInstrs = [(VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3996 {	// Pattern Pat Requires
  dag PatternToMatch = (v4i32 (or (and QPR:$Vn, QPR:$Vd), (and QPR:$Vm, (vnotq QPR:$Vd))));
  list<dag> ResultInstrs = [(VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3997 {	// Pattern Pat Requires
  dag PatternToMatch = (v2i64 (or (and QPR:$Vn, QPR:$Vd), (and QPR:$Vm, (vnotq QPR:$Vd))));
  list<dag> ResultInstrs = [(VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3998 {	// Pattern Pat
  dag PatternToMatch = (xor (v4i32 (bitconvert (v8i16 (abd_shr (v8i8 DPR:$opA), (v8i8 DPR:$opB), 15)))), (v4i32 (bitconvert (v8i16 (add (sub (zext (v8i8 DPR:$opA)), (zext (v8i8 DPR:$opB))), (v8i16 (abd_shr (v8i8 DPR:$opA), (v8i8 DPR:$opB), 15)))))));
  list<dag> ResultInstrs = [(VABDLuv8i16 DPR:$opA, DPR:$opB)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_3999 {	// Pattern Pat
  dag PatternToMatch = (xor (v4i32 (abd_shr (v4i16 DPR:$opA), (v4i16 DPR:$opB), 31)), (v4i32 (add (sub (zext (v4i16 DPR:$opA)), (zext (v4i16 DPR:$opB))), (abd_shr (v4i16 DPR:$opA), (v4i16 DPR:$opB), 31))));
  list<dag> ResultInstrs = [(VABDLuv4i32 DPR:$opA, DPR:$opB)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4 {	// IntrinsicProperty WriteOnly
  int ArgNo = 0;
  string NAME = ?;
}
def anonymous_40 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_35, anonymous_41, anonymous_36, anonymous_42];
  string NAME = ?;
}
def anonymous_400 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_4000 {	// Pattern Pat
  dag PatternToMatch = (xor (v4i32 (bitconvert (v2i64 (abd_shr (v2i32 DPR:$opA), (v2i32 DPR:$opB), 63)))), (v4i32 (bitconvert (v2i64 (add (sub (zext (v2i32 DPR:$opA)), (zext (v2i32 DPR:$opB))), (abd_shr (v2i32 DPR:$opA), (v2i32 DPR:$opB), 63))))));
  list<dag> ResultInstrs = [(VABDLuv2i64 DPR:$opA, DPR:$opB)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4001 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (NEONvshl (sext node:$LHS), node:$RHS);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_4002 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$LHS, node:$RHS);
  dag Fragment = (NEONvshl (zext node:$LHS), node:$RHS);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_4003 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8)));
  list<dag> ResultInstrs = [(VSHLLi8 DPR:$Rn, 8)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4004 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16)));
  list<dag> ResultInstrs = [(VSHLLi16 DPR:$Rn, 16)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4005 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32)));
  list<dag> ResultInstrs = [(VSHLLi32 DPR:$Rn, 32)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4006 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8)));
  list<dag> ResultInstrs = [(VSHLLi8 DPR:$Rn, 8)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4007 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16)));
  list<dag> ResultInstrs = [(VSHLLi16 DPR:$Rn, 16)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4008 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32)));
  list<dag> ResultInstrs = [(VSHLLi32 DPR:$Rn, 32)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4009 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (NEONvshl (anyext (v8i8 DPR:$Rn)), (i32 8)));
  list<dag> ResultInstrs = [(VSHLLi8 DPR:$Rn, 8)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_401 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  string NAME = ?;
}
def anonymous_4010 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (NEONvshl (anyext (v4i16 DPR:$Rn)), (i32 16)));
  list<dag> ResultInstrs = [(VSHLLi16 DPR:$Rn, 16)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4011 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (NEONvshl (anyext (v2i32 DPR:$Rn)), (i32 32)));
  list<dag> ResultInstrs = [(VSHLLi32 DPR:$Rn, 32)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4012 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$Rn, node:$amt);
  dag Fragment = (trunc (NEONvshrs node:$Rn, node:$amt));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def anonymous_4013 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt)));
  list<dag> ResultInstrs = [(VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4014 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (trunc (NEONvshru (v4i32 QPR:$Vn), shr_imm16:$amt)));
  list<dag> ResultInstrs = [(VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4015 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (trunc (NEONvshru (v2i64 QPR:$Vn), shr_imm32:$amt)));
  list<dag> ResultInstrs = [(VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4016 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (vnegd DPR:$src));
  list<dag> ResultInstrs = [(VNEGs8d DPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4017 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (vnegd DPR:$src));
  list<dag> ResultInstrs = [(VNEGs16d DPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4018 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (vnegd DPR:$src));
  list<dag> ResultInstrs = [(VNEGs32d DPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4019 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (vnegq QPR:$src));
  list<dag> ResultInstrs = [(VNEGs8q QPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_402 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_4020 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (vnegq QPR:$src));
  list<dag> ResultInstrs = [(VNEGs16q QPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4021 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (vnegq QPR:$src));
  list<dag> ResultInstrs = [(VNEGs32q QPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4022 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p} $Vd, $Vm";
  dag ResultInst = (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4023 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p} $Vd, $Vm";
  dag ResultInst = (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4028anonymous_4024 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i16 $Vd, $Vm";
  dag ResultInst = (VMOVv8i8 DPR:$Vd, anonymous_4029:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4028anonymous_4025 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i16 $Vd, $Vm";
  dag ResultInst = (VMOVv16i8 QPR:$Vd, anonymous_4029:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4028anonymous_4026 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i16 $Vd, $Vm";
  dag ResultInst = (VMOVv8i8 DPR:$Vd, anonymous_4031:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4028anonymous_4027 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i16 $Vd, $Vm";
  dag ResultInst = (VMOVv16i8 QPR:$Vd, anonymous_4031:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4029 {	// DAGOperand Operand nImmVMOVIReplicate
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_4030;
  string NAME = ?;
}
def anonymous_403 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  string NAME = ?;
}
def anonymous_4030 {	// AsmOperandClass nImmVMOVIAsmOperandReplicate
  string Name = "NEONi16vmovi8Replicate";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isNEONmovReplicate<8, 16>";
  string RenderMethod = "addNEONvmovi8ReplicateOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_4031 {	// DAGOperand Operand nImmVINVIReplicate
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_4032;
  string NAME = ?;
}
def anonymous_4032 {	// AsmOperandClass nImmVINVIAsmOperandReplicate
  string Name = "NEONi16invi8Replicate";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isNEONinvReplicate<8, 16>";
  string RenderMethod = "addNEONinvi8ReplicateOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_4033anonymous_4024 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i32 $Vd, $Vm";
  dag ResultInst = (VMOVv8i8 DPR:$Vd, anonymous_4034:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4033anonymous_4025 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i32 $Vd, $Vm";
  dag ResultInst = (VMOVv16i8 QPR:$Vd, anonymous_4034:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4033anonymous_4026 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i32 $Vd, $Vm";
  dag ResultInst = (VMOVv8i8 DPR:$Vd, anonymous_4036:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4033anonymous_4027 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i32 $Vd, $Vm";
  dag ResultInst = (VMOVv16i8 QPR:$Vd, anonymous_4036:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4034 {	// DAGOperand Operand nImmVMOVIReplicate
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_4035;
  string NAME = ?;
}
def anonymous_4035 {	// AsmOperandClass nImmVMOVIAsmOperandReplicate
  string Name = "NEONi32vmovi8Replicate";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isNEONmovReplicate<8, 32>";
  string RenderMethod = "addNEONvmovi8ReplicateOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_4036 {	// DAGOperand Operand nImmVINVIReplicate
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_4037;
  string NAME = ?;
}
def anonymous_4037 {	// AsmOperandClass nImmVINVIAsmOperandReplicate
  string Name = "NEONi32invi8Replicate";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isNEONinvReplicate<8, 32>";
  string RenderMethod = "addNEONinvi8ReplicateOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_4038anonymous_4024 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMOVv8i8 DPR:$Vd, anonymous_4039:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4038anonymous_4025 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMOVv16i8 QPR:$Vd, anonymous_4039:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4038anonymous_4026 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMOVv8i8 DPR:$Vd, anonymous_4041:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4038anonymous_4027 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMOVv16i8 QPR:$Vd, anonymous_4041:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4039 {	// DAGOperand Operand nImmVMOVIReplicate
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_4040;
  string NAME = ?;
}
def anonymous_404 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_4040 {	// AsmOperandClass nImmVMOVIAsmOperandReplicate
  string Name = "NEONi64vmovi8Replicate";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isNEONmovReplicate<8, 64>";
  string RenderMethod = "addNEONvmovi8ReplicateOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_4041 {	// DAGOperand Operand nImmVINVIReplicate
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_4042;
  string NAME = ?;
}
def anonymous_4042 {	// AsmOperandClass nImmVINVIAsmOperandReplicate
  string Name = "NEONi64invi8Replicate";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isNEONinvReplicate<8, 64>";
  string RenderMethod = "addNEONinvi8ReplicateOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_4047anonymous_4043 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i32 $Vd, $Vm";
  dag ResultInst = (VMOVv4i16 DPR:$Vd, anonymous_4048:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4047anonymous_4044 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i32 $Vd, $Vm";
  dag ResultInst = (VMOVv8i16 QPR:$Vd, anonymous_4048:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4047anonymous_4045 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i32 $Vd, $Vm";
  dag ResultInst = (VMVNv4i16 DPR:$Vd, anonymous_4048:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4047anonymous_4046 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i32 $Vd, $Vm";
  dag ResultInst = (VMVNv8i16 QPR:$Vd, anonymous_4048:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4048 {	// DAGOperand Operand nImmVMOVIReplicate
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_4049;
  string NAME = ?;
}
def anonymous_4049 {	// AsmOperandClass nImmVMOVIAsmOperandReplicate
  string Name = "NEONi32vmovi16Replicate";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isNEONmovReplicate<16, 32>";
  string RenderMethod = "addNEONvmovi16ReplicateOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_405 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_4050anonymous_4043 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMOVv4i16 DPR:$Vd, anonymous_4051:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4050anonymous_4044 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMOVv8i16 QPR:$Vd, anonymous_4051:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4050anonymous_4045 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMVNv4i16 DPR:$Vd, anonymous_4051:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4050anonymous_4046 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMVNv8i16 QPR:$Vd, anonymous_4051:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4051 {	// DAGOperand Operand nImmVMOVIReplicate
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_4052;
  string NAME = ?;
}
def anonymous_4052 {	// AsmOperandClass nImmVMOVIAsmOperandReplicate
  string Name = "NEONi64vmovi16Replicate";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isNEONmovReplicate<16, 64>";
  string RenderMethod = "addNEONvmovi16ReplicateOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_4053anonymous_4043 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMOVv2i32 DPR:$Vd, anonymous_4054:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4053anonymous_4044 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMOVv4i32 QPR:$Vd, anonymous_4054:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4053anonymous_4045 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMVNv2i32 DPR:$Vd, anonymous_4054:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4053anonymous_4046 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i64 $Vd, $Vm";
  dag ResultInst = (VMVNv4i32 QPR:$Vd, anonymous_4054:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4054 {	// DAGOperand Operand nImmVMOVIReplicate
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_4055;
  string NAME = ?;
}
def anonymous_4055 {	// AsmOperandClass nImmVMOVIAsmOperandReplicate
  string Name = "NEONi64vmovi32Replicate";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isNEONmovReplicate<32, 64>";
  string RenderMethod = "addNEONvmovi32ReplicateOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def anonymous_4056 {	// Pattern Pat
  dag PatternToMatch = (NEONvgetlanes (v16i8 QPR:$src), imm:$lane);
  list<dag> ResultInstrs = [(VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src, (DSubReg_i8_reg imm:$lane))), (SubReg_i8_lane imm:$lane))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4057 {	// Pattern Pat
  dag PatternToMatch = (NEONvgetlanes (v8i16 QPR:$src), imm:$lane);
  list<dag> ResultInstrs = [(VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4058 {	// Pattern Pat
  dag PatternToMatch = (NEONvgetlaneu (v16i8 QPR:$src), imm:$lane);
  list<dag> ResultInstrs = [(VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src, (DSubReg_i8_reg imm:$lane))), (SubReg_i8_lane imm:$lane))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4059 {	// Pattern Pat
  dag PatternToMatch = (NEONvgetlaneu (v8i16 QPR:$src), imm:$lane);
  list<dag> ResultInstrs = [(VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_406 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_4060 {	// Pattern Pat Requires
  dag PatternToMatch = (extractelt (v4i32 QPR:$src), imm:$lane);
  list<dag> ResultInstrs = [(VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane))];
  list<Predicate> Predicates = [HasNEON, HasFastVGETLNi32];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4061 {	// Pattern Pat Requires
  dag PatternToMatch = (extractelt (v2i32 DPR:$src), imm:$lane);
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)];
  list<Predicate> Predicates = [HasNEON, HasSlowVGETLNi32];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4062 {	// Pattern Pat Requires
  dag PatternToMatch = (extractelt (v4i32 QPR:$src), imm:$lane);
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)];
  list<Predicate> Predicates = [HasNEON, HasSlowVGETLNi32];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4063 {	// Pattern Pat
  dag PatternToMatch = (extractelt (v2f32 DPR:$src1), imm:$src2);
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1), DPR_VFP2)), (SSubReg_f32_reg imm:$src2))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4064 {	// Pattern Pat
  dag PatternToMatch = (extractelt (v4f32 QPR:$src1), imm:$src2);
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1), QPR_VFP2)), (SSubReg_f32_reg imm:$src2))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4065 {	// Pattern Pat
  dag PatternToMatch = (extractelt (v2f64 QPR:$src1), imm:$src2);
  list<dag> ResultInstrs = [(EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4066 {	// Pattern Pat
  dag PatternToMatch = (vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane);
  list<dag> ResultInstrs = [(v16i8 (INSERT_SUBREG QPR:$src1, (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1, (DSubReg_i8_reg imm:$lane))), GPR:$src2, (SubReg_i8_lane imm:$lane))), (DSubReg_i8_reg imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4067 {	// Pattern Pat
  dag PatternToMatch = (vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane);
  list<dag> ResultInstrs = [(v8i16 (INSERT_SUBREG QPR:$src1, (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1, (DSubReg_i16_reg imm:$lane))), GPR:$src2, (SubReg_i16_lane imm:$lane))), (DSubReg_i16_reg imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4068 {	// Pattern Pat
  dag PatternToMatch = (insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane);
  list<dag> ResultInstrs = [(v4i32 (INSERT_SUBREG QPR:$src1, (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1, (DSubReg_i32_reg imm:$lane))), GPR:$src2, (SubReg_i32_lane imm:$lane))), (DSubReg_i32_reg imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4069 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)), SPR:$src2, (SSubReg_f32_reg imm:$src3))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_407 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_4070 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)), SPR:$src2, (SSubReg_f32_reg imm:$src3))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4071 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3));
  list<dag> ResultInstrs = [(INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4072 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (scalar_to_vector SPR:$src));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4073 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (scalar_to_vector (f64 DPR:$src)));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4074 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (scalar_to_vector SPR:$src));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4075 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (scalar_to_vector GPR:$src));
  list<dag> ResultInstrs = [(VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4076 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (scalar_to_vector GPR:$src));
  list<dag> ResultInstrs = [(VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4077 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (scalar_to_vector GPR:$src));
  list<dag> ResultInstrs = [(VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4078 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (scalar_to_vector GPR:$src));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)), dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4079 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (scalar_to_vector GPR:$src));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)), dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_408 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_4080 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (scalar_to_vector GPR:$src));
  list<dag> ResultInstrs = [(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)), dsub_0)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4081 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f32 (NEONvdup (f32 (bitconvert GPR:$R))));
  list<dag> ResultInstrs = [(VDUP32d GPR:$R)];
  list<Predicate> Predicates = [HasNEON, HasFastVDUP32];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4082 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (NEONvdup (f32 (bitconvert GPR:$R))));
  list<dag> ResultInstrs = [(VDUP32q GPR:$R)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4083 {	// Pattern Pat Requires
  dag PatternToMatch = (v2i32 (NEONvdup (i32 GPR:$R)));
  list<dag> ResultInstrs = [(VMOVDRR GPR:$R, GPR:$R)];
  list<Predicate> Predicates = [HasNEON, HasSlowVDUP32];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4084 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f32 (NEONvdup (f32 (bitconvert GPR:$R))));
  list<dag> ResultInstrs = [(VMOVDRR GPR:$R, GPR:$R)];
  list<Predicate> Predicates = [HasNEON, HasSlowVDUP32];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4085 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane));
  list<dag> ResultInstrs = [(VDUPLN32d DPR:$Vm, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4086 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane));
  list<dag> ResultInstrs = [(VDUPLN32q DPR:$Vm, imm:$lane)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4087 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane));
  list<dag> ResultInstrs = [(v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src, (DSubReg_i8_reg imm:$lane))), (SubReg_i8_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4088 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane));
  list<dag> ResultInstrs = [(v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4089 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane));
  list<dag> ResultInstrs = [(v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_409 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_4090 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane));
  list<dag> ResultInstrs = [(v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4091 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (NEONvdup (f32 SPR:$src)));
  list<dag> ResultInstrs = [(v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0), (i32 0)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4092 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (NEONvdup (f32 SPR:$src)));
  list<dag> ResultInstrs = [(v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0), (i32 0)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4093 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (anyext (v8i8 DPR:$Vm)));
  list<dag> ResultInstrs = [(VMOVLuv8i16 DPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4094 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (anyext (v4i16 DPR:$Vm)));
  list<dag> ResultInstrs = [(VMOVLuv4i32 DPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4095 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (anyext (v2i32 DPR:$Vm)));
  list<dag> ResultInstrs = [(VMOVLuv2i64 DPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4096 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.s32.f32 $Dd, $Dm, #0";
  dag ResultInst = (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4097 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.u32.f32 $Dd, $Dm, #0";
  dag ResultInst = (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4098 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.f32.s32 $Dd, $Dm, #0";
  dag ResultInst = (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4099 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.f32.u32 $Dd, $Dm, #0";
  dag ResultInst = (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_41 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "dtdh";
  string NAME = ?;
}
def anonymous_410 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_4100 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.s32.f32 $Qd, $Qm, #0";
  dag ResultInst = (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4101 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.u32.f32 $Qd, $Qm, #0";
  dag ResultInst = (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4102 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.f32.s32 $Qd, $Qm, #0";
  dag ResultInst = (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4103 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.f32.u32 $Qd, $Qm, #0";
  dag ResultInst = (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4104 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.s16.f16 $Dd, $Dm, #0";
  dag ResultInst = (VCVTh2sd DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4105 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.u16.f16 $Dd, $Dm, #0";
  dag ResultInst = (VCVTh2ud DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4106 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.f16.s16 $Dd, $Dm, #0";
  dag ResultInst = (VCVTs2hd DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4107 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.f16.u16 $Dd, $Dm, #0";
  dag ResultInst = (VCVTu2hd DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4108 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.s16.f16 $Qd, $Qm, #0";
  dag ResultInst = (VCVTh2sq QPR:$Qd, QPR:$Qm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4109 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.u16.f16 $Qd, $Qm, #0";
  dag ResultInst = (VCVTh2uq QPR:$Qd, QPR:$Qm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_411 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "SAMPLE_C_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_384, anonymous_219, anonymous_302, anonymous_385, anonymous_31, anonymous_269, anonymous_352, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_386, anonymous_221, anonymous_304, anonymous_387, anonymous_148, anonymous_249, anonymous_332, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_388, anonymous_223, anonymous_306, anonymous_389, anonymous_149, anonymous_250, anonymous_333, anonymous_165];
  string NAME = ?;
}
def anonymous_4110 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.f16.s16 $Qd, $Qm, #0";
  dag ResultInst = (VCVTs2hq QPR:$Qd, QPR:$Qm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4111 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcvt${p}.f16.u16 $Qd, $Qm, #0";
  dag ResultInst = (VCVTu2hq QPR:$Qd, QPR:$Qm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4112 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (NEONvrev64 (v2f32 DPR:$Vm)));
  list<dag> ResultInstrs = [(VREV64d32 DPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4113 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (NEONvrev64 (v4f32 QPR:$Vm)));
  list<dag> ResultInstrs = [(VREV64q32 QPR:$Vm)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4114 {	// Pattern Pat AlignedVEXTq
  dag PatternToMatch = (v8i8 (vector_extract_subvec (v16i8 QPR:$src), (i32 imm:$start)));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v16i8 QPR:$src), (DSubReg_i8_reg imm:$start))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4115 {	// Pattern Pat AlignedVEXTq
  dag PatternToMatch = (v4i16 (vector_extract_subvec (v8i16 QPR:$src), (i32 imm:$start)));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v8i16 QPR:$src), (DSubReg_i16_reg imm:$start))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4116 {	// Pattern Pat AlignedVEXTq
  dag PatternToMatch = (v2i32 (vector_extract_subvec (v4i32 QPR:$src), (i32 imm:$start)));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v4i32 QPR:$src), (DSubReg_i32_reg imm:$start))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4117 {	// Pattern Pat AlignedVEXTq
  dag PatternToMatch = (v1i64 (vector_extract_subvec (v2i64 QPR:$src), (i32 imm:$start)));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2i64 QPR:$src), (DSubReg_f64_reg imm:$start))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4118 {	// Pattern Pat AlignedVEXTq
  dag PatternToMatch = (v2f32 (vector_extract_subvec (v4f32 QPR:$src), (i32 imm:$start)));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v4f32 QPR:$src), (DSubReg_i32_reg imm:$start))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4119 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (NEONvext (v2f32 DPR:$Vn), (v2f32 DPR:$Vm), (i32 imm:$index)));
  list<dag> ResultInstrs = [(VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_412 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_4120 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (NEONvext (v4f32 QPR:$Vn), (v4f32 QPR:$Vm), (i32 imm:$index)));
  list<dag> ResultInstrs = [(VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4121 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vuzp${p}.32 $Dd, $Dm";
  dag ResultInst = (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4122 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vzip${p}.32 $Dd, $Dm";
  dag ResultInst = (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4123 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (NEONvtbl2 v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vm));
  list<dag> ResultInstrs = [(v8i8 (VTBL2 (REG_SEQUENCE DPair, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1), v8i8:$Vm))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4124 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (int_arm_neon_vtbx2 v8i8:$orig, v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vm));
  list<dag> ResultInstrs = [(v8i8 (VTBX2 v8i8:$orig, (REG_SEQUENCE DPair, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1), v8i8:$Vm))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4125 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (int_arm_neon_vtbl3 v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vn2, v8i8:$Vm));
  list<dag> ResultInstrs = [(v8i8 (VTBL3Pseudo (REG_SEQUENCE QQPR, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1, v8i8:$Vn2, dsub_2, (v8i8 (IMPLICIT_DEF)), dsub_3), v8i8:$Vm))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4126 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (int_arm_neon_vtbx3 v8i8:$orig, v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vn2, v8i8:$Vm));
  list<dag> ResultInstrs = [(v8i8 (VTBX3Pseudo v8i8:$orig, (REG_SEQUENCE QQPR, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1, v8i8:$Vn2, dsub_2, (v8i8 (IMPLICIT_DEF)), dsub_3), v8i8:$Vm))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4127 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (int_arm_neon_vtbl4 v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vn2, v8i8:$Vn3, v8i8:$Vm));
  list<dag> ResultInstrs = [(v8i8 (VTBL4Pseudo (REG_SEQUENCE QQPR, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1, v8i8:$Vn2, dsub_2, v8i8:$Vn3, dsub_3), v8i8:$Vm))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4128 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (int_arm_neon_vtbx4 v8i8:$orig, v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vn2, v8i8:$Vn3, v8i8:$Vm));
  list<dag> ResultInstrs = [(v8i8 (VTBX4Pseudo v8i8:$orig, (REG_SEQUENCE QQPR, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1, v8i8:$Vn2, dsub_2, v8i8:$Vn3, dsub_3), v8i8:$Vm))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_413 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_87];
  string NAME = ?;
}
def anonymous_4133 {	// Pattern Pat
  dag PatternToMatch = (i32 (int_arm_neon_sha1h i32:$Rn));
  list<dag> ResultInstrs = [(COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (SHA1H (SUBREG_TO_REG (i64 0), (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)), ssub_0)), ssub_0)), GPR)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4134 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk));
  list<dag> ResultInstrs = [(SHA1C v4i32:$hash_abcd, (SUBREG_TO_REG (i64 0), (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4135 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk));
  list<dag> ResultInstrs = [(SHA1M v4i32:$hash_abcd, (SUBREG_TO_REG (i64 0), (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4136 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk));
  list<dag> ResultInstrs = [(SHA1P v4i32:$hash_abcd, (SUBREG_TO_REG (i64 0), (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4137 {	// Pattern Pat NEONFPPat N3VSPat
  dag PatternToMatch = (f32 (fadd SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VADDfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4138 {	// Pattern Pat NEONFPPat N3VSPat
  dag PatternToMatch = (f32 (fsub SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VSUBfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4139 {	// Pattern Pat NEONFPPat N3VSPat
  dag PatternToMatch = (f32 (fmul SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VMULfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_414 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_87];
  string NAME = ?;
}
def anonymous_4140 {	// Pattern Pat NEONFPPat N3VSMulOpPat Requires
  dag PatternToMatch = (f32 (fadd SPR:$acc, (f32 (fmul SPR:$a, SPR:$b))));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VMLAfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$acc, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4141 {	// Pattern Pat NEONFPPat N3VSMulOpPat Requires
  dag PatternToMatch = (f32 (fsub SPR:$acc, (f32 (fmul SPR:$a, SPR:$b))));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VMLSfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$acc, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4142 {	// Pattern Pat NEONFPPat N3VSMulOpPat Requires
  dag PatternToMatch = (f32 (fadd SPR:$acc, (f32 (fmul SPR:$a, SPR:$b))));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VFMAfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$acc, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasVFP4, UseNEONForFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4143 {	// Pattern Pat NEONFPPat N3VSMulOpPat Requires
  dag PatternToMatch = (f32 (fsub SPR:$acc, (f32 (fmul SPR:$a, SPR:$b))));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VFMSfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$acc, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasVFP4, UseNEONForFP, UseFusedMAC];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4144 {	// Pattern Pat NEONFPPat N2VSPat
  dag PatternToMatch = (f32 (fabs SPR:$a));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VABSfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4145 {	// Pattern Pat NEONFPPat N2VSPat
  dag PatternToMatch = (f32 (fneg SPR:$a));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VNEGfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4146 {	// Pattern Pat NEONFPPat N3VSPatFP16 Requires
  dag PatternToMatch = (f16 (fmaxnan HPR:$a, HPR:$b));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v4f16 (COPY_TO_REGCLASS (VMAXhd (INSERT_SUBREG (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), HPR:$a, ssub_0), (INSERT_SUBREG (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), HPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4147 {	// Pattern Pat NEONFPPat N3VSPatFP16 Requires
  dag PatternToMatch = (f16 (fminnan HPR:$a, HPR:$b));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v4f16 (COPY_TO_REGCLASS (VMINhd (INSERT_SUBREG (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), HPR:$a, ssub_0), (INSERT_SUBREG (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), HPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasFullFP16];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4148 {	// Pattern Pat NEONFPPat N3VSPat Requires
  dag PatternToMatch = (f32 (fmaxnan SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VMAXfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4149 {	// Pattern Pat NEONFPPat N3VSPat Requires
  dag PatternToMatch = (f32 (fminnan SPR:$a, SPR:$b));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (VMINfd (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)];
  list<Predicate> Predicates = [HasNEON];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_415 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "face";
  string NAME = ?;
}
def anonymous_4150 {	// Pattern Pat NEONFPPat NVCVTFIPat
  dag PatternToMatch = (i32 (fp_to_sint SPR:$a));
  list<dag> ResultInstrs = [(i32 (EXTRACT_SUBREG (v2f32 (VCVTf2sd (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, ssub_0))), ssub_0))];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4151 {	// Pattern Pat NEONFPPat NVCVTFIPat
  dag PatternToMatch = (i32 (fp_to_uint SPR:$a));
  list<dag> ResultInstrs = [(i32 (EXTRACT_SUBREG (v2f32 (VCVTf2ud (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, ssub_0))), ssub_0))];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4152 {	// Pattern Pat NEONFPPat NVCVTIFPat
  dag PatternToMatch = (f32 (sint_to_fp GPR:$a));
  list<dag> ResultInstrs = [(f32 (EXTRACT_SUBREG (v2f32 (VCVTs2fd (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (i32 (COPY_TO_REGCLASS GPR:$a, SPR)), ssub_0))), ssub_0))];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4153 {	// Pattern Pat NEONFPPat NVCVTIFPat
  dag PatternToMatch = (f32 (uint_to_fp GPR:$a));
  list<dag> ResultInstrs = [(f32 (EXTRACT_SUBREG (v2f32 (VCVTu2fd (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (i32 (COPY_TO_REGCLASS GPR:$a, SPR)), ssub_0))), ssub_0))];
  list<Predicate> Predicates = [HasNEON, UseNEONForFP];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4154 {	// Pattern Pat VFPPat
  dag PatternToMatch = (f64 (sint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane)));
  list<dag> ResultInstrs = [(VSITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))];
  list<Predicate> Predicates = [HasVFP2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4155 {	// Pattern Pat VFPPat
  dag PatternToMatch = (f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane)));
  list<dag> ResultInstrs = [(VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))];
  list<Predicate> Predicates = [HasVFP2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4156 {	// Pattern Pat VFPPat
  dag PatternToMatch = (f64 (uint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane)));
  list<dag> ResultInstrs = [(VUITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))];
  list<Predicate> Predicates = [HasVFP2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4157 {	// Pattern Pat VFPPat
  dag PatternToMatch = (f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane)));
  list<dag> ResultInstrs = [(VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))];
  list<Predicate> Predicates = [HasVFP2];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4158 {	// Pattern Pat Requires
  dag PatternToMatch = (f32 (bitconvert GPR:$a));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)];
  list<Predicate> Predicates = [HasNEON, DontUseVMOVSR];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4159 {	// Pattern Pat Requires
  dag PatternToMatch = (arm_vmovsr GPR:$a);
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)];
  list<Predicate> Predicates = [HasNEON, DontUseVMOVSR];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_416 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "face";
  string NAME = ?;
}
def anonymous_4160 {	// Pattern Pat
  dag PatternToMatch = (v1i64 (bitconvert (v2i32 DPR:$src)));
  list<dag> ResultInstrs = [(v1i64 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4161 {	// Pattern Pat
  dag PatternToMatch = (v1i64 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(v1i64 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4162 {	// Pattern Pat
  dag PatternToMatch = (v1i64 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(v1i64 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4163 {	// Pattern Pat
  dag PatternToMatch = (v1i64 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(v1i64 DPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4164 {	// Pattern Pat
  dag PatternToMatch = (v1i64 (bitconvert (v2f32 DPR:$src)));
  list<dag> ResultInstrs = [(v1i64 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4165 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (bitconvert (v1i64 DPR:$src)));
  list<dag> ResultInstrs = [(v2i32 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4166 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(v2i32 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4167 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(v2i32 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4168 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(v2i32 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4169 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (bitconvert (v2f32 DPR:$src)));
  list<dag> ResultInstrs = [(v2i32 DPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_417 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_4170 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (v1i64 DPR:$src)));
  list<dag> ResultInstrs = [(v4i16 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4171 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (v2i32 DPR:$src)));
  list<dag> ResultInstrs = [(v4i16 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4172 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(v4i16 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4173 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(v4i16 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4174 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (v2f32 DPR:$src)));
  list<dag> ResultInstrs = [(v4i16 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4175 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (v1i64 DPR:$src)));
  list<dag> ResultInstrs = [(v8i8 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4176 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (v2i32 DPR:$src)));
  list<dag> ResultInstrs = [(v8i8 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4177 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(v8i8 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4178 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(v8i8 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4179 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (v2f32 DPR:$src)));
  list<dag> ResultInstrs = [(v8i8 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_418 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_87];
  string NAME = ?;
}
def anonymous_4180 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v1i64 DPR:$src)));
  list<dag> ResultInstrs = [(f64 DPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4181 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v2i32 DPR:$src)));
  list<dag> ResultInstrs = [(f64 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4182 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(f64 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4183 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v4f16 DPR:$src)));
  list<dag> ResultInstrs = [(f64 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4184 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(f64 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4185 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v2f32 DPR:$src)));
  list<dag> ResultInstrs = [(f64 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4186 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(v2f32 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4187 {	// Pattern Pat
  dag PatternToMatch = (v4f16 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(v4f16 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4188 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (bitconvert (v1i64 DPR:$src)));
  list<dag> ResultInstrs = [(v2f32 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4189 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (bitconvert (v2i32 DPR:$src)));
  list<dag> ResultInstrs = [(v2f32 DPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_419 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_4190 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(v2f32 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4191 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(v2f32 DPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4192 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (bitconvert (v4i32 QPR:$src)));
  list<dag> ResultInstrs = [(v2i64 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4193 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(v2i64 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4194 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(v2i64 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4195 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(v2i64 QPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4196 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (bitconvert (v4f32 QPR:$src)));
  list<dag> ResultInstrs = [(v2i64 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4197 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (bitconvert (v2i64 QPR:$src)));
  list<dag> ResultInstrs = [(v4i32 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4198 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(v4i32 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4199 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(v4i32 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_42 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "dtdv";
  string NAME = ?;
}
def anonymous_420 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  string NAME = ?;
}
def anonymous_4200 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(v4i32 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4201 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (bitconvert (v4f32 QPR:$src)));
  list<dag> ResultInstrs = [(v4i32 QPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4202 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v2i64 QPR:$src)));
  list<dag> ResultInstrs = [(v8i16 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4203 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v4i32 QPR:$src)));
  list<dag> ResultInstrs = [(v8i16 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4204 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(v8i16 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4205 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(v8i16 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4206 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v4f32 QPR:$src)));
  list<dag> ResultInstrs = [(v8i16 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4207 {	// Pattern Pat
  dag PatternToMatch = (v8f16 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(v8f16 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4208 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v2i64 QPR:$src)));
  list<dag> ResultInstrs = [(v16i8 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4209 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v4i32 QPR:$src)));
  list<dag> ResultInstrs = [(v16i8 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_421 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_4210 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(v16i8 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4211 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(v16i8 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4212 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v4f32 QPR:$src)));
  list<dag> ResultInstrs = [(v16i8 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4213 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v2i64 QPR:$src)));
  list<dag> ResultInstrs = [(v4f32 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4214 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v4i32 QPR:$src)));
  list<dag> ResultInstrs = [(v4f32 QPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4215 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(v4f32 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4216 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(v4f32 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4217 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(v4f32 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4218 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v2i64 QPR:$src)));
  list<dag> ResultInstrs = [(v2f64 QPR:$src)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4219 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v4i32 QPR:$src)));
  list<dag> ResultInstrs = [(v2f64 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_422 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  string NAME = ?;
}
def anonymous_4220 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(v2f64 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4221 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v8f16 QPR:$src)));
  list<dag> ResultInstrs = [(v2f64 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4222 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(v2f64 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4223 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v4f32 QPR:$src)));
  list<dag> ResultInstrs = [(v2f64 QPR:$src)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4224 {	// Pattern Pat
  dag PatternToMatch = (v1i64 (bitconvert (v2i32 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d32 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4225 {	// Pattern Pat
  dag PatternToMatch = (v1i64 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d16 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4226 {	// Pattern Pat
  dag PatternToMatch = (v1i64 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4227 {	// Pattern Pat
  dag PatternToMatch = (v1i64 (bitconvert (v2f32 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d32 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4228 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (bitconvert (v1i64 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d32 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4229 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(VREV32d16 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_423 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_4230 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(VREV32d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4231 {	// Pattern Pat
  dag PatternToMatch = (v2i32 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d32 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4232 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (v1i64 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d16 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4233 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (v2i32 DPR:$src)));
  list<dag> ResultInstrs = [(VREV32d16 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4234 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(VREV16d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4235 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d16 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4236 {	// Pattern Pat
  dag PatternToMatch = (v4i16 (bitconvert (v2f32 DPR:$src)));
  list<dag> ResultInstrs = [(VREV32d16 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4237 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (v1i64 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4238 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (v2i32 DPR:$src)));
  list<dag> ResultInstrs = [(VREV32d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4239 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(VREV16d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_424 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  string NAME = ?;
}
def anonymous_4240 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4241 {	// Pattern Pat
  dag PatternToMatch = (v8i8 (bitconvert (v2f32 DPR:$src)));
  list<dag> ResultInstrs = [(VREV32d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4242 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v2i32 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d32 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4243 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v4f16 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d16 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4244 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d16 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4245 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4246 {	// Pattern Pat
  dag PatternToMatch = (f64 (bitconvert (v2f32 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d32 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4247 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (bitconvert (f64 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d32 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4248 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (bitconvert (v1i64 DPR:$src)));
  list<dag> ResultInstrs = [(VREV64d32 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4249 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (bitconvert (v4i16 DPR:$src)));
  list<dag> ResultInstrs = [(VREV32d16 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_425 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  string NAME = ?;
}
def anonymous_4250 {	// Pattern Pat
  dag PatternToMatch = (v2f32 (bitconvert (v8i8 DPR:$src)));
  list<dag> ResultInstrs = [(VREV32d8 DPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4251 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (bitconvert (v4i32 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q32 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4252 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4253 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4254 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (bitconvert (v4f32 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q32 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4255 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (bitconvert (v2i64 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q32 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4256 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(VREV32q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4257 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(VREV32q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4258 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q32 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4259 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v2i64 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_426 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_4260 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v4i32 QPR:$src)));
  list<dag> ResultInstrs = [(VREV32q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4261 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(VREV16q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4262 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4263 {	// Pattern Pat
  dag PatternToMatch = (v8f16 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4264 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (bitconvert (v4f32 QPR:$src)));
  list<dag> ResultInstrs = [(VREV32q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4265 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v2i64 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4266 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v4i32 QPR:$src)));
  list<dag> ResultInstrs = [(VREV32q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4267 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(VREV16q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4268 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4269 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (bitconvert (v4f32 QPR:$src)));
  list<dag> ResultInstrs = [(VREV32q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_427 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  string NAME = ?;
}
def anonymous_4270 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v2i64 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q32 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4271 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(VREV32q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4272 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v8f16 QPR:$src)));
  list<dag> ResultInstrs = [(VREV32q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4273 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(VREV32q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4274 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (bitconvert (v2f64 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q32 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4275 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v4i32 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q32 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4276 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v8i16 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4277 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v8f16 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q16 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4278 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v16i8 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q8 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4279 {	// Pattern Pat
  dag PatternToMatch = (v2f64 (bitconvert (v4f32 QPR:$src)));
  list<dag> ResultInstrs = [(VREV64q32 QPR:$src)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_428 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_4280 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f64 (byte_alignedload addrmode6:$addr));
  list<dag> ResultInstrs = [(VREV64q8 (VLD1q8 addrmode6:$addr))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4281 {	// Pattern Pat Requires
  dag PatternToMatch = (byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1q8 addrmode6:$addr, (VREV64q8 QPR:$value))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4282 {	// Pattern Pat Requires
  dag PatternToMatch = (v2f64 (hword_alignedload addrmode6:$addr));
  list<dag> ResultInstrs = [(VREV64q16 (VLD1q16 addrmode6:$addr))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4283 {	// Pattern Pat Requires
  dag PatternToMatch = (hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr);
  list<dag> ResultInstrs = [(VST1q16 addrmode6:$addr, (VREV64q16 QPR:$value))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4284 {	// Pattern Pat
  dag PatternToMatch = (f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane))));
  list<dag> ResultInstrs = [(f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4285_Any {	// Pattern Pat
  dag PatternToMatch = (v8i16 (extloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv8i16 (VLD1d8 addrmode6:$addr))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_4285_S {	// Pattern Pat
  dag PatternToMatch = (v8i16 (sextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLsv8i16 (VLD1d8 addrmode6:$addr))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_4285_Z {	// Pattern Pat
  dag PatternToMatch = (v8i16 (zextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv8i16 (VLD1d8 addrmode6:$addr))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_4286_Any {	// Pattern Pat
  dag PatternToMatch = (v4i32 (extloadvi16 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv4i32 (VLD1d16 addrmode6:$addr))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_4286_S {	// Pattern Pat
  dag PatternToMatch = (v4i32 (sextloadvi16 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLsv4i32 (VLD1d16 addrmode6:$addr))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_4286_Z {	// Pattern Pat
  dag PatternToMatch = (v4i32 (zextloadvi16 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv4i32 (VLD1d16 addrmode6:$addr))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_4287_Any {	// Pattern Pat
  dag PatternToMatch = (v2i64 (extloadvi32 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (VLD1d32 addrmode6:$addr))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_4287_S {	// Pattern Pat
  dag PatternToMatch = (v2i64 (sextloadvi32 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLsv2i64 (VLD1d32 addrmode6:$addr))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_4287_Z {	// Pattern Pat
  dag PatternToMatch = (v2i64 (zextloadvi32 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (VLD1d32 addrmode6:$addr))];
  list<Predicate> Predicates = [];
  int AddedComplexity = 10;
  string NAME = ?;
}
def anonymous_4288_Any {	// Pattern Pat
  dag PatternToMatch = (v4i16 (extloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4288_S {	// Pattern Pat
  dag PatternToMatch = (v4i16 (sextloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLsv8i16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4288_Z {	// Pattern Pat
  dag PatternToMatch = (v4i16 (zextloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4289_Any {	// Pattern Pat
  dag PatternToMatch = (v2i32 (extloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv4i32 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4289_S {	// Pattern Pat
  dag PatternToMatch = (v2i32 (sextloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLsv4i32 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4289_Z {	// Pattern Pat
  dag PatternToMatch = (v2i32 (zextloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv4i32 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_429 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  string NAME = ?;
}
def anonymous_4290_Any {	// Pattern Pat
  dag PatternToMatch = (v4i32 (extloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0))];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4290_S {	// Pattern Pat
  dag PatternToMatch = (v4i32 (sextloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0))];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4290_Z {	// Pattern Pat
  dag PatternToMatch = (v4i32 (zextloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0))];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4291_Any {	// Pattern Pat
  dag PatternToMatch = (v2i32 (extloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4291_S {	// Pattern Pat
  dag PatternToMatch = (v2i32 (sextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4291_Z {	// Pattern Pat
  dag PatternToMatch = (v2i32 (zextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0)];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4292_Any {	// Pattern Pat
  dag PatternToMatch = (v2i64 (extloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0))];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4292_S {	// Pattern Pat
  dag PatternToMatch = (v2i64 (sextloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0))];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4292_Z {	// Pattern Pat
  dag PatternToMatch = (v2i64 (zextloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0))];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4293_Any {	// Pattern Pat
  dag PatternToMatch = (v4i16 (extloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv8i16 (VREV32d8 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4293_S {	// Pattern Pat
  dag PatternToMatch = (v4i16 (sextloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLsv8i16 (VREV32d8 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4293_Z {	// Pattern Pat
  dag PatternToMatch = (v4i16 (zextloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv8i16 (VREV32d8 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4294_Any {	// Pattern Pat
  dag PatternToMatch = (v2i32 (extloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv4i32 (VREV32d16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4294_S {	// Pattern Pat
  dag PatternToMatch = (v2i32 (sextloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLsv4i32 (VREV32d16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4294_Z {	// Pattern Pat
  dag PatternToMatch = (v2i32 (zextloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv4i32 (VREV32d16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4295_Any {	// Pattern Pat
  dag PatternToMatch = (v4i32 (extloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VREV32d8 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4295_S {	// Pattern Pat
  dag PatternToMatch = (v4i32 (sextloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 (VREV32d8 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4295_Z {	// Pattern Pat
  dag PatternToMatch = (v4i32 (zextloadvi8 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VREV32d8 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4296_Any {	// Pattern Pat
  dag PatternToMatch = (v2i32 (extloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4296_S {	// Pattern Pat
  dag PatternToMatch = (v2i32 (sextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4296_Z {	// Pattern Pat
  dag PatternToMatch = (v2i32 (zextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0)];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4297_Any {	// Pattern Pat
  dag PatternToMatch = (v2i64 (extloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (VREV32d16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4297_S {	// Pattern Pat
  dag PatternToMatch = (v2i64 (sextloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (VREV32d16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4297_Z {	// Pattern Pat
  dag PatternToMatch = (v2i64 (zextloadvi16 addrmode6oneL32:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (VREV32d16 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4298 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (extloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4299 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (zextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_43 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_31, anonymous_38, anonymous_44];
  string NAME = ?;
}
def anonymous_430 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_4300 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (sextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))];
  list<Predicate> Predicates = [IsLE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4301 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (extloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4302 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (zextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4303 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (sextloadvi8 addrmode6:$addr));
  list<dag> ResultInstrs = [(VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))];
  list<Predicate> Predicates = [IsBE];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4304 {	// Pattern Pat
  dag PatternToMatch = (v2i64 (concat_vectors DPR:$Dn, DPR:$Dm));
  list<dag> ResultInstrs = [(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4305 {	// Pattern Pat
  dag PatternToMatch = (v4i32 (concat_vectors DPR:$Dn, DPR:$Dm));
  list<dag> ResultInstrs = [(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4306 {	// Pattern Pat
  dag PatternToMatch = (v8i16 (concat_vectors DPR:$Dn, DPR:$Dm));
  list<dag> ResultInstrs = [(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4307 {	// Pattern Pat
  dag PatternToMatch = (v16i8 (concat_vectors DPR:$Dn, DPR:$Dm));
  list<dag> ResultInstrs = [(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4308 {	// Pattern Pat
  dag PatternToMatch = (v4f32 (concat_vectors DPR:$Dn, DPR:$Dm));
  list<dag> ResultInstrs = [(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)];
  list<Predicate> Predicates = [];
  int AddedComplexity = 0;
  string NAME = ?;
}
def anonymous_4309 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "fmdhr${p} $Dd, $Rn";
  dag ResultInst = (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_431 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  string NAME = ?;
}
def anonymous_4310 {	// InstAlias Requires VFP2InstAlias
  string AsmString = "fmdlr${p} $Dd, $Rn";
  dag ResultInst = (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasVFP2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4311anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4311anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4311anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4311anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4312anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4312anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4312anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4312anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4313anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbic${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4313anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbic${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4313anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbic${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4313anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbic${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4314anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbic${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4314anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbic${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4314anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbic${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4314anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbic${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4315anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4315anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4315anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4315anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4316anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4316anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4316anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4316anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4317anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4317anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4317anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4317anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4318anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4318anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4318anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4318anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4319anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.8	$Vdn, $Vm";
  dag ResultInst = (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4319anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.16	$Vdn, $Vm";
  dag ResultInst = (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4319anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.32	$Vdn, $Vm";
  dag ResultInst = (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4319anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.64	$Vdn, $Vm";
  dag ResultInst = (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_432 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_4320anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.8	$Vdn, $Vm";
  dag ResultInst = (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4320anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.16	$Vdn, $Vm";
  dag ResultInst = (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4320anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.32	$Vdn, $Vm";
  dag ResultInst = (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4320anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vand${p}.64	$Vdn, $Vm";
  dag ResultInst = (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4321anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.8	$Vdn, $Vm";
  dag ResultInst = (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4321anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.16	$Vdn, $Vm";
  dag ResultInst = (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4321anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.32	$Vdn, $Vm";
  dag ResultInst = (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4321anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.64	$Vdn, $Vm";
  dag ResultInst = (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4322anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.8	$Vdn, $Vm";
  dag ResultInst = (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4322anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.16	$Vdn, $Vm";
  dag ResultInst = (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4322anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.32	$Vdn, $Vm";
  dag ResultInst = (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4322anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "veor${p}.64	$Vdn, $Vm";
  dag ResultInst = (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4323anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.8	$Vdn, $Vm";
  dag ResultInst = (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4323anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.16	$Vdn, $Vm";
  dag ResultInst = (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4323anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.32	$Vdn, $Vm";
  dag ResultInst = (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4323anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.64	$Vdn, $Vm";
  dag ResultInst = (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4324anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.8	$Vdn, $Vm";
  dag ResultInst = (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4324anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.16	$Vdn, $Vm";
  dag ResultInst = (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4324anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.32	$Vdn, $Vm";
  dag ResultInst = (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4324anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vorr${p}.64	$Vdn, $Vm";
  dag ResultInst = (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4325 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vand${p}.i16 $Vd, $imm";
  dag ResultInst = (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4326 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vand${p}.i32 $Vd, $imm";
  dag ResultInst = (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4327 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vand${p}.i16 $Vd, $imm";
  dag ResultInst = (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4328 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vand${p}.i32 $Vd, $imm";
  dag ResultInst = (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4329anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmov${p}.8	$Vd, $Vm";
  dag ResultInst = (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4329anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmov${p}.16	$Vd, $Vm";
  dag ResultInst = (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4329anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmov${p}.32	$Vd, $Vm";
  dag ResultInst = (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4329anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmov${p}.64	$Vd, $Vm";
  dag ResultInst = (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_433 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_269, anonymous_435];
  string NAME = ?;
}
def anonymous_4330anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmov${p}.8	$Vd, $Vm";
  dag ResultInst = (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4330anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmov${p}.16	$Vd, $Vm";
  dag ResultInst = (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4330anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmov${p}.32	$Vd, $Vm";
  dag ResultInst = (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4330anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmov${p}.64	$Vd, $Vm";
  dag ResultInst = (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4331anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmvn${p}.8	$Vd, $Vm";
  dag ResultInst = (VMVNd DPR:$Vd, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4331anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmvn${p}.16	$Vd, $Vm";
  dag ResultInst = (VMVNd DPR:$Vd, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4331anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmvn${p}.32	$Vd, $Vm";
  dag ResultInst = (VMVNd DPR:$Vd, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4331anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmvn${p}.64	$Vd, $Vm";
  dag ResultInst = (VMVNd DPR:$Vd, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4332anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmvn${p}.8	$Vd, $Vm";
  dag ResultInst = (VMVNq QPR:$Vd, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4332anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmvn${p}.16	$Vd, $Vm";
  dag ResultInst = (VMVNq QPR:$Vd, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4332anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmvn${p}.32	$Vd, $Vm";
  dag ResultInst = (VMVNq QPR:$Vd, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4332anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vmvn${p}.64	$Vd, $Vm";
  dag ResultInst = (VMVNq QPR:$Vd, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4333 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.s8 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4334 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.s16 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4335 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.s32 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4336 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.u8 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4337 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.u16 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4338 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.u32 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4339 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.f32 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_434 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_269, anonymous_435];
  string NAME = ?;
}
def anonymous_4340 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.f16 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGEhd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4341 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.s8 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4342 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.s16 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4343 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.s32 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4344 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.u8 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4345 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.u16 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4346 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.u32 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4347 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.f32 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4348 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vcle${p}.f16 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGEhq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4349 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.s8 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_435 {	// AMDGPUArg
  LLVMType Type = anonymous_191;
  string Name = "face";
  string NAME = ?;
}
def anonymous_4350 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.s16 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4351 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.s32 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4352 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.u8 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4353 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.u16 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4354 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.u32 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4355 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.f32 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4356 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.f16 $Dd, $Dn, $Dm";
  dag ResultInst = (VCGThd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4357 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.s8 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4358 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.s16 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4359 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.s32 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_436 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_4360 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.u8 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4361 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.u16 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4362 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.u32 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4363 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.f32 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4364 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vclt${p}.f16 $Qd, $Qn, $Qm";
  dag ResultInst = (VCGThq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON, HasFullFP16];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4365anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vswp${p}.8	$Vd, $Vm";
  dag ResultInst = (VSWPd DPR:$Vd, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4365anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vswp${p}.16	$Vd, $Vm";
  dag ResultInst = (VSWPd DPR:$Vd, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4365anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vswp${p}.32	$Vd, $Vm";
  dag ResultInst = (VSWPd DPR:$Vd, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4365anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vswp${p}.64	$Vd, $Vm";
  dag ResultInst = (VSWPd DPR:$Vd, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4366anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vswp${p}.8	$Vd, $Vm";
  dag ResultInst = (VSWPq QPR:$Vd, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4366anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vswp${p}.16	$Vd, $Vm";
  dag ResultInst = (VSWPq QPR:$Vd, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4366anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vswp${p}.32	$Vd, $Vm";
  dag ResultInst = (VSWPq QPR:$Vd, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4366anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vswp${p}.64	$Vd, $Vm";
  dag ResultInst = (VSWPq QPR:$Vd, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4367anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbif${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4367anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbif${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4367anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbif${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4367anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbif${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4368anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbit${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4368anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbit${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4368anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbit${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4368anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbit${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4369anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbsl${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4369anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbsl${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4369anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbsl${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4369anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbsl${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_437 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_435];
  string NAME = ?;
}
def anonymous_4370anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbif${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4370anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbif${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4370anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbif${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4370anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbif${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4371anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbit${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4371anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbit${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4371anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbit${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4371anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbit${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4372anonymous_3106 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbsl${p}.8	$Vd, $Vn, $Vm";
  dag ResultInst = (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4372anonymous_3107 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbsl${p}.16	$Vd, $Vn, $Vm";
  dag ResultInst = (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4372anonymous_3108 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbsl${p}.32	$Vd, $Vn, $Vm";
  dag ResultInst = (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4372anonymous_3109 {	// InstAlias Requires VFPDataTypeInstAlias
  string AsmString = "vbsl${p}.64	$Vd, $Vn, $Vm";
  dag ResultInst = (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4373 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i32 $Vd, $imm";
  dag ResultInst = (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4374 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.i32 $Vd, $imm";
  dag ResultInst = (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4375 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i32 $Vd, $imm";
  dag ResultInst = (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4376 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmvn${p}.i32 $Vd, $imm";
  dag ResultInst = (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4377 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vbicq";
  string ToMnemonic = "vbic";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4378 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vandq";
  string ToMnemonic = "vand";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4379 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "veorq";
  string ToMnemonic = "veor";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_438 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_4380 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vorrq";
  string ToMnemonic = "vorr";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4381 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vmovq";
  string ToMnemonic = "vmov";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4382 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vmvnq";
  string ToMnemonic = "vmvn";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4383 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vmovq.f32";
  string ToMnemonic = "vmov.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4384 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vmovq.f64";
  string ToMnemonic = "vmov.f64";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4385 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vaddq";
  string ToMnemonic = "vadd";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4386 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vsubq";
  string ToMnemonic = "vsub";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4387 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vminq";
  string ToMnemonic = "vmin";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4388 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vmaxq";
  string ToMnemonic = "vmax";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4389 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vmulq";
  string ToMnemonic = "vmul";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_439 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435];
  string NAME = ?;
}
def anonymous_4390 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vabsq";
  string ToMnemonic = "vabs";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4391 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vshlq";
  string ToMnemonic = "vshl";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4392 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vshrq";
  string ToMnemonic = "vshr";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4393 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vcvtq";
  string ToMnemonic = "vcvt";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4394 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vcleq";
  string ToMnemonic = "vcle";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4395 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vceqq";
  string ToMnemonic = "vceq";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4396 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vzipq";
  string ToMnemonic = "vzip";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4397 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vswpq";
  string ToMnemonic = "vswp";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4398 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vrecpeq.f32";
  string ToMnemonic = "vrecpe.f32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_4399 {	// MnemonicAlias Requires NEONMnemonicAlias
  string FromMnemonic = "vrecpeq.u32";
  string ToMnemonic = "vrecpe.u32";
  string AsmVariantName = "";
  list<Predicate> Predicates = [HasNEON];
  string NAME = ?;
}
def anonymous_44 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "r";
  string NAME = ?;
}
def anonymous_440 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_4400 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.f32 $Vd, $imm";
  dag ResultInst = (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4401 {	// InstAlias Requires NEONInstAlias
  string AsmString = "vmov${p}.f32 $Vd, $imm";
  dag ResultInst = (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [HasNEON];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4402 {	// InstAlias Requires
  string AsmString = "dmb";
  dag ResultInst = (DMB 15);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, HasDB];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4403 {	// InstAlias Requires
  string AsmString = "dsb";
  dag ResultInst = (DSB 15);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, HasDB];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4404 {	// InstAlias Requires
  string AsmString = "isb";
  dag ResultInst = (ISB 15);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, HasDB];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4405 {	// InstAlias Requires
  string AsmString = "dfb";
  dag ResultInst = (DSB 12);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, HasDFB];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4406 {	// MnemonicAlias
  string FromMnemonic = "swi";
  string ToMnemonic = "svc";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4407 {	// MnemonicAlias
  string FromMnemonic = "ldmfd";
  string ToMnemonic = "ldm";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4408 {	// MnemonicAlias
  string FromMnemonic = "ldmia";
  string ToMnemonic = "ldm";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4409 {	// MnemonicAlias
  string FromMnemonic = "ldmea";
  string ToMnemonic = "ldmdb";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_441 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435];
  string NAME = ?;
}
def anonymous_4410 {	// MnemonicAlias
  string FromMnemonic = "stmfd";
  string ToMnemonic = "stmdb";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4411 {	// MnemonicAlias
  string FromMnemonic = "stmia";
  string ToMnemonic = "stm";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4412 {	// MnemonicAlias
  string FromMnemonic = "stmea";
  string ToMnemonic = "stm";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4413 {	// InstAlias Requires
  string AsmString = "pkhbt${p} $Rd, $Rn, $Rm";
  dag ResultInst = (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, HasV6];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4414 {	// InstAlias Requires
  string AsmString = "pkhtb${p} $Rd, $Rn, $Rm";
  dag ResultInst = (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, HasV6];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4415 {	// InstAlias Requires ARMInstAlias
  string AsmString = "push${p} $regs";
  dag ResultInst = (STMDB_UPD SP, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4416 {	// InstAlias Requires ARMInstAlias
  string AsmString = "pop${p} $regs";
  dag ResultInst = (LDMIA_UPD SP, pred:$p, reglist:$regs);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4417 {	// InstAlias Requires ARMInstAlias
  string AsmString = "ssat${p} $Rd, $sat_imm, $Rn";
  dag ResultInst = (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4418 {	// InstAlias Requires ARMInstAlias
  string AsmString = "usat${p} $Rd, $sat_imm, $Rn";
  dag ResultInst = (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4419 {	// InstAlias Requires ARMInstAlias
  string AsmString = "sxtab${p} $Rd, $Rn, $Rm";
  dag ResultInst = (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_442 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_4420 {	// InstAlias Requires ARMInstAlias
  string AsmString = "sxtah${p} $Rd, $Rn, $Rm";
  dag ResultInst = (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4421 {	// InstAlias Requires ARMInstAlias
  string AsmString = "sxtab16${p} $Rd, $Rn, $Rm";
  dag ResultInst = (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4422 {	// InstAlias Requires ARMInstAlias
  string AsmString = "sxtb${p} $Rd, $Rm";
  dag ResultInst = (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4423 {	// InstAlias Requires ARMInstAlias
  string AsmString = "sxtb16${p} $Rd, $Rm";
  dag ResultInst = (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4424 {	// InstAlias Requires ARMInstAlias
  string AsmString = "sxth${p} $Rd, $Rm";
  dag ResultInst = (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4425 {	// InstAlias Requires ARMInstAlias
  string AsmString = "uxtab${p} $Rd, $Rn, $Rm";
  dag ResultInst = (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4426 {	// InstAlias Requires ARMInstAlias
  string AsmString = "uxtah${p} $Rd, $Rn, $Rm";
  dag ResultInst = (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4427 {	// InstAlias Requires ARMInstAlias
  string AsmString = "uxtab16${p} $Rd, $Rn, $Rm";
  dag ResultInst = (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4428 {	// InstAlias Requires ARMInstAlias
  string AsmString = "uxtb${p} $Rd, $Rm";
  dag ResultInst = (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4429 {	// InstAlias Requires ARMInstAlias
  string AsmString = "uxtb16${p} $Rd, $Rm";
  dag ResultInst = (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_443 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  string NAME = ?;
}
def anonymous_4430 {	// InstAlias Requires ARMInstAlias
  string AsmString = "uxth${p} $Rd, $Rm";
  dag ResultInst = (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4431 {	// MnemonicAlias
  string FromMnemonic = "rfefa";
  string ToMnemonic = "rfeda";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4432 {	// MnemonicAlias
  string FromMnemonic = "rfeea";
  string ToMnemonic = "rfedb";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4433 {	// MnemonicAlias
  string FromMnemonic = "rfefd";
  string ToMnemonic = "rfeia";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4434 {	// MnemonicAlias
  string FromMnemonic = "rfeed";
  string ToMnemonic = "rfeib";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4435 {	// MnemonicAlias
  string FromMnemonic = "rfe";
  string ToMnemonic = "rfeia";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4436 {	// MnemonicAlias
  string FromMnemonic = "srsfa";
  string ToMnemonic = "srsib";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4437 {	// MnemonicAlias
  string FromMnemonic = "srsea";
  string ToMnemonic = "srsia";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4438 {	// MnemonicAlias
  string FromMnemonic = "srsfd";
  string ToMnemonic = "srsdb";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4439 {	// MnemonicAlias
  string FromMnemonic = "srsed";
  string ToMnemonic = "srsda";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_444 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  string NAME = ?;
}
def anonymous_4440 {	// MnemonicAlias
  string FromMnemonic = "srs";
  string ToMnemonic = "srsia";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4441 {	// MnemonicAlias
  string FromMnemonic = "qsubaddx";
  string ToMnemonic = "qsax";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4442 {	// MnemonicAlias
  string FromMnemonic = "saddsubx";
  string ToMnemonic = "sasx";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4443 {	// MnemonicAlias
  string FromMnemonic = "shaddsubx";
  string ToMnemonic = "shasx";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4444 {	// MnemonicAlias
  string FromMnemonic = "shsubaddx";
  string ToMnemonic = "shsax";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4445 {	// MnemonicAlias
  string FromMnemonic = "ssubaddx";
  string ToMnemonic = "ssax";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4446 {	// MnemonicAlias
  string FromMnemonic = "uaddsubx";
  string ToMnemonic = "uasx";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4447 {	// MnemonicAlias
  string FromMnemonic = "uhaddsubx";
  string ToMnemonic = "uhasx";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4448 {	// MnemonicAlias
  string FromMnemonic = "uhsubaddx";
  string ToMnemonic = "uhsax";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4449 {	// MnemonicAlias
  string FromMnemonic = "uqaddsubx";
  string ToMnemonic = "uqasx";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_445 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_4450 {	// MnemonicAlias
  string FromMnemonic = "uqsubaddx";
  string ToMnemonic = "uqsax";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4451 {	// MnemonicAlias
  string FromMnemonic = "usubaddx";
  string ToMnemonic = "usax";
  string AsmVariantName = "";
  list<Predicate> Predicates = [];
  string NAME = ?;
}
def anonymous_4452 {	// InstAlias Requires ARMInstSubst
  string AsmString = "mov${s}${p} $Rd, $imm";
  dag ResultInst = (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4453 {	// InstAlias Requires ARMInstSubst
  string AsmString = "mvn${s}${p} $Rd, $imm";
  dag ResultInst = (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4454 {	// InstAlias Requires ARMInstSubst
  string AsmString = "bic${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4455 {	// InstAlias Requires ARMInstSubst
  string AsmString = "bic${s}${p} $Rdn, $imm";
  dag ResultInst = (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4456 {	// InstAlias Requires ARMInstSubst
  string AsmString = "and${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4457 {	// InstAlias Requires ARMInstSubst
  string AsmString = "and${s}${p} $Rdn, $imm";
  dag ResultInst = (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4458 {	// InstAlias Requires ARMInstSubst
  string AsmString = "add${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4459 {	// InstAlias Requires ARMInstSubst
  string AsmString = "add${s}${p} $Rd, $imm";
  dag ResultInst = (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_446 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  string NAME = ?;
}
def anonymous_4460 {	// InstAlias Requires ARMInstSubst
  string AsmString = "sub${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4461 {	// InstAlias Requires ARMInstSubst
  string AsmString = "sub${s}${p} $Rd, $imm";
  dag ResultInst = (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4462 {	// InstAlias Requires ARMInstSubst
  string AsmString = "adc${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4463 {	// InstAlias Requires ARMInstSubst
  string AsmString = "adc${s}${p} $Rdn, $imm";
  dag ResultInst = (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4464 {	// InstAlias Requires ARMInstSubst
  string AsmString = "sbc${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4465 {	// InstAlias Requires ARMInstSubst
  string AsmString = "sbc${s}${p} $Rdn, $imm";
  dag ResultInst = (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4466 {	// InstAlias Requires ARMInstSubst
  string AsmString = "cmp${p} $Rd, $imm";
  dag ResultInst = (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4467 {	// InstAlias Requires ARMInstSubst
  string AsmString = "cmn${p} $Rd, $imm";
  dag ResultInst = (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, UseNegativeImmediates];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4468 {	// InstAlias Requires ARMInstAlias
  string AsmString = "neg${s}${p} $Rd, $Rm";
  dag ResultInst = (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4469 {	// InstAlias Requires
  string AsmString = "nop${p}";
  dag ResultInst = (MOVr R0, R0, pred:$p, zero_reg);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsARM, NoV6];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_447 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_4470 {	// InstAlias Requires
  string AsmString = "mul${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, NoV6];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4471 {	// InstAlias Requires
  string AsmString = "mla${s}${p} $Rd, $Rn, $Rm, $Ra";
  dag ResultInst = (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, NoV6];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4472 {	// InstAlias Requires
  string AsmString = "smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm";
  dag ResultInst = (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, NoV6];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4473 {	// InstAlias Requires
  string AsmString = "umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm";
  dag ResultInst = (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, NoV6];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4474 {	// InstAlias Requires
  string AsmString = "smull${s}${p} $RdLo, $RdHi, $Rn, $Rm";
  dag ResultInst = (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, NoV6];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_4475 {	// InstAlias Requires
  string AsmString = "umull${s}${p} $RdLo, $RdHi, $Rn, $Rm";
  dag ResultInst = (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsARM, NoV6];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def anonymous_448 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  string NAME = ?;
}
def anonymous_449 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_45 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_33, anonymous_38, anonymous_44];
  string NAME = ?;
}
def anonymous_450 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  string NAME = ?;
}
def anonymous_451 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_415, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_416, anonymous_205];
  string NAME = ?;
}
def anonymous_452 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  string NAME = ?;
}
def anonymous_453 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  string NAME = ?;
}
def anonymous_454 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_415, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_416, anonymous_205];
  string NAME = ?;
}
def anonymous_455 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  string NAME = ?;
}
def anonymous_456 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_205];
  string NAME = ?;
}
def anonymous_457 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  string NAME = ?;
}
def anonymous_458 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_205];
  string NAME = ?;
}
def anonymous_459 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  string NAME = ?;
}
def anonymous_46 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_35, anonymous_41, anonymous_47, anonymous_36, anonymous_42, anonymous_48];
  string NAME = ?;
}
def anonymous_460 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_461 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_462 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_463 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_464 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_465 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  string NAME = ?;
}
def anonymous_466 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_467 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  string NAME = ?;
}
def anonymous_468 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_469 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  string NAME = ?;
}
def anonymous_47 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "drdh";
  string NAME = ?;
}
def anonymous_470 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_471 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  string NAME = ?;
}
def anonymous_472 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_473 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  string NAME = ?;
}
def anonymous_474 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_475 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  string NAME = ?;
}
def anonymous_476 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_477 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  string NAME = ?;
}
def anonymous_478 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_479 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  string NAME = ?;
}
def anonymous_48 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "drdv";
  string NAME = ?;
}
def anonymous_480 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_481 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_482 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_483 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_484 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_485 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_486 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_487 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "SAMPLE_C_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_488 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_489 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_93];
  string NAME = ?;
}
def anonymous_49 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_31, anonymous_38, anonymous_50];
  string NAME = ?;
}
def anonymous_490 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_93];
  string NAME = ?;
}
def anonymous_491 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "slice";
  string NAME = ?;
}
def anonymous_492 {	// AMDGPUArg
  LLVMType Type = llvm_half_ty;
  string Name = "slice";
  string NAME = ?;
}
def anonymous_493 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_494 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_93];
  string NAME = ?;
}
def anonymous_495 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_496 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_93];
  string NAME = ?;
}
def anonymous_497 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_498 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_93];
  string NAME = ?;
}
def anonymous_499 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_5 {	// IntrinsicProperty ReadOnly
  int ArgNo = 1;
  string NAME = ?;
}
def anonymous_50 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "face";
  string NAME = ?;
}
def anonymous_500 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_501 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_502 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_503 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_504 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_505 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_506 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_507 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_508 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_509 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_511];
  string NAME = ?;
}
def anonymous_51 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_33, anonymous_38, anonymous_50];
  string NAME = ?;
}
def anonymous_510 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_511];
  string NAME = ?;
}
def anonymous_511 {	// AMDGPUArg
  LLVMType Type = anonymous_191;
  string Name = "slice";
  string NAME = ?;
}
def anonymous_512 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_513 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_511];
  string NAME = ?;
}
def anonymous_514 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_515 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_511];
  string NAME = ?;
}
def anonymous_516 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_517 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_511];
  string NAME = ?;
}
def anonymous_518 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_519 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_52 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_31, anonymous_53];
  string NAME = ?;
}
def anonymous_520 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_521 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_522 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_523 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_524 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_525 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_526 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_527 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_528 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_529 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_53 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "slice";
  string NAME = ?;
}
def anonymous_530 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_531 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_532 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_533 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_534 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_535 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_536 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_537 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_538 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_539 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_54 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_33, anonymous_53];
  string NAME = ?;
}
def anonymous_540 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_221, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_223, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_541 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  string NAME = ?;
}
def anonymous_542 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_221, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_223, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_543 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  string NAME = ?;
}
def anonymous_544 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_545 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  string NAME = ?;
}
def anonymous_546 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_547 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  string NAME = ?;
}
def anonymous_548 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_221, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_223, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_549 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_55 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_31, anonymous_38, anonymous_53];
  string NAME = ?;
}
def anonymous_550 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_221, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_223, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_551 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_552 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_553 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_554 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_555 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_556 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_221, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_223, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_557 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_221, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_223, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_558 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_559 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_56 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_33, anonymous_38, anonymous_53];
  string NAME = ?;
}
def anonymous_560 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_221, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_223, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_561 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_221, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_223, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_562 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_563 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "SAMPLE_C_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_219, anonymous_31, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_221, anonymous_148, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_223, anonymous_149, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_564 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_565 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_93];
  string NAME = ?;
}
def anonymous_566 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_93];
  string NAME = ?;
}
def anonymous_567 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_568 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_93];
  string NAME = ?;
}
def anonymous_569 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_57 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_31, anonymous_38, anonymous_58];
  string NAME = ?;
}
def anonymous_570 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  string NAME = ?;
}
def anonymous_571 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_572 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  string NAME = ?;
}
def anonymous_573 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_574 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_575 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_576 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_577 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_578 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_579 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_58 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "fragid";
  string NAME = ?;
}
def anonymous_580 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_581 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  string NAME = ?;
}
def anonymous_582 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_583 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_269, anonymous_511];
  string NAME = ?;
}
def anonymous_584 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_269, anonymous_511];
  string NAME = ?;
}
def anonymous_585 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_586 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_511];
  string NAME = ?;
}
def anonymous_587 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_588 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511];
  string NAME = ?;
}
def anonymous_589 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_59 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_33, anonymous_38, anonymous_58];
  string NAME = ?;
}
def anonymous_590 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511];
  string NAME = ?;
}
def anonymous_591 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_592 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_593 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_594 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_595 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_596 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_597 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_598 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_599 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_6 {	// LLVMType LLVMMatchType
  ValueType VT = OtherVT;
  int isAny = 0;
  int Number = 0;
  string NAME = ?;
}
def anonymous_60 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_31, anonymous_38, anonymous_53, anonymous_58];
  string NAME = ?;
}
def anonymous_600 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_601 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_602 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_603 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_604 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_605 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_606 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_607 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_608 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  string NAME = ?;
}
def anonymous_609 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_61 {	// makeArgList
  list<AMDGPUArg> ret = [anonymous_33, anonymous_38, anonymous_53, anonymous_58];
  string NAME = ?;
}
def anonymous_610 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_611 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_612 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_613 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_614 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  string NAME = ?;
}
def anonymous_615 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_616 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  string NAME = ?;
}
def anonymous_617 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_D";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_618 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  string NAME = ?;
}
def anonymous_619 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_D_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_62 {	// AMDGPUArg
  LLVMType Type = llvm_i32_ty;
  string Name = "offset";
  string NAME = ?;
}
def anonymous_620 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  string NAME = ?;
}
def anonymous_621 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_622 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_623 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_624 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_625 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_D_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_626 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_627 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_D_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_628 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  string NAME = ?;
}
def anonymous_629 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_63 {	// AMDGPUArg
  LLVMType Type = llvm_float_ty;
  string Name = "zcompare";
  string NAME = ?;
}
def anonymous_630 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_631 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_CD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_632 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_CD_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_633 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_634 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_635 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_CD_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_636 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "SAMPLE_C_CD_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 1;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_35, anonymous_301, anonymous_219, anonymous_302, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_220, anonymous_303, anonymous_221, anonymous_304, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_222, anonymous_305, anonymous_223, anonymous_306, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_637 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "GET_LOD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148];
  list<AMDGPUArg> AddrA16Args = [anonymous_149];
  string NAME = ?;
}
def anonymous_638 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GET_LOD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_639 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "GET_LOD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_332];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_333];
  string NAME = ?;
}
def anonymous_64 {	// AMDGPUArg
  LLVMType Type = llvm_anyfloat_ty;
  string Name = "bias";
  string NAME = ?;
}
def anonymous_640 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GET_LOD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_641 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "GET_LOD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_492];
  string NAME = ?;
}
def anonymous_642 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GET_LOD";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_643 {	// AMDGPUDimProfile AMDGPUDimGetResInfoProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "GET_RESINFO";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_65];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_114];
  string NAME = ?;
}
def anonymous_644 {	// AMDGPUDimProfile AMDGPUDimGetResInfoProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GET_RESINFO";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_65];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_114];
  string NAME = ?;
}
def anonymous_645 {	// AMDGPUDimProfile AMDGPUDimGetResInfoProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "GET_RESINFO";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_65];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_114];
  string NAME = ?;
}
def anonymous_646 {	// AMDGPUDimProfile AMDGPUDimGetResInfoProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GET_RESINFO";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_65];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_114];
  string NAME = ?;
}
def anonymous_647 {	// AMDGPUDimProfile AMDGPUDimGetResInfoProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "GET_RESINFO";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_65];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_114];
  string NAME = ?;
}
def anonymous_648 {	// AMDGPUDimProfile AMDGPUDimGetResInfoProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GET_RESINFO";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_65];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_114];
  string NAME = ?;
}
def anonymous_649 {	// AMDGPUDimProfile AMDGPUDimGetResInfoProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "GET_RESINFO";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_65];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_114];
  string NAME = ?;
}
def anonymous_65 {	// AMDGPUArg
  LLVMType Type = llvm_anyint_ty;
  string Name = "mip";
  string NAME = ?;
}
def anonymous_650 {	// AMDGPUDimProfile AMDGPUDimGetResInfoProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "GET_RESINFO";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "mip";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_65];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_113];
  list<AMDGPUArg> AddrA16Args = [anonymous_114];
  string NAME = ?;
}
def anonymous_651 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_652 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_653 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_654 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_655 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_656 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_657 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_658 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_659 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_66 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "LOAD";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_660 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_661 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_662 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_663 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_664 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_665 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_666 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_667 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_668 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_669 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_67 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33];
  string NAME = ?;
}
def anonymous_670 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_671 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_672 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_673 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_674 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_163];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_675 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_676 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_677 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_678 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_679 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_68 {	// arglistmatchshift
  list<AMDGPUArg> ret = [];
  string NAME = ?;
}
def anonymous_680 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_681 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_682 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_683 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_B";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_684 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_685 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_686 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_B_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_687 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_688 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_689 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_69 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33];
  string NAME = ?;
}
def anonymous_690 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_691 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_692 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_693 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_694 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_695 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_B_CL";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_696 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_165];
  string NAME = ?;
}
def anonymous_697 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_435, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_165];
  string NAME = ?;
}
def anonymous_698 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_B_CL_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_64, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "clamp";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_64, anonymous_63, anonymous_31, anonymous_269, anonymous_511, anonymous_192];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_177, anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_164];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_178, anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_165];
  string NAME = ?;
}
def anonymous_699 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_205];
  string NAME = ?;
}
def anonymous_7 {	// LLVMType LLVMAnyPointerType
  ValueType VT = iPTRAny;
  int isAny = 1;
  LLVMType ElTy = llvm_anyint_ty;
  string NAME = ?;
}
def anonymous_70 {	// AMDGPUArg
  LLVMType Type = llvm_i32_ty;
  string Name = "s";
  string NAME = ?;
}
def anonymous_700 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_415, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_416, anonymous_205];
  string NAME = ?;
}
def anonymous_701 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_702 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_205];
  string NAME = ?;
}
def anonymous_703 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_415, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_416, anonymous_205];
  string NAME = ?;
}
def anonymous_704 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_705 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_205];
  string NAME = ?;
}
def anonymous_706 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_205];
  string NAME = ?;
}
def anonymous_707 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_L";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_708 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_205];
  string NAME = ?;
}
def anonymous_709 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_415, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_416, anonymous_205];
  string NAME = ?;
}
def anonymous_71 {	// AMDGPUArg
  LLVMType Type = llvm_i16_ty;
  string Name = "s";
  string NAME = ?;
}
def anonymous_710 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_L_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "lod";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93, anonymous_203];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_491, anonymous_204];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_492, anonymous_205];
  string NAME = ?;
}
def anonymous_711 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_712 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_713 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_714 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_715 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_716 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_717 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_718 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_719 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_LZ";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_72 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "LOAD";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_720 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "GATHER4_C_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250];
  string NAME = ?;
}
def anonymous_721 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "GATHER4_C_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_415];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_416];
  string NAME = ?;
}
def anonymous_722 {	// AMDGPUDimProfile AMDGPUDimSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "GATHER4_C_LZ_O";
  bit IsSample = 1;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [anonymous_62, anonymous_63];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_62, anonymous_63, anonymous_31, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_62, anonymous_63, anonymous_148, anonymous_249, anonymous_491];
  list<AMDGPUArg> AddrA16Args = [anonymous_62, anonymous_63, anonymous_149, anonymous_250, anonymous_492];
  string NAME = ?;
}
def anonymous_723 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "vdata";
  string NAME = ?;
}
def anonymous_724 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_SWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_725 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_SWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_726 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_SWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_727 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_SWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_728 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_SWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_729 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_SWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_73 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75];
  string NAME = ?;
}
def anonymous_730 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_SWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_731 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_SWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_732 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_ADD";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_733 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_ADD";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_734 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_ADD";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_735 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_ADD";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_736 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_ADD";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_737 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_ADD";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_738 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_ADD";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_739 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_ADD";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_74 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75];
  string NAME = ?;
}
def anonymous_740 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_SUB";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_741 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_SUB";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_742 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_SUB";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_743 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_SUB";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_744 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_SUB";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_745 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_SUB";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_746 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_SUB";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_747 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_SUB";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_748 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_SMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_749 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_SMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_75 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "t";
  string NAME = ?;
}
def anonymous_750 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_SMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_751 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_SMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_752 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_SMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_753 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_SMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_754 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_SMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_755 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_SMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_756 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_UMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_757 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_UMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_758 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_UMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_759 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_UMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_76 {	// AMDGPUArg
  LLVMType Type = llvm_i32_ty;
  string Name = "t";
  string NAME = ?;
}
def anonymous_760 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_UMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_761 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_UMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_762 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_UMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_763 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_UMIN";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_764 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_SMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_765 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_SMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_766 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_SMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_767 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_SMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_768 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_SMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_769 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_SMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_77 {	// AMDGPUArg
  LLVMType Type = llvm_i16_ty;
  string Name = "t";
  string NAME = ?;
}
def anonymous_770 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_SMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_771 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_SMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_772 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_UMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_773 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_UMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_774 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_UMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_775 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_UMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_776 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_UMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_777 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_UMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_778 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_UMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_779 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_UMAX";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_78 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "LOAD";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_780 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_AND";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_781 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_AND";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_782 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_AND";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_783 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_AND";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_784 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_AND";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_785 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_AND";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_786 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_AND";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_787 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_AND";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_788 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_OR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_789 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_OR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_79 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_81];
  string NAME = ?;
}
def anonymous_790 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_OR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_791 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_OR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_792 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_OR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_793 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_OR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_794 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_OR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_795 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_OR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_796 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_XOR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_797 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_XOR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_798 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_XOR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_799 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_XOR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_8 {	// IntrinsicProperty ReadNone
  int ArgNo = 1;
  string NAME = ?;
}
def anonymous_80 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_81];
  string NAME = ?;
}
def anonymous_800 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_XOR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_801 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_XOR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_802 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_XOR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_803 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_XOR";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_804 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_INC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_805 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_INC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_806 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_INC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_807 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_INC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_808 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_INC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_809 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_INC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_81 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "r";
  string NAME = ?;
}
def anonymous_810 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_INC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_811 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_INC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_812 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_DEC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_813 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_DEC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_814 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_DEC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_815 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_DEC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_816 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_DEC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_817 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_DEC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_818 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_DEC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_819 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_DEC";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_723];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_82 {	// AMDGPUArg
  LLVMType Type = llvm_i32_ty;
  string Name = "r";
  string NAME = ?;
}
def anonymous_820 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "src";
  string NAME = ?;
}
def anonymous_821 {	// AMDGPUArg
  LLVMType Type = anonymous_6;
  string Name = "cmp";
  string NAME = ?;
}
def anonymous_822 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1D;
  string OpMod = "ATOMIC_CMPSWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_820, anonymous_821];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33];
  list<LLVMType> AddrTypes = [llvm_anyint_ty];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70];
  list<AMDGPUArg> AddrA16Args = [anonymous_71];
  string NAME = ?;
}
def anonymous_823 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2D;
  string OpMod = "ATOMIC_CMPSWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_820, anonymous_821];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77];
  string NAME = ?;
}
def anonymous_824 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim3D;
  string OpMod = "ATOMIC_CMPSWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_820, anonymous_821];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_81];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_82];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_83];
  string NAME = ?;
}
def anonymous_825 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "ATOMIC_CMPSWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_820, anonymous_821];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_826 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "ATOMIC_CMPSWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_820, anonymous_821];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_827 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "ATOMIC_CMPSWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_820, anonymous_821];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_828 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "ATOMIC_CMPSWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_820, anonymous_821];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_829 {	// AMDGPUDimProfile AMDGPUDimAtomicProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArrayMsaa;
  string OpMod = "ATOMIC_CMPSWAP";
  bit IsSample = 0;
  bit IsAtomic = 1;
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<AMDGPUArg> DataArgs = [anonymous_820, anonymous_821];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95, anonymous_104];
  string NAME = ?;
}
def anonymous_83 {	// AMDGPUArg
  LLVMType Type = llvm_i16_ty;
  string Name = "r";
  string NAME = ?;
}
def anonymous_830 {	// SDTypeConstraint SDTCisInt
  int OperandNum = 0;
  string NAME = ?;
}
def anonymous_831 {	// SDTypeConstraint SDTCisFP
  int OperandNum = 0;
  string NAME = ?;
}
def anonymous_832 {	// SDTypeConstraint SDTCisPtrTy
  int OperandNum = 0;
  string NAME = ?;
}
def anonymous_833 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 0;
  ValueType VT = OtherVT;
  string NAME = ?;
}
def anonymous_834 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 0;
  int OtherOperandNum = 1;
  string NAME = ?;
}
def anonymous_835 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 0;
  int OtherOperandNum = 2;
  string NAME = ?;
}
def anonymous_836 {	// SDTypeConstraint SDTCisInt
  int OperandNum = 2;
  string NAME = ?;
}
def anonymous_837 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 0;
  int OtherOperandNum = 3;
  string NAME = ?;
}
def anonymous_838 {	// SDTypeConstraint SDTCisFP
  int OperandNum = 2;
  string NAME = ?;
}
def anonymous_839 {	// SDTypeConstraint SDTCisInt
  int OperandNum = 1;
  string NAME = ?;
}
def anonymous_84 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDimCube;
  string OpMod = "LOAD";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_87];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_88];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_89];
  string NAME = ?;
}
def anonymous_840 {	// SDTypeConstraint SDTCisOpSmallerThanOp
  int OperandNum = 1;
  int BigOperandNum = 0;
  string NAME = ?;
}
def anonymous_841 {	// SDTypeConstraint SDTCisSameNumEltsAs
  int OperandNum = 0;
  int OtherOperandNum = 1;
  string NAME = ?;
}
def anonymous_842 {	// SDTypeConstraint SDTCisOpSmallerThanOp
  int OperandNum = 0;
  int BigOperandNum = 1;
  string NAME = ?;
}
def anonymous_843 {	// SDTypeConstraint SDTCisFP
  int OperandNum = 1;
  string NAME = ?;
}
def anonymous_844 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 2;
  ValueType VT = OtherVT;
  string NAME = ?;
}
def anonymous_845 {	// SDTypeConstraint SDTCisVTSmallerThanOp
  int OperandNum = 2;
  int OtherOperandNum = 1;
  string NAME = ?;
}
def anonymous_846 {	// SDTypeConstraint SDTCisVec
  int OperandNum = 0;
  string NAME = ?;
}
def anonymous_847 {	// SDTypeConstraint SDTCisVec
  int OperandNum = 1;
  string NAME = ?;
}
def anonymous_848 {	// SDTypeConstraint SDTCisSameSizeAs
  int OperandNum = 0;
  int OtherOperandNum = 1;
  string NAME = ?;
}
def anonymous_849 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 1;
  int OtherOperandNum = 2;
  string NAME = ?;
}
def anonymous_85 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_87];
  string NAME = ?;
}
def anonymous_850 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 3;
  ValueType VT = OtherVT;
  string NAME = ?;
}
def anonymous_851 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 2;
  int OtherOperandNum = 3;
  string NAME = ?;
}
def anonymous_852 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 3;
  int OtherOperandNum = 4;
  string NAME = ?;
}
def anonymous_853 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 5;
  ValueType VT = OtherVT;
  string NAME = ?;
}
def anonymous_854 {	// SDTypeConstraint SDTCisVT
  int OperandNum = 1;
  ValueType VT = OtherVT;
  string NAME = ?;
}
def anonymous_855 {	// SDTypeConstraint SDTCisPtrTy
  int OperandNum = 1;
  string NAME = ?;
}
def anonymous_856 {	// SDTypeConstraint SDTCisPtrTy
  int OperandNum = 3;
  string NAME = ?;
}
def anonymous_857 {	// SDTypeConstraint SDTCisVec
  int OperandNum = 2;
  string NAME = ?;
}
def anonymous_858 {	// SDTypeConstraint SDTCisSameNumEltsAs
  int OperandNum = 1;
  int OtherOperandNum = 2;
  string NAME = ?;
}
def anonymous_859 {	// SDTypeConstraint SDTCisSameNumEltsAs
  int OperandNum = 0;
  int OtherOperandNum = 2;
  string NAME = ?;
}
def anonymous_86 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_87];
  string NAME = ?;
}
def anonymous_860 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 1;
  int OtherOperandNum = 3;
  string NAME = ?;
}
def anonymous_861 {	// SDTypeConstraint SDTCisPtrTy
  int OperandNum = 4;
  string NAME = ?;
}
def anonymous_862 {	// SDTypeConstraint SDTCVecEltisVT
  int OperandNum = 1;
  ValueType VT = i1;
  string NAME = ?;
}
def anonymous_863 {	// SDTypeConstraint SDTCVecEltisVT
  int OperandNum = 0;
  ValueType VT = i1;
  string NAME = ?;
}
def anonymous_864 {	// SDTypeConstraint SDTCisEltOfVec
  int OperandNum = 0;
  int OtherOpNum = 1;
  string NAME = ?;
}
def anonymous_865 {	// SDTypeConstraint SDTCisPtrTy
  int OperandNum = 2;
  string NAME = ?;
}
def anonymous_866 {	// SDTypeConstraint SDTCisEltOfVec
  int OperandNum = 2;
  int OtherOpNum = 1;
  string NAME = ?;
}
def anonymous_867 {	// SDTypeConstraint SDTCisSubVecOfVec
  int OperandNum = 0;
  int OtherOpNum = 1;
  string NAME = ?;
}
def anonymous_868 {	// SDTypeConstraint SDTCisSubVecOfVec
  int OperandNum = 2;
  int OtherOpNum = 1;
  string NAME = ?;
}
def anonymous_869 {	// SDTypeConstraint SDTCisInt
  int OperandNum = 3;
  string NAME = ?;
}
def anonymous_87 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "face";
  string NAME = ?;
}
def anonymous_870 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 0;
  int OtherOperandNum = 4;
  string NAME = ?;
}
def anonymous_871 {	// SDTypeConstraint SDTCisPtrTy
  int OperandNum = 5;
  string NAME = ?;
}
def anonymous_872 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = -1;
  list<SDTypeConstraint> Constraints = [];
  string NAME = ?;
}
def anonymous_873 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 1;
  list<SDTypeConstraint> Constraints = [];
  string NAME = ?;
}
def anonymous_874 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_865];
  string NAME = ?;
}
def anonymous_875 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 3;
  list<SDTypeConstraint> Constraints = [anonymous_834, anonymous_856];
  string NAME = ?;
}
def anonymous_876 {	// SDTypeConstraint SDTCisSubVecOfVec
  int OperandNum = 1;
  int OtherOpNum = 0;
  string NAME = ?;
}
def anonymous_877 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_876, anonymous_849];
  string NAME = ?;
}
def anonymous_878 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = 2;
  list<SDTypeConstraint> Constraints = [anonymous_836, anonymous_847, anonymous_846];
  string NAME = ?;
}
def anonymous_879 {	// SDTypeProfile
  int NumResults = 0;
  int NumOperands = -1;
  list<SDTypeConstraint> Constraints = [anonymous_832];
  string NAME = ?;
}
def anonymous_88 {	// AMDGPUArg
  LLVMType Type = llvm_i32_ty;
  string Name = "face";
  string NAME = ?;
}
def anonymous_880 {	// SDTypeProfile
  int NumResults = 1;
  int NumOperands = -1;
  list<SDTypeConstraint> Constraints = [anonymous_855];
  string NAME = ?;
}
def anonymous_881 {	// SDTypeConstraint SDTCisSameAs
  int OperandNum = 1;
  int OtherOperandNum = 0;
  string NAME = ?;
}
def anonymous_882 {	// GINodeEquiv
  Instruction I = G_ANYEXT;
  SDNode Node = anyext;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_883 {	// GINodeEquiv
  Instruction I = G_SEXT;
  SDNode Node = sext;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_884 {	// GINodeEquiv
  Instruction I = G_ZEXT;
  SDNode Node = zext;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_885 {	// GINodeEquiv
  Instruction I = G_TRUNC;
  SDNode Node = trunc;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_886 {	// GINodeEquiv
  Instruction I = G_BITCAST;
  SDNode Node = bitconvert;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_887 {	// GINodeEquiv
  Instruction I = G_CONSTANT;
  SDNode Node = imm;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_888 {	// GINodeEquiv
  Instruction I = G_FCONSTANT;
  SDNode Node = fpimm;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_889 {	// GINodeEquiv
  Instruction I = G_ADD;
  SDNode Node = add;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_89 {	// AMDGPUArg
  LLVMType Type = llvm_i16_ty;
  string Name = "face";
  string NAME = ?;
}
def anonymous_890 {	// GINodeEquiv
  Instruction I = G_SUB;
  SDNode Node = sub;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_891 {	// GINodeEquiv
  Instruction I = G_MUL;
  SDNode Node = mul;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_892 {	// GINodeEquiv
  Instruction I = G_SDIV;
  SDNode Node = sdiv;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_893 {	// GINodeEquiv
  Instruction I = G_UDIV;
  SDNode Node = udiv;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_894 {	// GINodeEquiv
  Instruction I = G_SREM;
  SDNode Node = srem;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_895 {	// GINodeEquiv
  Instruction I = G_UREM;
  SDNode Node = urem;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_896 {	// GINodeEquiv
  Instruction I = G_AND;
  SDNode Node = and;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_897 {	// GINodeEquiv
  Instruction I = G_OR;
  SDNode Node = or;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_898 {	// GINodeEquiv
  Instruction I = G_XOR;
  SDNode Node = xor;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_899 {	// GINodeEquiv
  Instruction I = G_SHL;
  SDNode Node = shl;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_9 {	// IntrinsicProperty ReadOnly
  int ArgNo = 2;
  string NAME = ?;
}
def anonymous_90 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim1DArray;
  string OpMod = "LOAD";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_95];
  string NAME = ?;
}
def anonymous_900 {	// GINodeEquiv
  Instruction I = G_LSHR;
  SDNode Node = srl;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_901 {	// GINodeEquiv
  Instruction I = G_ASHR;
  SDNode Node = sra;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_902 {	// GINodeEquiv
  Instruction I = G_SELECT;
  SDNode Node = select;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_903 {	// GINodeEquiv
  Instruction I = G_FNEG;
  SDNode Node = fneg;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_904 {	// GINodeEquiv
  Instruction I = G_FPEXT;
  SDNode Node = fpextend;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_905 {	// GINodeEquiv
  Instruction I = G_FPTRUNC;
  SDNode Node = fpround;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_906 {	// GINodeEquiv
  Instruction I = G_FPTOSI;
  SDNode Node = fp_to_sint;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_907 {	// GINodeEquiv
  Instruction I = G_FPTOUI;
  SDNode Node = fp_to_uint;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_908 {	// GINodeEquiv
  Instruction I = G_SITOFP;
  SDNode Node = sint_to_fp;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_909 {	// GINodeEquiv
  Instruction I = G_UITOFP;
  SDNode Node = uint_to_fp;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_91 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_93];
  string NAME = ?;
}
def anonymous_910 {	// GINodeEquiv
  Instruction I = G_FADD;
  SDNode Node = fadd;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_911 {	// GINodeEquiv
  Instruction I = G_FSUB;
  SDNode Node = fsub;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_912 {	// GINodeEquiv
  Instruction I = G_FMA;
  SDNode Node = fma;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_913 {	// GINodeEquiv
  Instruction I = G_FMUL;
  SDNode Node = fmul;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_914 {	// GINodeEquiv
  Instruction I = G_FDIV;
  SDNode Node = fdiv;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_915 {	// GINodeEquiv
  Instruction I = G_FREM;
  SDNode Node = frem;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_916 {	// GINodeEquiv
  Instruction I = G_FPOW;
  SDNode Node = fpow;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_917 {	// GINodeEquiv
  Instruction I = G_FEXP2;
  SDNode Node = fexp2;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_918 {	// GINodeEquiv
  Instruction I = G_FLOG2;
  SDNode Node = flog2;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_919 {	// GINodeEquiv
  Instruction I = G_INTRINSIC;
  SDNode Node = intrinsic_wo_chain;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_92 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_93];
  string NAME = ?;
}
def anonymous_920 {	// GINodeEquiv
  Instruction I = G_INTRINSIC_W_SIDE_EFFECTS;
  SDNode Node = intrinsic_void;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_921 {	// GINodeEquiv
  Instruction I = G_INTRINSIC_W_SIDE_EFFECTS;
  SDNode Node = intrinsic_w_chain;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_922 {	// GINodeEquiv
  Instruction I = G_BR;
  SDNode Node = br;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_923 {	// GINodeEquiv
  Instruction I = G_BSWAP;
  SDNode Node = bswap;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_924 {	// GINodeEquiv
  Instruction I = G_LOAD;
  SDNode Node = ld;
  bit CheckMMOIsNonAtomic = 1;
  Instruction IfSignExtend = G_SEXTLOAD;
  Instruction IfZeroExtend = G_ZEXTLOAD;
  string NAME = ?;
}
def anonymous_925 {	// GINodeEquiv
  Instruction I = G_STORE;
  SDNode Node = st;
  bit CheckMMOIsNonAtomic = 1;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_926 {	// GINodeEquiv
  Instruction I = G_ATOMIC_CMPXCHG;
  SDNode Node = atomic_cmp_swap;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_927 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_XCHG;
  SDNode Node = atomic_swap;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_928 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_ADD;
  SDNode Node = atomic_load_add;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_929 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_SUB;
  SDNode Node = atomic_load_sub;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_93 {	// AMDGPUArg
  LLVMType Type = anonymous_19;
  string Name = "slice";
  string NAME = ?;
}
def anonymous_930 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_AND;
  SDNode Node = atomic_load_and;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_931 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_NAND;
  SDNode Node = atomic_load_nand;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_932 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_OR;
  SDNode Node = atomic_load_or;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_933 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_XOR;
  SDNode Node = atomic_load_xor;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_934 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_MIN;
  SDNode Node = atomic_load_min;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_935 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_MAX;
  SDNode Node = atomic_load_max;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_936 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_UMIN;
  SDNode Node = atomic_load_umin;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_937 {	// GINodeEquiv
  Instruction I = G_ATOMICRMW_UMAX;
  SDNode Node = atomic_load_umax;
  bit CheckMMOIsNonAtomic = 0;
  Instruction IfSignExtend = ?;
  Instruction IfZeroExtend = ?;
  string NAME = ?;
}
def anonymous_938 {	// PredicateProlog
  code Code = [{
  const ARMBaseInstrInfo *TII =
    static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
  (void)TII;
  const ARMSubtarget *STI =
    static_cast<const ARMSubtarget*>(SchedModel->getSubtargetInfo());
  (void)STI;
}];
  string NAME = ?;
}
def anonymous_939 {	// InstrStage
  int Cycles = 1;
  list<FuncUnit> Units = [V6_Pipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_94 {	// AMDGPUArg
  LLVMType Type = llvm_i32_ty;
  string Name = "slice";
  string NAME = ?;
}
def anonymous_940 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUx;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_941 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_942 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_943 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_944 {	// InstrStage
  int Cycles = 2;
  list<FuncUnit> Units = [V6_Pipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_945 {	// InstrItinData
  InstrItinClass TheClass = IIC_iALUsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [3, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_946 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_947 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_948 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_949 {	// InstrItinData
  InstrItinClass TheClass = IIC_iBITsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [3, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_95 {	// AMDGPUArg
  LLVMType Type = llvm_i16_ty;
  string Name = "slice";
  string NAME = ?;
}
def anonymous_950 {	// InstrItinData
  InstrItinClass TheClass = IIC_iUNAr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_951 {	// InstrItinData
  InstrItinClass TheClass = IIC_iUNAsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_952 {	// InstrItinData
  InstrItinClass TheClass = IIC_iEXTr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_953 {	// InstrItinData
  InstrItinClass TheClass = IIC_iEXTAr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_954 {	// InstrItinData
  InstrItinClass TheClass = IIC_iEXTAsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [3, 3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_955 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_956 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_957 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_958 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMPsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_959 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_96 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DArray;
  string OpMod = "LOAD";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_93];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_94];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_95];
  string NAME = ?;
}
def anonymous_960 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_961 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_962 {	// InstrItinData
  InstrItinClass TheClass = IIC_iTSTsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_963 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_964 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_965 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_966 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_967 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVix2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939, anonymous_939];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_968 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVix2addpc;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939, anonymous_939, anonymous_939];
  list<int> OperandCycles = [3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_969 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMOVix2ld;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939, anonymous_939, anonymous_939];
  list<int> OperandCycles = [5];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_97 {	// arglistconcat
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_93];
  string NAME = ?;
}
def anonymous_970 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [3];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_971 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [3, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_972 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [3, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_973 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_974 {	// InstrItinData
  InstrItinClass TheClass = IIC_iCMOVix2;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939, anonymous_939];
  list<int> OperandCycles = [4];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_975 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_976 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_977 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNsi;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_978 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMVNsr;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [3, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_979 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMUL16;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_98 {	// arglistmatchshift
  list<AMDGPUArg> ret = [anonymous_33, anonymous_75, anonymous_93];
  string NAME = ?;
}
def anonymous_980 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMAC16;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_981 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMUL32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [5, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_982 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMAC32;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [5, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_983 {	// InstrStage
  int Cycles = 3;
  list<FuncUnit> Units = [V6_Pipe];
  int TimeInc = -1;
  int Kind = 0;
  string NAME = ?;
}
def anonymous_984 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMUL64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [6, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_985 {	// InstrItinData
  InstrItinClass TheClass = IIC_iMAC64;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_983];
  list<int> OperandCycles = [6, 1, 1, 2];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_986 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_987 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_988 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_d_i;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_989 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_99 {	// AMDGPUDimProfile AMDGPUDimNoSampleProfile
  AMDGPUDimProps Dim = AMDGPUDim2DMsaa;
  string OpMod = "LOAD";
  bit IsSample = 0;
  bit IsAtomic = 0;
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<AMDGPUArg> DataArgs = [];
  list<AMDGPUArg> ExtraAddrArgs = [];
  bit Gradients = 0;
  string LodClampMip = "";
  int NumRetAndDataAnyTypes = 1;
  list<AMDGPUArg> AddrArgs = [anonymous_33, anonymous_75, anonymous_102];
  list<LLVMType> AddrTypes = [llvm_anyint_ty, anonymous_19, anonymous_19];
  list<AMDGPUArg> AddrDefaultArgs = [anonymous_70, anonymous_76, anonymous_103];
  list<AMDGPUArg> AddrA16Args = [anonymous_71, anonymous_77, anonymous_104];
  string NAME = ?;
}
def anonymous_990 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_991 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_d_r;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_992 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [5, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_993 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_si;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [5, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_994 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_995 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_iu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_996 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_997 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_bh_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_998 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_d_ru;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_939];
  list<int> OperandCycles = [4, 2, 1, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anonymous_999 {	// InstrItinData
  InstrItinClass TheClass = IIC_iLoad_siu;
  int NumMicroOps = 1;
  list<InstrStage> Stages = [anonymous_944];
  list<int> OperandCycles = [5, 2, 2, 1];
  list<Bypass> Bypasses = [];
  string NAME = ?;
}
def anyext {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ANY_EXTEND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntExtendOp;
  string NAME = ?;
}
def arm_bl_target {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getARMBLTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ARMBranchTarget;
  string NAME = ?;
}
def arm_blx_target {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getARMBLXTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ThumbBranchTarget;
  string NAME = ?;
}
def arm_br_target {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = OtherVT;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getARMBranchTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ARMBranchTarget;
  string NAME = ?;
}
def arm_cmpfp {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPOutGlue];
  string Opcode = "ARMISD::CMPFP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_ARMFCmp;
  string NAME = ?;
}
def arm_cmpfp0 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPOutGlue];
  string Opcode = "ARMISD::CMPFPw0";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_CMPFP0;
  string NAME = ?;
}
def arm_fmdrr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMOVDRR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_VMOVDRR;
  string NAME = ?;
}
def arm_fmrrd {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMOVRRD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_VMOVRRD;
  string NAME = ?;
}
def arm_fmstat {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPInGlue, SDNPOutGlue];
  string Opcode = "ARMISD::FMSTAT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTNone;
  string NAME = ?;
}
def arm_i32imm {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
  if (Subtarget->useMovt(*MF))
    return true;
  return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def arm_vmovhr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMOVhr";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_VMOVhr;
  string NAME = ?;
}
def arm_vmovrh {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMOVrh";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_VMOVrh;
  string NAME = ?;
}
def arm_vmovsr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ARMISD::VMOVSR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_VMOVSR;
  string NAME = ?;
}
def assertsext {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::AssertSext";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_assertext;
  string NAME = ?;
}
def assertzext {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::AssertZext";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_assertext;
  string NAME = ?;
}
def atomic_cmp_swap {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_CMP_SWAP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic3;
  string NAME = ?;
}
def atomic_cmp_swap_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_16 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_16 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_16 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_16 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_16 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_32 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_32 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_32 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_32 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_32 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_64 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_64 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_64 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_64 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_64 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_8 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_8 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_8 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_8 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_cmp_swap_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$cmp, node:$val);
  dag Fragment = (atomic_cmp_swap_8 node:$ptr, node:$cmp, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_fence {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ISD::ATOMIC_FENCE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomicFence;
  string NAME = ?;
}
def atomic_load {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomicLoad;
  string NAME = ?;
}
def atomic_load_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (atomic_load node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (atomic_load node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (atomic_load node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (atomic_load node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_acquire_16 {	// SDPatternOperator PatFrag acquiring_load
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (atomic_load_16 node:$ptr);
  code PredicateCode = [{
  AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
  return isAcquireOrStronger(Ordering);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_acquire_32 {	// SDPatternOperator PatFrag acquiring_load
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (atomic_load_32 node:$ptr);
  code PredicateCode = [{
  AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
  return isAcquireOrStronger(Ordering);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_acquire_8 {	// SDPatternOperator PatFrag acquiring_load
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (atomic_load_8 node:$ptr);
  code PredicateCode = [{
  AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
  return isAcquireOrStronger(Ordering);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_ADD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_add_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_add_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_add_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_AND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_and_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_and_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_and_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_CLR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_clr_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_clr_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_clr_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_MAX";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_max_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_max_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_max_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_MIN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_min_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_min_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_min_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_NAND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_nand_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_nand_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_nand_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_OR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_or_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_or_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_or_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_SUB";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_sub_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_sub_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_sub_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_UMAX";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_umax_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umax_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umax_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_UMIN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_umin_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_umin_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_umin_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_LOAD_XOR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_load_xor_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_load_xor_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_load_xor_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_STORE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomicStore;
  string NAME = ?;
}
def atomic_store_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_release_16 {	// SDPatternOperator PatFrag releasing_store
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_16 node:$ptr, node:$val);
  code PredicateCode = [{
  AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
  return isReleaseOrStronger(Ordering);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_release_32 {	// SDPatternOperator PatFrag releasing_store
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_32 node:$ptr, node:$val);
  code PredicateCode = [{
  AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
  return isReleaseOrStronger(Ordering);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_store_release_8 {	// SDPatternOperator PatFrag releasing_store
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_store_8 node:$ptr, node:$val);
  code PredicateCode = [{
  AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
  return isReleaseOrStronger(Ordering);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::ATOMIC_SWAP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTAtomic2;
  string NAME = ?;
}
def atomic_swap_16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_16_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_16_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_16_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_16_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_16_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_16 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_32_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_32_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_32_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_32_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_32_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_32 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_64_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_64_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_64_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_64_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_64_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_64 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_8_acq_rel {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = 1;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_8_acquire {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = 1;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_8_monotonic {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = 1;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_8_release {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = 1;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def atomic_swap_8_seq_cst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr, node:$val);
  dag Fragment = (atomic_swap_8 node:$ptr, node:$val);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = 1;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = 1;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def banked_reg {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeBankedReg";
  ValueType Type = i32;
  string PrintMethod = "printBankedRegOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = BankedRegOperand;
  string NAME = ?;
}
def bb {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::BasicBlock";
  string SDClass = "BasicBlockSDNode";
  SDTypeProfile TypeProfile = SDTOther;
  string NAME = ?;
}
def bf_inv_mask_imm {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeBitfieldMaskOperand";
  ValueType Type = i32;
  string PrintMethod = "printBitfieldInvMaskImmOperand";
  string EncoderMethod = "getBitfieldInvertedMaskOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = BitfieldAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
  return ARM::isBitFieldInvertedMask(N->getZExtValue());
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def bitconvert {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::BITCAST";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTUnaryOp;
  string NAME = ?;
}
def bitreverse {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::BITREVERSE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def blockaddress {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::BlockAddress";
  string SDClass = "BlockAddressSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def br {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ISD::BR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTBr;
  string NAME = ?;
}
def brcc {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ISD::BR_CC";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTBrCC;
  string NAME = ?;
}
def brcond {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ISD::BRCOND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTBrcond;
  string NAME = ?;
}
def brind {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ISD::BRIND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTBrind;
  string NAME = ?;
}
def brtarget {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2BROperand";
  ValueType Type = OtherVT;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getBranchTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def bswap {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::BSWAP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def build_vector {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::BUILD_VECTOR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_872;
  string NAME = ?;
}
def byte_alignedload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (load node:$ptr);
  code PredicateCode = [{
  return cast<LoadSDNode>(N)->getAlignment() == 1;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def byte_alignedstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (store node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<StoreSDNode>(N)->getAlignment() == 1;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def c_imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printCImmediate";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = CoprocRegAsmOperand;
  string NAME = ?;
}
def catchpad {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ISD::CATCHPAD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTNone;
  string NAME = ?;
}
def catchret {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ISD::CATCHRET";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTCatchret;
  string NAME = ?;
}
def cc_out {	// DAGOperand Operand OperandWithDefaultOps OptionalDefOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeCCOutOperand";
  ValueType Type = OtherVT;
  string PrintMethod = "printSBitModifierOperand";
  string EncoderMethod = "getCCOutOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops CCR);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = CCOutOperand;
  dag DefaultOps = (ops (i32 zero_reg));
  string NAME = ?;
}
def cleanupret {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ISD::CLEANUPRET";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTNone;
  string NAME = ?;
}
def cmovpred {	// DAGOperand Operand PredicateOp ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printPredicateOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops i32imm, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectCMOVPred";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def complexrotateop {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printComplexRotationOp<90, 0>";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_3110;
  string NAME = ?;
}
def complexrotateopodd {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printComplexRotationOp<180, 90>";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = anonymous_3111;
  string NAME = ?;
}
def concat_vectors {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::CONCAT_VECTORS";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_877;
  string NAME = ?;
}
def cond {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::CONDCODE";
  string SDClass = "CondCodeSDNode";
  SDTypeProfile TypeProfile = SDTOther;
  string NAME = ?;
}
def const_pool_asm_imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = const_pool_asm_operand;
  string NAME = ?;
}
def const_pool_asm_operand {	// AsmOperandClass
  string Name = "ConstPoolAsmImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def constpool {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ConstantPool";
  string SDClass = "ConstantPoolSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def coproc_option_imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printCoprocOptionImm";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = CoprocOptionAsmOperand;
  string NAME = ?;
}
def cpinst_operand {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printCPInstOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def ctlz {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::CTLZ";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def ctlz_zero_undef {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::CTLZ_ZERO_UNDEF";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def ctpop {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::CTPOP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def cttz {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::CTTZ";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def cttz_zero_undef {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::CTTZ_ZERO_UNDEF";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntUnaryOp;
  string NAME = ?;
}
def debugtrap {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ISD::DEBUGTRAP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTNone;
  string NAME = ?;
}
def decimate {
  string NAME = ?;
}
def dpr_reglist {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeDPRRegListOperand";
  ValueType Type = i32;
  string PrintMethod = "printRegisterList";
  string EncoderMethod = "getRegisterListOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = DPRRegListAsmOperand;
  string NAME = ?;
}
def dsub_0 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 64;
  int Offset = 0;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def dsub_1 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 64;
  int Offset = 64;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def dsub_2 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 64;
  int Offset = 128;
  list<SubRegIndex> ComposedOf = [qsub_1, dsub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def dsub_3 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 64;
  int Offset = 192;
  list<SubRegIndex> ComposedOf = [qsub_1, dsub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def dsub_4 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 64;
  int Offset = 256;
  list<SubRegIndex> ComposedOf = [qsub_2, dsub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def dsub_5 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 64;
  int Offset = 320;
  list<SubRegIndex> ComposedOf = [qsub_2, dsub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def dsub_6 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 64;
  int Offset = 384;
  list<SubRegIndex> ComposedOf = [qsub_3, dsub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def dsub_7 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 64;
  int Offset = 448;
  list<SubRegIndex> ComposedOf = [qsub_3, dsub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def dword_alignedload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (load node:$ptr);
  code PredicateCode = [{
  return cast<LoadSDNode>(N)->getAlignment() >= 8;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def dword_alignedstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (store node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<StoreSDNode>(N)->getAlignment() >= 8;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def externalsym {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ExternalSymbol";
  string SDClass = "ExternalSymbolSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def extload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (unindexedload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = 1;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def extloadf32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = f32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def extloadf64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = f64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def extloadi1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i1;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def extloadi16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def extloadi32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def extloadi8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def extloadvf32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = f32;
  string NAME = ?;
}
def extloadvf64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = f64;
  string NAME = ?;
}
def extloadvi1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i1;
  string NAME = ?;
}
def extloadvi16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i16;
  string NAME = ?;
}
def extloadvi32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i32;
  string NAME = ?;
}
def extloadvi8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (extload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i8;
  string NAME = ?;
}
def extract_subvector {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::EXTRACT_SUBVECTOR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTSubVecExtract;
  string NAME = ?;
}
def extractelt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::EXTRACT_VECTOR_ELT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTVecExtract;
  string NAME = ?;
}
def f128 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 12;
  string NAME = ?;
}
def f16 {	// ValueType
  string Namespace = "MVT";
  int Size = 16;
  int Value = 8;
  string NAME = ?;
}
def f16_to_fp {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FP16_TO_FP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntToFPOp;
  string NAME = ?;
}
def f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 9;
  string NAME = ?;
}
def f32imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = f32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def f64 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 10;
  string NAME = ?;
}
def f64imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = f64;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def f80 {	// ValueType
  string Namespace = "MVT";
  int Size = 80;
  int Value = 11;
  string NAME = ?;
}
def fAny {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 252;
  string NAME = ?;
}
def fabs {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FABS";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fadd {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative];
  string Opcode = "ISD::FADD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def fadd_mlx {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (fadd node:$lhs, node:$rhs);
  code PredicateCode = [{
  return hasNoVMLxHazardUse(N);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def fbits16 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printFBits16";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = fbits16_asm_operand;
  string NAME = ?;
}
def fbits16_asm_operand {	// AsmOperandClass
  string Name = "FBits16";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def fbits32 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printFBits32";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = fbits32_asm_operand;
  string NAME = ?;
}
def fbits32_asm_operand {	// AsmOperandClass
  string Name = "FBits32";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def fcanonicalize {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FCANONICALIZE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fceil {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FCEIL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fcopysign {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FCOPYSIGN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPSignOp;
  string NAME = ?;
}
def fcos {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FCOS";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fdiv {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FDIV";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def fexp2 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FEXP2";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def ffloor {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FFLOOR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fgetsign {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FGETSIGN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPToIntOp;
  string NAME = ?;
}
def flog2 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FLOG2";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fma {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FMA";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPTernaryOp;
  string NAME = ?;
}
def fmad {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FMAD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPTernaryOp;
  string NAME = ?;
}
def fmaxnan {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FMAXNAN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def fmaxnum {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::FMAXNUM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def fminnan {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FMINNAN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def fminnum {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::FMINNUM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def fmul {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative];
  string Opcode = "ISD::FMUL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def fmul_su {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (fmul node:$lhs, node:$rhs);
  code PredicateCode = [{
  return N->hasOneUse();
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def fnearbyint {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FNEARBYINT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fneg {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FNEG";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fp_to_f16 {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FP_TO_FP16";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPToIntOp;
  string NAME = ?;
}
def fp_to_sint {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FP_TO_SINT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPToIntOp;
  string NAME = ?;
}
def fp_to_uint {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FP_TO_UINT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPToIntOp;
  string NAME = ?;
}
def fpextend {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FP_EXTEND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPExtendOp;
  string NAME = ?;
}
def fpimm {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ConstantFP";
  string SDClass = "ConstantFPSDNode";
  SDTypeProfile TypeProfile = SDTFPLeaf;
  string NAME = ?;
}
def fpow {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FPOW";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def fpround {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FP_ROUND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPRoundOp;
  string NAME = ?;
}
def frameindex {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FrameIndex";
  string SDClass = "FrameIndexSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def frem {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FREM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def frint {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FRINT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fround {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FROUND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fsin {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FSIN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fsqrt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FSQRT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def fsub {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FSUB";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPBinOp;
  string NAME = ?;
}
def fsub_mlx {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (fsub node:$lhs, node:$rhs);
  code PredicateCode = [{
  return hasNoVMLxHazardUse(N);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def ftrunc {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::FTRUNC";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTFPUnaryOp;
  string NAME = ?;
}
def globaladdr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::GlobalAddress";
  string SDClass = "GlobalAddressSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def globaltlsaddr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::GlobalTLSAddress";
  string SDClass = "GlobalAddressSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def gsub_0 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 0;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def gsub_1 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 32;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def hGPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (sub GPR, tGPR);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [r8, r15]";
  string NAME = ?;
}
def hi16 {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def hword_alignedload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (load node:$ptr);
  code PredicateCode = [{
  return cast<LoadSDNode>(N)->getAlignment() == 2;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def hword_alignedstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (store node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<StoreSDNode>(N)->getAlignment() == 2;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 1;
  int Value = 2;
  string NAME = ?;
}
def i128 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 7;
  string NAME = ?;
}
def i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 16;
  int Value = 4;
  string NAME = ?;
}
def i16imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i16;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def i1imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i1;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 5;
  string NAME = ?;
}
def i32imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 6;
  string NAME = ?;
}
def i64imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i64;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 8;
  int Value = 3;
  string NAME = ?;
}
def i8imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i8;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def iAny {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 253;
  string NAME = ?;
}
def iPTR {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 254;
  string NAME = ?;
}
def iPTRAny {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 250;
  string NAME = ?;
}
def iflags_op {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printCPSIFlag";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ProcIFlagsOperand;
  string NAME = ?;
}
def imm {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::Constant";
  string SDClass = "ConstantSDNode";
  SDTypeProfile TypeProfile = SDTIntLeaf;
  string NAME = ?;
}
def imm0_1 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_1AsmOperand;
  string NAME = ?;
}
def imm0_15 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_15AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 0 && Imm < 16;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_239 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_239AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm >= 0 && Imm < 240; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_255 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_255AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm >= 0 && Imm < 256; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_255_comp {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{
  return ~((uint32_t)N->getZExtValue()) < 256;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def imm0_255_not {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{
  return (uint32_t)(~N->getZExtValue()) < 255;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_not_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def imm0_3 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_3AsmOperand;
  string NAME = ?;
}
def imm0_31 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_31AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 0 && Imm < 32;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_32 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_32AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 0 && Imm < 33;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_4095 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = imm0_4095_asmoperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 0 && Imm < 4096;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_4095_asmoperand {	// AsmOperandClass ImmAsmOperand
  string Name = "Imm0_4095";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<0,4095>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [0,4095]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def imm0_4095_neg {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = imm0_4095_neg_asmoperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{
 return (uint32_t)(-N->getZExtValue()) < 4096;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_neg_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def imm0_4095_neg_asmoperand {	// AsmOperandClass
  string Name = "Imm0_4095Neg";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def imm0_63 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_63AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 0 && Imm < 64;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_65535 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_65535AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 0 && Imm < 65536;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_65535_expr {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getHiLo16ImmOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_65535ExprAsmOperand;
  string NAME = ?;
}
def imm0_65535_neg {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return -Imm >= 0 && -Imm < 65536;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_7 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm0_7AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 0 && Imm < 8;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm0_7_neg {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{
  return (uint32_t)-N->getZExtValue() < 8;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_neg_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def imm16 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm16AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm == 16; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm16_31 {	// SDPatternOperator PatFrag ImmLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm1_15 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm1_15AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm > 0 && Imm < 16; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm1_16 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printImmPlusOneOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm1_16AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
    return Imm > 0 && Imm <= 16;
  }];
  SDNodeXForm OperandTransform = imm1_16_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm1_16_XFORM {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def imm1_255_neg {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{
  uint32_t Val = -N->getZExtValue();
  return (Val > 0 && Val < 255);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_neg_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def imm1_31 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm1_31AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm > 0 && Imm < 32; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm1_32 {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printImmPlusOneOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm1_32AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
   uint64_t Imm = N->getZExtValue();
   return Imm > 0 && Imm <= 32;
 }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm1_32_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def imm1_32_XFORM {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def imm1_7 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm1_7AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm > 0 && Imm < 8; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm24b {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm24bitAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 0 && Imm <= 0xffffff;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm256_510 {	// SDPatternOperator PatFrag ImmLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 256 && Imm < 511;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm256_65535_expr {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm256_65535ExprAsmOperand;
  string NAME = ?;
}
def imm32 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm32AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm == 32; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm8 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm8AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm == 8; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm8_255 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = Imm8_255AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm >= 8 && Imm < 256;
}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def imm8_255_neg {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{
  unsigned Val = -N->getZExtValue();
  return Val >= 8 && Val < 256;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_neg_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def imm8_or_16 {	// SDPatternOperator PatFrag ImmLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm == 8 || Imm == 16;}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def immAllOnesV {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (build_vector);
  code PredicateCode = [{
  return ISD::isBuildVectorAllOnes(N);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def immAllZerosV {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (build_vector);
  code PredicateCode = [{
  return ISD::isBuildVectorAllZeros(N);
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def imm_neg_XFORM {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def imm_not_XFORM {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def imm_sr {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printThumbSRImm";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ThumbSRImmAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
  uint64_t Imm = N->getZExtValue();
  return Imm > 0 && Imm <= 32;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_sr_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def imm_sr_XFORM {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  unsigned Imm = N->getZExtValue();
  return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def imod_op {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printCPSIMod";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def implicit {
  string NAME = ?;
}
def ineg {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$in);
  dag Fragment = (sub 0, node:$in);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def ins {
  string NAME = ?;
}
def insert_subvector {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::INSERT_SUBVECTOR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTSubVecInsert;
  string NAME = ?;
}
def insertelt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::INSERT_VECTOR_ELT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTVecInsert;
  string NAME = ?;
}
def instregex {
  string NAME = ?;
}
def instrs {
  string NAME = ?;
}
def instsyncb_opt {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeInstSyncBarrierOption";
  ValueType Type = i32;
  string PrintMethod = "printInstSyncBOption";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = InstSyncBarrierOptOperand;
  string NAME = ?;
}
def int_aarch64_clrex {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crc32b {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crc32cb {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crc32ch {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crc32cw {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crc32cx {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crc32h {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crc32w {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crc32x {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_aesd {	// SDPatternOperator Intrinsic Crypto_AES_DataKey_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_aese {	// SDPatternOperator Intrinsic Crypto_AES_DataKey_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_aesimc {	// SDPatternOperator Intrinsic Crypto_AES_Data_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_aesmc {	// SDPatternOperator Intrinsic Crypto_AES_Data_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha1c {	// SDPatternOperator Intrinsic Crypto_SHA_5Hash4Schedule_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha1h {	// SDPatternOperator Intrinsic Crypto_SHA_1Hash_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha1m {	// SDPatternOperator Intrinsic Crypto_SHA_5Hash4Schedule_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha1p {	// SDPatternOperator Intrinsic Crypto_SHA_5Hash4Schedule_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha1su0 {	// SDPatternOperator Intrinsic Crypto_SHA_12Schedule_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha1su1 {	// SDPatternOperator Intrinsic Crypto_SHA_8Schedule_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha256h {	// SDPatternOperator Intrinsic Crypto_SHA_8Hash4Schedule_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha256h2 {	// SDPatternOperator Intrinsic Crypto_SHA_8Hash4Schedule_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha256su0 {	// SDPatternOperator Intrinsic Crypto_SHA_8Schedule_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_crypto_sha256su1 {	// SDPatternOperator Intrinsic Crypto_SHA_12Schedule_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_dmb {	// GCCBuiltin MSBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_dmb";
  string MSBuiltinName = "__dmb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_dsb {	// GCCBuiltin MSBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_dsb";
  string MSBuiltinName = "__dsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_hint {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_isb {	// GCCBuiltin MSBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_isb";
  string MSBuiltinName = "__isb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_ldaxp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_ldaxr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_ldxp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_ldxr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_abs {	// SDPatternOperator Intrinsic AdvSIMD_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_any_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_addhn {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_addp {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_cls {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fabd {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_facge {	// SDPatternOperator Intrinsic AdvSIMD_2Arg_FloatCompare_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_facgt {	// SDPatternOperator Intrinsic AdvSIMD_2Arg_FloatCompare_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_faddv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Float_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtas {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtau {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtms {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtmu {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtns {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtnu {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtps {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtpu {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtxn {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Expand_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtzs {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fcvtzu {	// SDPatternOperator Intrinsic AdvSIMD_FPToIntRounding_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fmax {	// SDPatternOperator Intrinsic AdvSIMD_2FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fmaxnm {	// SDPatternOperator Intrinsic AdvSIMD_2FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fmaxnmp {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fmaxnmv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Float_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fmaxp {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fmaxv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Float_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fmin {	// SDPatternOperator Intrinsic AdvSIMD_2FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fminnm {	// SDPatternOperator Intrinsic AdvSIMD_2FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fminnmp {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fminnmv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Float_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fminp {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fminv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Float_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_fmulx {	// SDPatternOperator Intrinsic AdvSIMD_2FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_frecpe {	// SDPatternOperator Intrinsic AdvSIMD_1FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_frecps {	// SDPatternOperator Intrinsic AdvSIMD_2FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_frecpx {	// SDPatternOperator Intrinsic AdvSIMD_1FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_frintn {	// SDPatternOperator Intrinsic AdvSIMD_1FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_frsqrte {	// SDPatternOperator Intrinsic AdvSIMD_1FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_frsqrts {	// SDPatternOperator Intrinsic AdvSIMD_2FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld1x2 {	// SDPatternOperator Intrinsic AdvSIMD_2Vec_Load_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld1x3 {	// SDPatternOperator Intrinsic AdvSIMD_3Vec_Load_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld1x4 {	// SDPatternOperator Intrinsic AdvSIMD_4Vec_Load_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld2 {	// SDPatternOperator Intrinsic AdvSIMD_2Vec_Load_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld2lane {	// SDPatternOperator Intrinsic AdvSIMD_2Vec_Load_Lane_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld2r {	// SDPatternOperator Intrinsic AdvSIMD_2Vec_Load_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld3 {	// SDPatternOperator Intrinsic AdvSIMD_3Vec_Load_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld3lane {	// SDPatternOperator Intrinsic AdvSIMD_3Vec_Load_Lane_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld3r {	// SDPatternOperator Intrinsic AdvSIMD_3Vec_Load_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld4 {	// SDPatternOperator Intrinsic AdvSIMD_4Vec_Load_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld4lane {	// SDPatternOperator Intrinsic AdvSIMD_4Vec_Load_Lane_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ld4r {	// SDPatternOperator Intrinsic AdvSIMD_4Vec_Load_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_pmul {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_pmull {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Long_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_pmull64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_raddhn {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_rbit {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_rshrn {	// SDPatternOperator Intrinsic AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_rsubhn {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sabd {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_saddlp {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Expand_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_saddlv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Int_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_saddv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Int_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_scalar_sqxtn {	// SDPatternOperator Intrinsic AdvSIMD_1IntArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_scalar_sqxtun {	// SDPatternOperator Intrinsic AdvSIMD_1IntArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_scalar_uqxtn {	// SDPatternOperator Intrinsic AdvSIMD_1IntArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sdot {	// SDPatternOperator Intrinsic AdvSIMD_Dot_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_shadd {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_shll {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_shsub {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_smax {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_smaxp {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_smaxv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Int_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_smin {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sminp {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sminv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Int_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_smull {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Long_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqabs {	// SDPatternOperator Intrinsic AdvSIMD_1IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqadd {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqdmulh {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqdmull {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Long_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqdmulls_scalar {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqneg {	// SDPatternOperator Intrinsic AdvSIMD_1IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqrdmulh {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqrshl {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqrshrn {	// SDPatternOperator Intrinsic AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqrshrun {	// SDPatternOperator Intrinsic AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqshl {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqshlu {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqshrn {	// SDPatternOperator Intrinsic AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqshrun {	// SDPatternOperator Intrinsic AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqsub {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqxtn {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sqxtun {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_srhadd {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_srshl {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sshl {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_sshll {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_st1x2 {	// SDPatternOperator Intrinsic AdvSIMD_2Vec_Store_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_st1x3 {	// SDPatternOperator Intrinsic AdvSIMD_3Vec_Store_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_st1x4 {	// SDPatternOperator Intrinsic AdvSIMD_4Vec_Store_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6, anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_st2 {	// SDPatternOperator Intrinsic AdvSIMD_2Vec_Store_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_st2lane {	// SDPatternOperator Intrinsic AdvSIMD_2Vec_Store_Lane_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_st3 {	// SDPatternOperator Intrinsic AdvSIMD_3Vec_Store_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_st3lane {	// SDPatternOperator Intrinsic AdvSIMD_3Vec_Store_Lane_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_st4 {	// SDPatternOperator Intrinsic AdvSIMD_4Vec_Store_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6, anonymous_12];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_st4lane {	// SDPatternOperator Intrinsic AdvSIMD_4Vec_Store_Lane_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_23];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_subhn {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_suqadd {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_tbl1 {	// SDPatternOperator Intrinsic AdvSIMD_Tbl1_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_tbl2 {	// SDPatternOperator Intrinsic AdvSIMD_Tbl2_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_tbl3 {	// SDPatternOperator Intrinsic AdvSIMD_Tbl3_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_tbl4 {	// SDPatternOperator Intrinsic AdvSIMD_Tbl4_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_tbx1 {	// SDPatternOperator Intrinsic AdvSIMD_Tbx1_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_tbx2 {	// SDPatternOperator Intrinsic AdvSIMD_Tbx2_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_tbx3 {	// SDPatternOperator Intrinsic AdvSIMD_Tbx3_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_tbx4 {	// SDPatternOperator Intrinsic AdvSIMD_Tbx4_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uabd {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uaddlp {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Expand_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uaddlv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Int_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uaddv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Int_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_udot {	// SDPatternOperator Intrinsic AdvSIMD_Dot_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uhadd {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uhsub {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_umax {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_umaxp {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_umaxv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Int_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_umin {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uminp {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uminv {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Int_Across_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_umull {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Long_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uqadd {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uqrshl {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uqrshrn {	// SDPatternOperator Intrinsic AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uqshl {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uqshrn {	// SDPatternOperator Intrinsic AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uqsub {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_uqxtn {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_urecpe {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_urhadd {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_urshl {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ursqrte {	// SDPatternOperator Intrinsic AdvSIMD_1VectorArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ushl {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_ushll {	// SDPatternOperator Intrinsic AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_usqadd {	// SDPatternOperator Intrinsic AdvSIMD_2IntArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_vcopy_lane {	// SDPatternOperator Intrinsic AdvSIMD_2Vector2Index_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, llvm_i64_ty, anonymous_6, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_vcvtfp2fxs {	// SDPatternOperator Intrinsic AdvSIMD_CvtFPToFx_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_vcvtfp2fxu {	// SDPatternOperator Intrinsic AdvSIMD_CvtFPToFx_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_vcvtfp2hf {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_vcvtfxs2fp {	// SDPatternOperator Intrinsic AdvSIMD_CvtFxToFP_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_vcvtfxu2fp {	// SDPatternOperator Intrinsic AdvSIMD_CvtFxToFP_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_vcvthf2fp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_vsli {	// SDPatternOperator Intrinsic AdvSIMD_3VectorArg_Scalar_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_neon_vsri {	// SDPatternOperator Intrinsic AdvSIMD_3VectorArg_Scalar_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_sdiv {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_sisd_fabd {	// SDPatternOperator Intrinsic AdvSIMD_2Scalar_Float_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_sisd_fcvtxn {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_stlxp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_stlxr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_stxp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_stxr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_aarch64_udiv {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "aarch64";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_addressofreturnaddress {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_adjust_trampoline {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_adjust_trampoline";
  string NAME = ?;
}
def int_amdgcn_alignbit {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_alignbyte {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_atomic_dec {	// SDPatternOperator Intrinsic AMDGPUAtomicIncIntrin
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, anonymous_6, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_atomic_inc {	// SDPatternOperator Intrinsic AMDGPUAtomicIncIntrin
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, anonymous_6, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_break {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_add {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_and {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_cmpswap {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_or {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_smax {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_smin {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_sub {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_swap {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_umax {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_umin {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_atomic_xor {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_load {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferLoad
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 0;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_load_format {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferLoad
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 0;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_store {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferStore
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_store_format {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUBufferStore
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_wbinvl1 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_buffer_wbinvl1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_wbinvl1_sc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_buffer_wbinvl1_sc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_buffer_wbinvl1_vol {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_buffer_wbinvl1_vol";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_class {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cos {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cubeid {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_cubeid";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cubema {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_cubema";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cubesc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_cubesc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cubetc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_cubetc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cvt_pk_i16 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cvt_pk_u16 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cvt_pk_u8_f32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_cvt_pk_u8_f32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cvt_pknorm_i16 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cvt_pknorm_u16 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_cvt_pkrtz {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_dispatch_id {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_dispatch_id";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_dispatch_ptr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_dispatch_ptr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [anonymous_28];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_div_fixup {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_div_fmas {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_div_scale {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_ds_bpermute {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_ds_bpermute";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_ds_fadd {	// GCCBuiltin SDPatternOperator Intrinsic AMDGPULDSF32Intrin
  string GCCBuiltinName = "__builtin_amdgcn_ds_faddf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [anonymous_29, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_ds_fmax {	// GCCBuiltin SDPatternOperator Intrinsic AMDGPULDSF32Intrin
  string GCCBuiltinName = "__builtin_amdgcn_ds_fmaxf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [anonymous_29, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_ds_fmin {	// GCCBuiltin SDPatternOperator Intrinsic AMDGPULDSF32Intrin
  string GCCBuiltinName = "__builtin_amdgcn_ds_fminf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [anonymous_29, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_ds_permute {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_ds_permute";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_ds_swizzle {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_ds_swizzle";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_else {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i1_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_else_break {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_end_cf {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_exp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_any_ty, anonymous_6, anonymous_6, anonymous_6, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_exp_compr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, anonymous_6, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_fcmp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, anonymous_6, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_fdiv_fast {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_fdot2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_fdot2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_fmed3 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_fmed3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_fmul_legacy {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_fmul_legacy";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_fract {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_frexp_exp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_frexp_mant {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_groupstaticsize {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_groupstaticsize";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_icmp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, anonymous_6, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_if {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i1_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_if_break {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_image_atomic_add {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_add_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_732;
  string NAME = ?;
}
def int_amdgcn_image_atomic_add_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_736;
  string NAME = ?;
}
def int_amdgcn_image_atomic_add_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_733;
  string NAME = ?;
}
def int_amdgcn_image_atomic_add_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_737;
  string NAME = ?;
}
def int_amdgcn_image_atomic_add_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_739;
  string NAME = ?;
}
def int_amdgcn_image_atomic_add_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_738;
  string NAME = ?;
}
def int_amdgcn_image_atomic_add_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_734;
  string NAME = ?;
}
def int_amdgcn_image_atomic_add_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_735;
  string NAME = ?;
}
def int_amdgcn_image_atomic_and {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_and_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_780;
  string NAME = ?;
}
def int_amdgcn_image_atomic_and_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_784;
  string NAME = ?;
}
def int_amdgcn_image_atomic_and_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_781;
  string NAME = ?;
}
def int_amdgcn_image_atomic_and_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_785;
  string NAME = ?;
}
def int_amdgcn_image_atomic_and_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_787;
  string NAME = ?;
}
def int_amdgcn_image_atomic_and_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_786;
  string NAME = ?;
}
def int_amdgcn_image_atomic_and_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_782;
  string NAME = ?;
}
def int_amdgcn_image_atomic_and_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_783;
  string NAME = ?;
}
def int_amdgcn_image_atomic_cmpswap {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_cmpswap_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_822;
  string NAME = ?;
}
def int_amdgcn_image_atomic_cmpswap_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_826;
  string NAME = ?;
}
def int_amdgcn_image_atomic_cmpswap_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_823;
  string NAME = ?;
}
def int_amdgcn_image_atomic_cmpswap_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_827;
  string NAME = ?;
}
def int_amdgcn_image_atomic_cmpswap_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_829;
  string NAME = ?;
}
def int_amdgcn_image_atomic_cmpswap_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_828;
  string NAME = ?;
}
def int_amdgcn_image_atomic_cmpswap_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_824;
  string NAME = ?;
}
def int_amdgcn_image_atomic_cmpswap_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_825;
  string NAME = ?;
}
def int_amdgcn_image_atomic_dec {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_dec_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_812;
  string NAME = ?;
}
def int_amdgcn_image_atomic_dec_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_816;
  string NAME = ?;
}
def int_amdgcn_image_atomic_dec_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_813;
  string NAME = ?;
}
def int_amdgcn_image_atomic_dec_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_817;
  string NAME = ?;
}
def int_amdgcn_image_atomic_dec_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_819;
  string NAME = ?;
}
def int_amdgcn_image_atomic_dec_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_818;
  string NAME = ?;
}
def int_amdgcn_image_atomic_dec_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_814;
  string NAME = ?;
}
def int_amdgcn_image_atomic_dec_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_815;
  string NAME = ?;
}
def int_amdgcn_image_atomic_inc {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_inc_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_804;
  string NAME = ?;
}
def int_amdgcn_image_atomic_inc_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_808;
  string NAME = ?;
}
def int_amdgcn_image_atomic_inc_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_805;
  string NAME = ?;
}
def int_amdgcn_image_atomic_inc_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_809;
  string NAME = ?;
}
def int_amdgcn_image_atomic_inc_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_811;
  string NAME = ?;
}
def int_amdgcn_image_atomic_inc_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_810;
  string NAME = ?;
}
def int_amdgcn_image_atomic_inc_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_806;
  string NAME = ?;
}
def int_amdgcn_image_atomic_inc_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_807;
  string NAME = ?;
}
def int_amdgcn_image_atomic_or {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_or_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_788;
  string NAME = ?;
}
def int_amdgcn_image_atomic_or_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_792;
  string NAME = ?;
}
def int_amdgcn_image_atomic_or_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_789;
  string NAME = ?;
}
def int_amdgcn_image_atomic_or_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_793;
  string NAME = ?;
}
def int_amdgcn_image_atomic_or_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_795;
  string NAME = ?;
}
def int_amdgcn_image_atomic_or_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_794;
  string NAME = ?;
}
def int_amdgcn_image_atomic_or_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_790;
  string NAME = ?;
}
def int_amdgcn_image_atomic_or_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_791;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smax {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smax_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_764;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smax_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_768;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smax_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_765;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smax_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_769;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smax_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_771;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smax_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_770;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smax_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_766;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smax_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_767;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smin {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smin_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_748;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smin_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_752;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smin_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_749;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smin_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_753;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smin_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_755;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smin_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_754;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smin_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_750;
  string NAME = ?;
}
def int_amdgcn_image_atomic_smin_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_751;
  string NAME = ?;
}
def int_amdgcn_image_atomic_sub {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_sub_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_740;
  string NAME = ?;
}
def int_amdgcn_image_atomic_sub_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_744;
  string NAME = ?;
}
def int_amdgcn_image_atomic_sub_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_741;
  string NAME = ?;
}
def int_amdgcn_image_atomic_sub_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_745;
  string NAME = ?;
}
def int_amdgcn_image_atomic_sub_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_747;
  string NAME = ?;
}
def int_amdgcn_image_atomic_sub_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_746;
  string NAME = ?;
}
def int_amdgcn_image_atomic_sub_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_742;
  string NAME = ?;
}
def int_amdgcn_image_atomic_sub_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_743;
  string NAME = ?;
}
def int_amdgcn_image_atomic_swap {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_swap_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_724;
  string NAME = ?;
}
def int_amdgcn_image_atomic_swap_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_728;
  string NAME = ?;
}
def int_amdgcn_image_atomic_swap_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_725;
  string NAME = ?;
}
def int_amdgcn_image_atomic_swap_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_729;
  string NAME = ?;
}
def int_amdgcn_image_atomic_swap_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_731;
  string NAME = ?;
}
def int_amdgcn_image_atomic_swap_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_730;
  string NAME = ?;
}
def int_amdgcn_image_atomic_swap_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_726;
  string NAME = ?;
}
def int_amdgcn_image_atomic_swap_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_727;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umax {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umax_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_772;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umax_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_776;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umax_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_773;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umax_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_777;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umax_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_779;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umax_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_778;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umax_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_774;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umax_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_775;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umin {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umin_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_756;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umin_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_760;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umin_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_757;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umin_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_761;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umin_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_763;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umin_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_762;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umin_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_758;
  string NAME = ?;
}
def int_amdgcn_image_atomic_umin_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_759;
  string NAME = ?;
}
def int_amdgcn_image_atomic_xor {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageAtomic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_atomic_xor_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_796;
  string NAME = ?;
}
def int_amdgcn_image_atomic_xor_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_800;
  string NAME = ?;
}
def int_amdgcn_image_atomic_xor_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_797;
  string NAME = ?;
}
def int_amdgcn_image_atomic_xor_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_801;
  string NAME = ?;
}
def int_amdgcn_image_atomic_xor_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_803;
  string NAME = ?;
}
def int_amdgcn_image_atomic_xor_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_802;
  string NAME = ?;
}
def int_amdgcn_image_atomic_xor_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_798;
  string NAME = ?;
}
def int_amdgcn_image_atomic_xor_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_799;
  string NAME = ?;
}
def int_amdgcn_image_gather4 {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_651;
  string NAME = ?;
}
def int_amdgcn_image_gather4_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_653;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_675;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_677;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_687;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_689;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_688;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_690;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_692;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_691;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_676;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_678;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_680;
  string NAME = ?;
}
def int_amdgcn_image_gather4_b_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_679;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_657;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_659;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_681;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_683;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_693;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_695;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_694;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_696;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_698;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_697;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_682;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_684;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_686;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_b_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_685;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_669;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_671;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_670;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_672;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_674;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_673;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_658;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_l {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_l_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_705;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_l_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_707;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_l_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_706;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_l_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_l_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_708;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_l_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_710;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_l_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_709;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_lz {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_lz_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_717;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_lz_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_719;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_lz_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_718;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_lz_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_lz_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_720;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_lz_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_722;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_lz_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_721;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_660;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_662;
  string NAME = ?;
}
def int_amdgcn_image_gather4_c_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_661;
  string NAME = ?;
}
def int_amdgcn_image_gather4_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_663;
  string NAME = ?;
}
def int_amdgcn_image_gather4_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_665;
  string NAME = ?;
}
def int_amdgcn_image_gather4_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_664;
  string NAME = ?;
}
def int_amdgcn_image_gather4_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_666;
  string NAME = ?;
}
def int_amdgcn_image_gather4_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_668;
  string NAME = ?;
}
def int_amdgcn_image_gather4_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_667;
  string NAME = ?;
}
def int_amdgcn_image_gather4_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_652;
  string NAME = ?;
}
def int_amdgcn_image_gather4_l {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_l_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_699;
  string NAME = ?;
}
def int_amdgcn_image_gather4_l_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_701;
  string NAME = ?;
}
def int_amdgcn_image_gather4_l_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_700;
  string NAME = ?;
}
def int_amdgcn_image_gather4_l_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_l_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_702;
  string NAME = ?;
}
def int_amdgcn_image_gather4_l_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_704;
  string NAME = ?;
}
def int_amdgcn_image_gather4_l_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_703;
  string NAME = ?;
}
def int_amdgcn_image_gather4_lz {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_lz_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_711;
  string NAME = ?;
}
def int_amdgcn_image_gather4_lz_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_713;
  string NAME = ?;
}
def int_amdgcn_image_gather4_lz_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_712;
  string NAME = ?;
}
def int_amdgcn_image_gather4_lz_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_lz_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_714;
  string NAME = ?;
}
def int_amdgcn_image_gather4_lz_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_716;
  string NAME = ?;
}
def int_amdgcn_image_gather4_lz_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_715;
  string NAME = ?;
}
def int_amdgcn_image_gather4_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_gather4_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_654;
  string NAME = ?;
}
def int_amdgcn_image_gather4_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_656;
  string NAME = ?;
}
def int_amdgcn_image_gather4_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_655;
  string NAME = ?;
}
def int_amdgcn_image_getlod {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_getlod_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_637;
  string NAME = ?;
}
def int_amdgcn_image_getlod_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_641;
  string NAME = ?;
}
def int_amdgcn_image_getlod_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_638;
  string NAME = ?;
}
def int_amdgcn_image_getlod_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_642;
  string NAME = ?;
}
def int_amdgcn_image_getlod_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_639;
  string NAME = ?;
}
def int_amdgcn_image_getlod_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_640;
  string NAME = ?;
}
def int_amdgcn_image_getresinfo {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageLoad
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_anyint_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_getresinfo_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_643;
  string NAME = ?;
}
def int_amdgcn_image_getresinfo_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_647;
  string NAME = ?;
}
def int_amdgcn_image_getresinfo_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_644;
  string NAME = ?;
}
def int_amdgcn_image_getresinfo_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_648;
  string NAME = ?;
}
def int_amdgcn_image_getresinfo_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_650;
  string NAME = ?;
}
def int_amdgcn_image_getresinfo_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_649;
  string NAME = ?;
}
def int_amdgcn_image_getresinfo_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_645;
  string NAME = ?;
}
def int_amdgcn_image_getresinfo_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_646;
  string NAME = ?;
}
def int_amdgcn_image_load {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageLoad
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_anyint_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_load_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_66;
  string NAME = ?;
}
def int_amdgcn_image_load_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_90;
  string NAME = ?;
}
def int_amdgcn_image_load_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_72;
  string NAME = ?;
}
def int_amdgcn_image_load_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_96;
  string NAME = ?;
}
def int_amdgcn_image_load_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_105;
  string NAME = ?;
}
def int_amdgcn_image_load_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_99;
  string NAME = ?;
}
def int_amdgcn_image_load_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_78;
  string NAME = ?;
}
def int_amdgcn_image_load_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_84;
  string NAME = ?;
}
def int_amdgcn_image_load_mip {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageLoad
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_anyint_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_load_mip_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_108;
  string NAME = ?;
}
def int_amdgcn_image_load_mip_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_124;
  string NAME = ?;
}
def int_amdgcn_image_load_mip_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_115;
  string NAME = ?;
}
def int_amdgcn_image_load_mip_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_127;
  string NAME = ?;
}
def int_amdgcn_image_load_mip_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_118;
  string NAME = ?;
}
def int_amdgcn_image_load_mip_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_121;
  string NAME = ?;
}
def int_amdgcn_image_sample {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_145;
  string NAME = ?;
}
def int_amdgcn_image_sample_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_488;
  string NAME = ?;
}
def int_amdgcn_image_sample_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_246;
  string NAME = ?;
}
def int_amdgcn_image_sample_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_564;
  string NAME = ?;
}
def int_amdgcn_image_sample_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_329;
  string NAME = ?;
}
def int_amdgcn_image_sample_b {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_172;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_508;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_266;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_582;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_349;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_188;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_518;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_276;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_591;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_359;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_442;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_193;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_521;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_279;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_594;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_362;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_445;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_432;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_179;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_512;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_270;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_585;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_353;
  string NAME = ?;
}
def int_amdgcn_image_sample_b_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_436;
  string NAME = ?;
}
def int_amdgcn_image_sample_c {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_153;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_495;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_253;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_569;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_336;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_182;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_514;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_272;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_587;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_355;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_195;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_523;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_281;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_596;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_364;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_447;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_197;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_525;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_283;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_598;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_366;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_449;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_438;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_185;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_516;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_274;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_589;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_357;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_b_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_440;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_240;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_558;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_323;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_631;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_406;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_244;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_562;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_327;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_635;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 12;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_410;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_486;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_245;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_563;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_328;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_636;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 13;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_411;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_487;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_482;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_241;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_559;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_324;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_632;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 12;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_407;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cd_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_483;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_168;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_504;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_262;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_578;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_345;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_428;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_170;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_506;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_264;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_580;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_347;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_430;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_419;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_226;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_544;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_309;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_617;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_392;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_234;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_552;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_317;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_625;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 12;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_400;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_476;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_236;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_554;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_319;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_627;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 13;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_402;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_478;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_468;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_228;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_546;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_311;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_619;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 12;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_394;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_d_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_470;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_208;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_532;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_290;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_605;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_373;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_456;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_210;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_534;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_292;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_607;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_375;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_l_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_458;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_214;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_538;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_296;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_611;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_379;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_462;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_215;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_539;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_297;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_612;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_380;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_lz_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_463;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_156;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_497;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_255;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_571;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_338;
  string NAME = ?;
}
def int_amdgcn_image_sample_c_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_421;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_238;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_556;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_321;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_629;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_404;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_242;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_560;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_325;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_633;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_408;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_484;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_243;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_561;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_326;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_634;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 12;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_409;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_485;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_480;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_239;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_557;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_322;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_630;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_405;
  string NAME = ?;
}
def int_amdgcn_image_sample_cd_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_481;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_159;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_499;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_257;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_573;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_340;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_423;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_166;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_502;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_260;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_576;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_343;
  string NAME = ?;
}
def int_amdgcn_image_sample_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_426;
  string NAME = ?;
}
def int_amdgcn_image_sample_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_412;
  string NAME = ?;
}
def int_amdgcn_image_sample_d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_216;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_540;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_298;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_613;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_381;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_230;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_548;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_313;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_621;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_396;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_472;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_232;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 7;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_550;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_315;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_623;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 12;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_398;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cl_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 10;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_474;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_464;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_224;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_542;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 8;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_307;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_615;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 11;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_390;
  string NAME = ?;
}
def int_amdgcn_image_sample_d_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_anyfloat_ty, anonymous_191, anonymous_191, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 9;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_466;
  string NAME = ?;
}
def int_amdgcn_image_sample_l {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_199;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_527;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_285;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_600;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_368;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_451;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_206;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_530;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_288;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_603;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_371;
  string NAME = ?;
}
def int_amdgcn_image_sample_l_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_454;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_212;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_536;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_294;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_609;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_377;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_460;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_213;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_537;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_295;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_610;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_378;
  string NAME = ?;
}
def int_amdgcn_image_sample_lz_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_461;
  string NAME = ?;
}
def int_amdgcn_image_sample_o {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageSample
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_sample_o_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_150;
  string NAME = ?;
}
def int_amdgcn_image_sample_o_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_493;
  string NAME = ?;
}
def int_amdgcn_image_sample_o_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_251;
  string NAME = ?;
}
def int_amdgcn_image_sample_o_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_567;
  string NAME = ?;
}
def int_amdgcn_image_sample_o_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_334;
  string NAME = ?;
}
def int_amdgcn_image_sample_o_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_anyfloat_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_417;
  string NAME = ?;
}
def int_amdgcn_image_store {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageStore
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_anyint_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_store_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 3;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_131;
  string NAME = ?;
}
def int_amdgcn_image_store_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_135;
  string NAME = ?;
}
def int_amdgcn_image_store_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_132;
  string NAME = ?;
}
def int_amdgcn_image_store_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_136;
  string NAME = ?;
}
def int_amdgcn_image_store_2darraymsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_138;
  string NAME = ?;
}
def int_amdgcn_image_store_2dmsaa {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_137;
  string NAME = ?;
}
def int_amdgcn_image_store_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_133;
  string NAME = ?;
}
def int_amdgcn_image_store_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_134;
  string NAME = ?;
}
def int_amdgcn_image_store_mip {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageStore
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyint_ty, llvm_anyint_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 2;
  bit IsImage = 1;
  string NAME = ?;
}
def int_amdgcn_image_store_mip_1d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 4;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_139;
  string NAME = ?;
}
def int_amdgcn_image_store_mip_1darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_143;
  string NAME = ?;
}
def int_amdgcn_image_store_mip_2d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 5;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_140;
  string NAME = ?;
}
def int_amdgcn_image_store_mip_2darray {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_144;
  string NAME = ?;
}
def int_amdgcn_image_store_mip_3d {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_141;
  string NAME = ?;
}
def int_amdgcn_image_store_mip_cube {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic AMDGPUImageDimIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty, llvm_anyint_ty, anonymous_19, anonymous_19, anonymous_19, llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 6;
  bit IsImage = 1;
  AMDGPUDimProfile P = anonymous_142;
  string NAME = ?;
}
def int_amdgcn_implicit_buffer_ptr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_implicit_buffer_ptr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [anonymous_28];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_implicitarg_ptr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_implicitarg_ptr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [anonymous_28];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_init_exec {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_init_exec_from_input {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_interp_mov {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_interp_mov";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_interp_p1 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_interp_p1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_interp_p2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_interp_p2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_kernarg_segment_ptr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_kernarg_segment_ptr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [anonymous_28];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_kill {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_ldexp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_lerp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_lerp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_log_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_loop {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_mbcnt_hi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_mbcnt_hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_mbcnt_lo {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_mbcnt_lo";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_mov_dpp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_mqsad_pk_u16_u8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_mqsad_pk_u16_u8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_mqsad_u32_u8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_mqsad_u32_u8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_msad_u8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_msad_u8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_ps_live {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_qsad_pk_u16_u8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_qsad_pk_u16_u8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_queue_ptr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_queue_ptr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [anonymous_28];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_rcp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_rcp_legacy {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_rcp_legacy";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_readfirstlane {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_readfirstlane";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_readlane {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_readlane";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_rsq {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_rsq_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_rsq_legacy {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_rsq_legacy";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_barrier {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_barrier";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_dcache_inv {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_dcache_inv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_dcache_inv_vol {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_dcache_inv_vol";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_dcache_wb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_dcache_wb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_dcache_wb_vol {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_dcache_wb_vol";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_decperflevel {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_decperflevel";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_getpc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_getpc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_getreg {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_getreg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_incperflevel {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_incperflevel";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_memrealtime {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_memrealtime";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_memtime {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_memtime";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_sendmsg {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_sendmsg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_sendmsghalt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_sendmsghalt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_sleep {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_sleep";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_s_waitcnt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_s_waitcnt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_sad_hi_u8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_sad_hi_u8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_sad_u16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_sad_u16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_sad_u8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_sad_u8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_sbfe {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_sdot2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_sdot2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_v2i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_sdot4 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_sdot4";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_sdot8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_sdot8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_set_inactive {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_sffbh {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_sin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_tbuffer_load {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_any_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  int RsrcArg = 0;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_tbuffer_store {	// SDPatternOperator Intrinsic AMDGPURsrcIntrinsic
  list<SDNodeProperty> Properties = [SDNPMemOperand];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_any_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  int RsrcArg = 1;
  bit IsImage = 0;
  string NAME = ?;
}
def int_amdgcn_trig_preop {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_ubfe {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_udot2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_udot2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_v2i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_udot4 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_udot4";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_udot8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_udot8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_unreachable {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_update_dpp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_wave_barrier {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_wave_barrier";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_workgroup_id_x {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_amdgcn_workgroup_id_x";
  string NAME = ?;
}
def int_amdgcn_workgroup_id_y {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_amdgcn_workgroup_id_y";
  string NAME = ?;
}
def int_amdgcn_workgroup_id_z {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_amdgcn_workgroup_id_z";
  string NAME = ?;
}
def int_amdgcn_workitem_id_x {	// SDPatternOperator Intrinsic AMDGPUReadPreloadRegisterIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_workitem_id_y {	// SDPatternOperator Intrinsic AMDGPUReadPreloadRegisterIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_workitem_id_z {	// SDPatternOperator Intrinsic AMDGPUReadPreloadRegisterIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_wqm {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_any_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_wqm_vote {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_writelane {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_amdgcn_writelane";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_amdgcn_wwm {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "amdgcn";
  list<LLVMType> RetTypes = [llvm_any_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_annotation {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.annotation";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_cdp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_cdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_cdp2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_cdp2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_clrex {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_crc32b {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_crc32cb {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_crc32ch {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_crc32cw {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_crc32h {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_crc32w {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_dbg {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_dmb {	// GCCBuiltin MSBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_dmb";
  string MSBuiltinName = "__dmb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_dsb {	// GCCBuiltin MSBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_dsb";
  string MSBuiltinName = "__dsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_get_fpscr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_get_fpscr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_hint {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_isb {	// GCCBuiltin MSBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_isb";
  string MSBuiltinName = "__isb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ldaex {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ldaexd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ldc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_ldc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ldc2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_ldc2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ldc2l {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_ldc2l";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ldcl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_ldcl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ldrex {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ldrexd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_mcr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_mcr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_mcr2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_mcr2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_mcrr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_mcrr2 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_mrc {	// GCCBuiltin MSBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_mrc";
  string MSBuiltinName = "_MoveFromCoprocessor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_mrc2 {	// GCCBuiltin MSBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_mrc2";
  string MSBuiltinName = "_MoveFromCoprocessor2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_mrrc {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_mrrc2 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_aesd {	// SDPatternOperator Intrinsic AES_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_aese {	// SDPatternOperator Intrinsic AES_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_aesimc {	// SDPatternOperator Intrinsic AES_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_aesmc {	// SDPatternOperator Intrinsic AES_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sdot {	// SDPatternOperator Intrinsic Neon_Dot_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha1c {	// SDPatternOperator Intrinsic SHA_3Arg_i32_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha1h {	// SDPatternOperator Intrinsic SHA_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha1m {	// SDPatternOperator Intrinsic SHA_3Arg_i32_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha1p {	// SDPatternOperator Intrinsic SHA_3Arg_i32_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha1su0 {	// SDPatternOperator Intrinsic SHA_3Arg_v4i32_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha1su1 {	// SDPatternOperator Intrinsic SHA_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha256h {	// SDPatternOperator Intrinsic SHA_3Arg_v4i32_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha256h2 {	// SDPatternOperator Intrinsic SHA_3Arg_v4i32_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha256su0 {	// SDPatternOperator Intrinsic SHA_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_sha256su1 {	// SDPatternOperator Intrinsic SHA_3Arg_v4i32_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_udot {	// SDPatternOperator Intrinsic Neon_Dot_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vabds {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vabdu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vabs {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vacge {	// SDPatternOperator Intrinsic Neon_Compare_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vacgt {	// SDPatternOperator Intrinsic Neon_Compare_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_19];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vbsl {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcls {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtas {	// SDPatternOperator Intrinsic Neon_CvtFPtoInt_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtau {	// SDPatternOperator Intrinsic Neon_CvtFPtoInt_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtfp2fxs {	// SDPatternOperator Intrinsic Neon_CvtFPToFx_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtfp2fxu {	// SDPatternOperator Intrinsic Neon_CvtFPToFx_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtfp2hf {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtfxs2fp {	// SDPatternOperator Intrinsic Neon_CvtFxToFP_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtfxu2fp {	// SDPatternOperator Intrinsic Neon_CvtFxToFP_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyint_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvthf2fp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtms {	// SDPatternOperator Intrinsic Neon_CvtFPtoInt_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtmu {	// SDPatternOperator Intrinsic Neon_CvtFPtoInt_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtns {	// SDPatternOperator Intrinsic Neon_CvtFPtoInt_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtnu {	// SDPatternOperator Intrinsic Neon_CvtFPtoInt_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtps {	// SDPatternOperator Intrinsic Neon_CvtFPtoInt_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vcvtpu {	// SDPatternOperator Intrinsic Neon_CvtFPtoInt_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vhadds {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vhaddu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vhsubs {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vhsubu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vld1 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vld2 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vld2lane {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, anonymous_6, anonymous_6, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vld3 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vld3lane {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, anonymous_6, anonymous_6, anonymous_6, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vld4 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vld4lane {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty, anonymous_6, anonymous_6, anonymous_6];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, anonymous_6, anonymous_6, anonymous_6, anonymous_6, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vmaxnm {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vmaxs {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vmaxu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vminnm {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vmins {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vminu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vmullp {	// SDPatternOperator Intrinsic Neon_2Arg_Long_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vmulls {	// SDPatternOperator Intrinsic Neon_2Arg_Long_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vmullu {	// SDPatternOperator Intrinsic Neon_2Arg_Long_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vmulp {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vpadals {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vpadalu {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vpadd {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vpaddls {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vpaddlu {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vpmaxs {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vpmaxu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vpmins {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vpminu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqabs {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqadds {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqaddu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqdmulh {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqdmull {	// SDPatternOperator Intrinsic Neon_2Arg_Long_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_18, anonymous_18];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqmovns {	// SDPatternOperator Intrinsic Neon_1Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqmovnsu {	// SDPatternOperator Intrinsic Neon_1Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqmovnu {	// SDPatternOperator Intrinsic Neon_1Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqneg {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqrdmulh {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqrshiftns {	// SDPatternOperator Intrinsic Neon_2Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqrshiftnsu {	// SDPatternOperator Intrinsic Neon_2Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqrshiftnu {	// SDPatternOperator Intrinsic Neon_2Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqrshifts {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqrshiftu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqshiftns {	// SDPatternOperator Intrinsic Neon_2Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqshiftnsu {	// SDPatternOperator Intrinsic Neon_2Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqshiftnu {	// SDPatternOperator Intrinsic Neon_2Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqshifts {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqshiftsu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqshiftu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqsubs {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vqsubu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vraddhn {	// SDPatternOperator Intrinsic Neon_2Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrecpe {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrecps {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrhadds {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrhaddu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrinta {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrintm {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrintn {	// SDPatternOperator Intrinsic Neon_1FloatArg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrintp {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrintx {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrintz {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrshiftn {	// SDPatternOperator Intrinsic Neon_2Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrshifts {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrshiftu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrsqrte {	// SDPatternOperator Intrinsic Neon_1Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrsqrts {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vrsubhn {	// SDPatternOperator Intrinsic Neon_2Arg_Narrow_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_17, anonymous_17];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vshiftins {	// SDPatternOperator Intrinsic Neon_3Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vshifts {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vshiftu {	// SDPatternOperator Intrinsic Neon_2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vst1 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyvector_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vst2 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyvector_ty, anonymous_19, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vst2lane {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyvector_ty, anonymous_19, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vst3 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyvector_ty, anonymous_19, anonymous_19, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vst3lane {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyvector_ty, anonymous_19, anonymous_19, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vst4 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyvector_ty, anonymous_19, anonymous_19, anonymous_19, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vst4lane {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyvector_ty, anonymous_19, anonymous_19, anonymous_19, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vtbl1 {	// SDPatternOperator Intrinsic Neon_Tbl2Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vtbl2 {	// SDPatternOperator Intrinsic Neon_Tbl3Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vtbl3 {	// SDPatternOperator Intrinsic Neon_Tbl4Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vtbl4 {	// SDPatternOperator Intrinsic Neon_Tbl5Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vtbx1 {	// SDPatternOperator Intrinsic Neon_Tbl3Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vtbx2 {	// SDPatternOperator Intrinsic Neon_Tbl4Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vtbx3 {	// SDPatternOperator Intrinsic Neon_Tbl5Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_neon_vtbx4 {	// SDPatternOperator Intrinsic Neon_Tbl6Arg_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_v8i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_qadd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_qadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_qadd16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_qadd16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_qadd8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_qadd8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_qasx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_qasx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_qsax {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_qsax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_qsub {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_qsub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_qsub16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_qsub16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_qsub8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_qsub8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_sadd16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_sadd16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_sadd8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_sadd8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_sasx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_sasx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_sel {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_sel";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_set_fpscr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_set_fpscr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_shadd16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_shadd16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_shadd8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_shadd8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_shasx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_shasx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_shsax {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_shsax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_shsub16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_shsub16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_shsub8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_shsub8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlabb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlabb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlabt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlabt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlad {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlad";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smladx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smladx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlald {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlald";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlaldx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlaldx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlatb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlatb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlatt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlatt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlawb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlawb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlawt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlawt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlsd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlsdx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlsdx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlsld {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlsld";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smlsldx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smlsldx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smuad {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smuad";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smuadx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smuadx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smulbb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smulbb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smulbt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smulbt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smultb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smultb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smultt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smultt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smulwb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smulwb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smulwt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smulwt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smusd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smusd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_smusdx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_smusdx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_space {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ssat {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_ssat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ssat16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_ssat16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ssax {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_ssax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ssub16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_ssub16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_ssub8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_ssub8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_stc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_stc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_stc2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_stc2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_stc2l {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_stc2l";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_stcl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_stcl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_stlex {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_stlexd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_strex {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_strexd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_sxtab16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_sxtab16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_sxtb16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_sxtb16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uadd16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uadd16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uadd8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uadd8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uasx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uasx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uhadd16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uhadd16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uhadd8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uhadd8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uhasx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uhasx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uhsax {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uhsax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uhsub16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uhsub16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uhsub8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uhsub8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_undefined {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uqadd16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uqadd16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uqadd8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uqadd8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uqasx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uqasx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uqsax {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uqsax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uqsub16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uqsub16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uqsub8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uqsub8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_usad8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_usad8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_usada8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_usada8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_usat {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_usat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_usat16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_usat16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_usax {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_usax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_usub16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_usub16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_usub8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_usub8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uxtab16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uxtab16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_uxtb16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_arm_uxtb16";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_vcvtr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_arm_vcvtru {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "arm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_assume {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_bitreverse {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_bpf_load_byte {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_bpf_load_byte";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "bpf";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_bpf_load_half {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_bpf_load_half";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "bpf";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_bpf_load_word {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_bpf_load_word";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "bpf";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_bpf_pseudo {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_bpf_pseudo";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "bpf";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_bswap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_canonicalize {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ceil {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_clear_cache {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.clear_cache";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_codeview_annotation {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.codeview.annotation";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrNoDuplicate];
  bit isTarget = 0;
  string NAME = ?;
}
def int_convert_from_fp16 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_convert_to_fp16 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_copysign {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_alloc {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_token_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_begin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_token_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_10];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_destroy {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_done {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_end {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_frame {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_free {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_token_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_5, anonymous_0];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_id {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_token_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, IntrReadMem, anonymous_8, anonymous_9, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_noop {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_param {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, anonymous_11, anonymous_8];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_promise {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_resume {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_save {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_token_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_size {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_subfn_addr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_coro_suspend {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_token_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_cos {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ctlz {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ctpop {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_cttz {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_dbg_addr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_metadata_ty, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_dbg_declare {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_metadata_ty, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_dbg_label {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_dbg_value {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_metadata_ty, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_debugtrap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_debugtrap";
  string NAME = ?;
}
def int_donothing {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_dwarf_cfa {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_exceptioncode {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_token_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_exceptionpointer {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_token_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_return_i32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_return_i64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_sjlj_callsite {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_sjlj_functioncontext {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_sjlj_longjmp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoReturn];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_sjlj_lsda {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_sjlj_setjmp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_sjlj_setup_dispatch {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_typeid_for {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_eh_unwind_init {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_unwind_init";
  string NAME = ?;
}
def int_exp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_exp2 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_expect {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_cos {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_exp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_exp2 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_fadd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_fdiv {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_fma {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_fmul {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_frem {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_fsub {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_log {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_log10 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_log2 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_nearbyint {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_pow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_powi {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_i32_ty, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_rint {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_sin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_constrained_sqrt {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_metadata_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_deoptimize {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_any_ty];
  list<LLVMType> ParamTypes = [llvm_vararg_ty];
  list<IntrinsicProperty> IntrProperties = [Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_gc_relocate {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_any_ty];
  list<LLVMType> ParamTypes = [llvm_token_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_gc_result {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_any_ty];
  list<LLVMType> ParamTypes = [llvm_token_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_gc_statepoint {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_token_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_vararg_ty];
  list<IntrinsicProperty> IntrProperties = [Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_guard {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i1_ty, llvm_vararg_ty];
  list<IntrinsicProperty> IntrProperties = [Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_patchpoint_i64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_vararg_ty];
  list<IntrinsicProperty> IntrProperties = [Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_patchpoint_void {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_vararg_ty];
  list<IntrinsicProperty> IntrProperties = [Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_stackmap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_vararg_ty];
  list<IntrinsicProperty> IntrProperties = [Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_add {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_and {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_fadd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_fmax {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_fmin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_fmul {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_mul {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_or {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_smax {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_smin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_umax {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_umin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_experimental_vector_reduce_xor {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_fabs {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_floor {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_flt_rounds {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_flt_rounds";
  string NAME = ?;
}
def int_fma {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_fmuladd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_frameaddress {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_gcread {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptrptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_gcroot {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptrptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_gcwrite {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_0, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_get_dynamic_area_offset {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_abs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_abs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_absp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_absp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_abssat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_abssat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_add {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_add";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_h16_hh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_h16_hh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_h16_hl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_h16_hl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_h16_lh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_h16_lh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_h16_ll {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_h16_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_h16_sat_hh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_h16_sat_hh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_h16_sat_hl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_h16_sat_hl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_h16_sat_lh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_h16_sat_lh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_h16_sat_ll {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_h16_sat_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_l16_hl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_l16_hl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_l16_ll {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_l16_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_l16_sat_hl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_l16_sat_hl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addh_l16_sat_ll {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addh_l16_sat_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addpsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addpsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_addsp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sidi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_addsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_andir {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_andir";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_andp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_andp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_aslh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_aslh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_asrh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_asrh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_combine_hh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_combine_hh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_combine_hl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_combine_hl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_combine_lh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_combine_lh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_combine_ll {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_combine_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_combineii {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_combineii";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_combinew {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_combinew";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_max {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_max";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_maxp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_maxp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_maxu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_maxu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_maxup {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_maxup";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_min {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_min";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_minp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_minp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_minu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_minu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_minup {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_minup";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_neg {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_neg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_negp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_negp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_negsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_negsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_not {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_not";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_notp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_notp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_orir {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_orir";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_orp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_orp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_roundsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_roundsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_satb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_satb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_sath {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_sath";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_satub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_satub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_satuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_satuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_sub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_sub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_h16_hh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_h16_hh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_h16_hl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_h16_hl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_h16_lh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_h16_lh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_h16_ll {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_h16_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_h16_sat_hh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_h16_sat_hh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_h16_sat_hl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_h16_sat_hl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_h16_sat_lh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_h16_sat_lh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_h16_sat_ll {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_h16_sat_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_l16_hl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_l16_hl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_l16_ll {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_l16_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_l16_sat_hl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_l16_sat_hl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subh_l16_sat_ll {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subh_l16_sat_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_subsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_subsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_svaddh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_svaddh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_svaddhs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_svaddhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_svadduhs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_svadduhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_svavgh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_svavgh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_svavghs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_svavghs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_svnavgh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_svnavgh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_svsubh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_svsubh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_svsubhs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_svsubhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_svsubuhs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_svsubuhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_swiz {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_swiz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_sxtb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_sxtb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_sxth {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_sxth";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_sxtw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_sxtw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_tfr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_tfr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_tfrih {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_tfrih";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_tfril {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_tfril";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_tfrp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_tfrp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_tfrpi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_tfrpi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_tfrsi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_tfrsi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vabsh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vabsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vabshsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vabshsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vabsw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vabsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vabswsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vabswsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vaddb_map {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vaddb_map";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vaddh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vaddh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vaddhs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vaddhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vaddub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vaddub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vaddubs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vaddubs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vadduhs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vadduhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vaddw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vaddw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vaddws {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vaddws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavgh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavgh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavghcr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavghcr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavghr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavghr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavgub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavgub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavgubr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavgubr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavguh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavguh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavguhr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavguhr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavguw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavguw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavguwr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavguwr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavgw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavgw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavgwcr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavgwcr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vavgwr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vavgwr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vcmpbeq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vcmpbeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vcmpbgtu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vcmpbgtu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vcmpheq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vcmpheq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vcmphgt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vcmphgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vcmphgtu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vcmphgtu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vcmpweq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vcmpweq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vcmpwgt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vcmpwgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vcmpwgtu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vcmpwgtu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vconj {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vconj";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vmaxb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vmaxb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vmaxh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vmaxh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vmaxub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vmaxub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vmaxuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vmaxuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vmaxuw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vmaxuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vmaxw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vmaxw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vminb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vminb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vminh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vminh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vminub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vminub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vminuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vminuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vminuw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vminuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vminw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vminw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vnavgh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vnavgh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vnavghcr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vnavghcr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vnavghr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vnavghr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vnavgw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vnavgw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vnavgwcr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vnavgwcr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vnavgwr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vnavgwr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vraddub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vraddub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vraddub_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vraddub_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vrsadub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vrsadub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vrsadub_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vrsadub_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vsubb_map {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vsubb_map";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vsubh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vsubh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vsubhs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vsubhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vsubub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vsubub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vsububs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vsububs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vsubuhs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vsubuhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vsubw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vsubw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_vsubws {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_vsubws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_xorp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_xorp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_zxtb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_zxtb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A2_zxth {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A2_zxth";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_andn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_andn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_andnp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_andnp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_bitsplit {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_bitsplit";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_bitspliti {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_bitspliti";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_boundscheck {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sidi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_boundscheck";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmpbeq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmpbeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmpbeqi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmpbeqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmpbgt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmpbgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmpbgti {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmpbgti";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmpbgtu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmpbgtu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmpbgtui {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmpbgtui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmpheq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmpheq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmpheqi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmpheqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmphgt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmphgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmphgti {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmphgti";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmphgtu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmphgtu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cmphgtui {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cmphgtui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_combineir {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_combineir";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_combineri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_combineri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cround_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cround_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_cround_rr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_cround_rr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_modwrapu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_modwrapu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_orn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_orn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_ornp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_ornp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_rcmpeq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_rcmpeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_rcmpeqi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_rcmpeqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_rcmpneq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_rcmpneq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_rcmpneqi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_rcmpneqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_round_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_round_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_round_ri_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_round_ri_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_round_rr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_round_rr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_round_rr_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_round_rr_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_tlbmatch {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_tlbmatch";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmpbeq_any {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmpbeq_any";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmpbeqi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmpbeqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmpbgt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmpbgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmpbgti {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmpbgti";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmpbgtui {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmpbgtui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmpheqi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmpheqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmphgti {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmphgti";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmphgtui {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmphgtui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmpweqi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmpweqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmpwgti {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmpwgti";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vcmpwgtui {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vcmpwgtui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vrmaxh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vrmaxh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vrmaxuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vrmaxuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vrmaxuw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vrmaxuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vrmaxw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vrmaxw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vrminh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vrminh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vrminuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vrminuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vrminuw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vrminuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A4_vrminw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A4_vrminw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A5_vaddhubs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A5_vaddhubs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A6_vcmpbeq_notany {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_iLLiLLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A6_vcmpbeq_notany";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_A6_vcmpbeq_notany_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_iLLiLLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_A6_vcmpbeq_notany_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_all8 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_all8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_andn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_andn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_any8 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_any8";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_bitsclr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_bitsclr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_bitsclri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_bitsclri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_bitsset {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_bitsset";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpeq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpeqi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpeqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpeqp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpeqp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpgei {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpgei";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpgeui {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpgeui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpgt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpgti {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpgti";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpgtp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpgtp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpgtu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpgtu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpgtui {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpgtui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpgtup {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpgtup";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmplt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmplt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_cmpltu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_cmpltu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_mask {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_qi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_mux {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_mux";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_muxii {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_muxii";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_muxir {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_muxir";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_muxri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_muxri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_not {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_not";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_orn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_orn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_pxfer_map {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_pxfer_map";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_tfrpr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_tfrpr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_tfrrp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_tfrrp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_vitpack {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qiqi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_vitpack";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_vmux {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_qididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_vmux";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C2_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C2_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_and_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_and_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_and_andn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_and_andn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_and_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_and_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_and_orn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_and_orn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_cmplte {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_cmplte";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_cmpltei {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_cmpltei";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_cmplteu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_cmplteu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_cmplteui {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_cmplteui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_cmpneq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_cmpneq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_cmpneqi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_cmpneqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_fastcorner9 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qiqi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_fastcorner9";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_fastcorner9_not {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_qiqi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_fastcorner9_not";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_nbitsclr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_nbitsclr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_nbitsclri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_nbitsclri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_nbitsset {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_nbitsset";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_or_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_or_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_or_andn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_or_andn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_or_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_or_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_C4_or_orn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_C4_or_orn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_d2df {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_df_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_d2df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_d2sf {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_d2sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_df2d {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_df_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_df2d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_df2d_chop {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_df_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_df2d_chop";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_df2sf {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_df_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_df2sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_df2ud {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_df_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_df2ud";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_df2ud_chop {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_df_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_df2ud_chop";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_df2uw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_df_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_df2uw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_df2uw_chop {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_df_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_df2uw_chop";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_df2w {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_df_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_df2w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_df2w_chop {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_df_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_df2w_chop";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_sf2d {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_sf2d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_sf2d_chop {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_sf2d_chop";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_sf2df {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_df_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_sf2df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_sf2ud {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_sf2ud";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_sf2ud_chop {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_sf2ud_chop";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_sf2uw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_sf2uw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_sf2uw_chop {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_sf2uw_chop";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_sf2w {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_sf2w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_sf2w_chop {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_sf2w_chop";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_ud2df {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_df_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_ud2df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_ud2sf {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_ud2sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_uw2df {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_df_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_uw2df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_uw2sf {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_uw2sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_w2df {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_df_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_w2df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_conv_w2sf {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_conv_w2sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_dfclass {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_dfsi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_dfclass";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_dfcmpeq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_dfdf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_dfcmpeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_dfcmpge {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_dfdf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_dfcmpge";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_dfcmpgt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_dfdf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_dfcmpgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_dfcmpuo {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_dfdf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_dfcmpuo";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_dfimm_n {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_df_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_dfimm_n";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_dfimm_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_df_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_dfimm_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfadd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfclass {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sfsi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfclass";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfcmpeq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfcmpeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfcmpge {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfcmpge";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfcmpgt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfcmpgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfcmpuo {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfcmpuo";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sffixupd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sffixupd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sffixupn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sffixupn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sffixupr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sffixupr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sffma {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sffma";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sffma_lib {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sffma_lib";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sffma_sc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsfsfqi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sffma_sc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sffms {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sffms";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sffms_lib {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sffms_lib";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfimm_n {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfimm_n";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfimm_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfimm_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfmax {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfmax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfmin {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfmin";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfmpy {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfmpy";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_F2_sfsub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_sf_sfsf_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_F2_sfsub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Throws];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrb_pbr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic Hexagon_custom_brev_ld_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrb_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrb_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrd_pbr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic Hexagon_custom_brev_ld_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrd_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrd_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrh_pbr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic Hexagon_custom_brev_ld_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrh_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrh_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadri_pbr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic Hexagon_custom_brev_ld_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadri_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadri_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrub_pbr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic Hexagon_custom_brev_ld_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrub_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadrub_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadruh_pbr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic Hexagon_custom_brev_ld_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadruh_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadruh_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L2_loadw_locked {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_L2_loadw_locked";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_L4_loadd_locked {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_L4_loadd_locked";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_acci {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_acci";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_accii {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_accii";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmaci_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmaci_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmacr_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmacr_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmacs_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmacs_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmacs_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmacs_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmacsc_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmacsc_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmacsc_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmacsc_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpyi_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpyi_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpyr_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpyr_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpyrs_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpyrs_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpyrs_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpyrs_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpyrsc_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpyrsc_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpyrsc_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpyrsc_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpys_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpys_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpys_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpys_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpysc_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpysc_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cmpysc_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cmpysc_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cnacs_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cnacs_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cnacs_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cnacs_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cnacsc_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cnacsc_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_cnacsc_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_cnacsc_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_dpmpyss_acc_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_dpmpyss_acc_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_dpmpyss_nac_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_dpmpyss_nac_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_dpmpyss_rnd_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_dpmpyss_rnd_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_dpmpyss_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_dpmpyss_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_dpmpyuu_acc_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_dpmpyuu_acc_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_dpmpyuu_nac_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_dpmpyuu_nac_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_dpmpyuu_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_dpmpyuu_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_hmmpyh_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_hmmpyh_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_hmmpyh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_hmmpyh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_hmmpyl_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_hmmpyl_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_hmmpyl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_hmmpyl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_maci {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_maci";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_macsin {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_macsin";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_macsip {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_macsip";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmachs_rs0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmachs_rs0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmachs_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmachs_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmachs_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmachs_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmachs_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmachs_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmacls_rs0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmacls_rs0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmacls_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmacls_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmacls_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmacls_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmacls_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmacls_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmacuhs_rs0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmacuhs_rs0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmacuhs_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmacuhs_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmacuhs_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmacuhs_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmacuhs_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmacuhs_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmaculs_rs0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmaculs_rs0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmaculs_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmaculs_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmaculs_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmaculs_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmaculs_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmaculs_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyh_rs0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyh_rs0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyh_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyh_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyl_rs0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyl_rs0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyl_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyl_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyuh_rs0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyuh_rs0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyuh_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyuh_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyuh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyuh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyuh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyuh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyul_rs0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyul_rs0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyul_rs1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyul_rs1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyul_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyul_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mmpyul_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mmpyul_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_sat_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_sat_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_sat_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_sat_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_sat_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_sat_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_sat_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_acc_sat_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_sat_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_sat_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_sat_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_sat_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_sat_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_sat_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_sat_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_nac_sat_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_rnd_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_rnd_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_rnd_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_rnd_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_rnd_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_rnd_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_rnd_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_rnd_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_rnd_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_rnd_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_rnd_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_rnd_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_rnd_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_rnd_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_rnd_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_rnd_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_rnd_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_rnd_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_rnd_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_rnd_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_rnd_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_rnd_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_rnd_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_sat_rnd_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_up {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_up";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_up_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_up_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpy_up_s1_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpy_up_s1_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_acc_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_acc_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_acc_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_acc_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_acc_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_acc_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_acc_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_acc_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_acc_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_acc_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_acc_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_acc_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_acc_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_acc_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_acc_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_acc_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_nac_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_nac_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_nac_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_nac_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_nac_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_nac_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_nac_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_nac_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_nac_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_nac_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_nac_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_nac_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_nac_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_nac_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_nac_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_nac_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_rnd_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_rnd_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_rnd_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_rnd_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_rnd_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_rnd_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_rnd_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_rnd_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_rnd_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_rnd_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_rnd_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_rnd_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_rnd_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_rnd_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyd_rnd_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyd_rnd_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpysmi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpysmi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpysu_up {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpysu_up";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_acc_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_acc_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_acc_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_acc_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_acc_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_acc_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_acc_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_acc_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_acc_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_acc_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_acc_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_acc_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_acc_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_acc_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_acc_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_acc_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_nac_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_nac_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_nac_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_nac_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_nac_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_nac_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_nac_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_nac_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_nac_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_nac_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_nac_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_nac_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_nac_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_nac_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_nac_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_nac_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyu_up {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyu_up";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_acc_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_acc_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_acc_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_acc_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_acc_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_acc_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_acc_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_acc_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_acc_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_acc_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_acc_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_acc_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_acc_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_acc_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_acc_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_acc_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_nac_hh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_nac_hh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_nac_hh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_nac_hh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_nac_hl_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_nac_hl_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_nac_hl_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_nac_hl_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_nac_lh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_nac_lh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_nac_lh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_nac_lh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_nac_ll_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_nac_ll_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyud_nac_ll_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyud_nac_ll_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_mpyui {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_mpyui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_nacci {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_nacci";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_naccii {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_naccii";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_subacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_subacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vabsdiffh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vabsdiffh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vabsdiffw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vabsdiffw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vcmac_s0_sat_i {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vcmac_s0_sat_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vcmac_s0_sat_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vcmac_s0_sat_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vcmpy_s0_sat_i {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vcmpy_s0_sat_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vcmpy_s0_sat_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vcmpy_s0_sat_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vcmpy_s1_sat_i {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vcmpy_s1_sat_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vcmpy_s1_sat_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vcmpy_s1_sat_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vdmacs_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vdmacs_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vdmacs_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vdmacs_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vdmpyrs_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vdmpyrs_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vdmpyrs_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vdmpyrs_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vdmpys_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vdmpys_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vdmpys_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vdmpys_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmac2 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmac2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmac2es {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmac2es";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmac2es_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmac2es_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmac2es_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmac2es_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmac2s_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmac2s_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmac2s_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmac2s_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmac2su_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmac2su_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmac2su_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmac2su_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmpy2es_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmpy2es_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmpy2es_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmpy2es_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmpy2s_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmpy2s_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmpy2s_s0pack {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmpy2s_s0pack";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmpy2s_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmpy2s_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmpy2s_s1pack {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmpy2s_s1pack";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmpy2su_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmpy2su_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vmpy2su_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vmpy2su_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vraddh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vraddh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vradduh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vradduh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmaci_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmaci_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmaci_s0c {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmaci_s0c";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmacr_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmacr_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmacr_s0c {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmacr_s0c";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmpyi_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmpyi_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmpyi_s0c {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmpyi_s0c";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmpyr_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmpyr_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmpyr_s0c {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmpyr_s0c";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmpys_acc_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmpys_acc_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmpys_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmpys_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrcmpys_s1rp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrcmpys_s1rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrmac_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrmac_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_vrmpy_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_vrmpy_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M2_xor_xacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M2_xor_xacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_and_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_and_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_and_andn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_and_andn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_and_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_and_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_and_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_and_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_cmpyi_wh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_cmpyi_wh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_cmpyi_whc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_cmpyi_whc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_cmpyr_wh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_cmpyr_wh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_cmpyr_whc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_cmpyr_whc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_mac_up_s1_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_mac_up_s1_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_mpyri_addi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_mpyri_addi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_mpyri_addr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_mpyri_addr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_mpyri_addr_u2 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_mpyri_addr_u2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_mpyrr_addi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_mpyrr_addi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_mpyrr_addr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_mpyrr_addr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_nac_up_s1_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_nac_up_s1_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_or_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_or_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_or_andn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_or_andn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_or_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_or_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_or_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_or_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_pmpyw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_pmpyw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_pmpyw_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_pmpyw_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vpmpyh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vpmpyh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vpmpyh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vpmpyh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vrmpyeh_acc_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vrmpyeh_acc_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vrmpyeh_acc_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vrmpyeh_acc_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vrmpyeh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vrmpyeh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vrmpyeh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vrmpyeh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vrmpyoh_acc_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vrmpyoh_acc_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vrmpyoh_acc_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vrmpyoh_acc_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vrmpyoh_s0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vrmpyoh_s0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_vrmpyoh_s1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_vrmpyoh_s1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_xor_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_xor_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_xor_andn {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_xor_andn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_xor_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_xor_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M4_xor_xacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M4_xor_xacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vdmacbsu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vdmacbsu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vdmpybsu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vdmpybsu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vmacbsu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vmacbsu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vmacbuu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vmacbuu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vmpybsu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vmpybsu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vmpybuu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vmpybuu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vrmacbsu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vrmacbsu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vrmacbuu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vrmacbuu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vrmpybsu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vrmpybsu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M5_vrmpybuu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M5_vrmpybuu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M6_vabsdiffb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M6_vabsdiffb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_M6_vabsdiffub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_M6_vabsdiffub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_addasl_rrri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_addasl_rrri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_p_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_p_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_p_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_p_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_p_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_p_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_p_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_p_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_p_xacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_p_xacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_r_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_r_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_r_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_r_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_r_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_r_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_r_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_r_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_r_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_r_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_r_xacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_r_xacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_vh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_vh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_i_vw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_i_vw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_p_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_p_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_p_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_p_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_p_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_p_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_p_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_p_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_p_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_p_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_r_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_r_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_r_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_r_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_r_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_r_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_r_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_r_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_r_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_r_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_vh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_vh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asl_r_vw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asl_r_vw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_p_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_p_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_p_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_p_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_p_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_p_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_p_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_p_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_p_rnd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_p_rnd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_p_rnd_goodsyntax {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_r_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_r_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_r_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_r_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_r_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_r_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_r_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_r_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_r_rnd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_r_rnd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_r_rnd_goodsyntax {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_svw_trun {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_svw_trun";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_vh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_vh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_i_vw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_i_vw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_p_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_p_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_p_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_p_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_p_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_p_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_p_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_p_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_p_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_p_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_r_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_r_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_r_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_r_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_r_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_r_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_r_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_r_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_r_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_r_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_svw_trun {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_svw_trun";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_vh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_vh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_asr_r_vw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_asr_r_vw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_brev {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_brev";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_brevp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_brevp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_cabacencbin {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_cabacencbin";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_cl0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_cl0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_cl0p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_cl0p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_cl1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_cl1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_cl1p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_cl1p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_clb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_clb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_clbnorm {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_clbnorm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_clbp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_clbp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_clrbit_i {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_clrbit_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_clrbit_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_clrbit_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_ct0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_ct0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_ct0p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_ct0p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_ct1 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_ct1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_ct1p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_ct1p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_deinterleave {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_deinterleave";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_extractu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_extractu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_extractu_rp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sidi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_extractu_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_extractup {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_extractup";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_extractup_rp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_extractup_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_insert {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_insert";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_insert_rp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisidi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_insert_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_insertp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_insertp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_insertp_rp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_dididi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_insertp_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_interleave {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_interleave";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lfsp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lfsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_p_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_p_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_p_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_p_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_p_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_p_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_p_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_p_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_p_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_p_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_r_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_r_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_r_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_r_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_r_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_r_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_r_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_r_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_vh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_vh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsl_r_vw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsl_r_vw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_p_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_p_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_p_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_p_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_p_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_p_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_p_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_p_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_p_xacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_p_xacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_r_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_r_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_r_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_r_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_r_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_r_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_r_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_r_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_r_xacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_r_xacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_vh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_vh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_i_vw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_i_vw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_p_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_p_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_p_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_p_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_p_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_p_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_p_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_p_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_p_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_p_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_r_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_r_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_r_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_r_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_r_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_r_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_r_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_r_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_vh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_vh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_lsr_r_vw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_lsr_r_vw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_packhl {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_packhl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_parityp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_parityp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_setbit_i {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_setbit_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_setbit_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_setbit_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_shuffeb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_shuffeb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_shuffeh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_shuffeh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_shuffob {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_shuffob";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_shuffoh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_shuffoh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerb_pbr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memsisi_Intrinsic
  string GCCBuiltinName = "__builtin_brev_stb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerb_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerb_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerd_pbr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memdisi_Intrinsic
  string GCCBuiltinName = "__builtin_brev_std";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerd_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerd_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerf_pbr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memsisi_Intrinsic
  string GCCBuiltinName = "__builtin_brev_sthhi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerf_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerf_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerh_pbr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memsisi_Intrinsic
  string GCCBuiltinName = "__builtin_brev_sth";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerh_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storerh_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storeri_pbr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memsisi_Intrinsic
  string GCCBuiltinName = "__builtin_brev_stw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storeri_pci {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_22];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storeri_pcr {	// SDPatternOperator Intrinsic Hexagon_NonGCC_Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_21];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_storew_locked {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_storew_locked";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_svsathb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_svsathb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_svsathub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_svsathub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_tableidxb_goodsyntax {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_tableidxb_goodsyntax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_tableidxd_goodsyntax {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_tableidxd_goodsyntax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_tableidxh_goodsyntax {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_tableidxh_goodsyntax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_tableidxw_goodsyntax {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_tableidxw_goodsyntax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_togglebit_i {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_togglebit_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_togglebit_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_togglebit_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_tstbit_i {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_tstbit_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_tstbit_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_tstbit_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_valignib {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_valignib";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_valignrb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didiqi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_valignrb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vcnegh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vcnegh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vcrotate {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vcrotate";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vrcnegh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vrcnegh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vrndpackwh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vrndpackwh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vrndpackwhs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vrndpackwhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsathb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsathb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsathb_nopack {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsathb_nopack";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsathub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsathub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsathub_nopack {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsathub_nopack";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsatwh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsatwh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsatwh_nopack {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsatwh_nopack";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsatwuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsatwuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsatwuh_nopack {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsatwuh_nopack";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsplatrb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsplatrb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsplatrh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsplatrh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vspliceib {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vspliceib";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsplicerb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didiqi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsplicerb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsxtbh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsxtbh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vsxthw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vsxthw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vtrunehb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vtrunehb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vtrunewh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vtrunewh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vtrunohb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vtrunohb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vtrunowh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vtrunowh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vzxtbh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vzxtbh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S2_vzxthw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_si_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S2_vzxthw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_addaddi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_addaddi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_addi_asl_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_addi_asl_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_addi_lsr_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_addi_lsr_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_andi_asl_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_andi_asl_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_andi_lsr_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_andi_lsr_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_clbaddi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_clbaddi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_clbpaddi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_clbpaddi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_clbpnorm {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_clbpnorm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_extract {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_extract";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_extract_rp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sidi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_extract_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_extractp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_extractp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_extractp_rp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_extractp_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_lsli {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_lsli";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_ntstbit_i {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_ntstbit_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_ntstbit_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_ntstbit_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_or_andi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_or_andi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_or_andix {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_or_andix";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_or_ori {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_or_ori";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_ori_asl_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_ori_asl_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_ori_lsr_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_ori_lsr_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_parity {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_parity";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_stored_locked {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_stored_locked";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_subaddi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_subaddi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_subi_asl_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_subi_asl_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_subi_lsr_ri {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_sisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_subi_lsr_ri";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_vrcrotate {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_vrcrotate";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_vrcrotate_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didisisi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_vrcrotate_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_vxaddsubh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_vxaddsubh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_vxaddsubhr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_vxaddsubhr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_vxaddsubw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_vxaddsubw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_vxsubaddh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_vxsubaddh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_vxsubaddhr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_vxsubaddhr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S4_vxsubaddw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_didi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S4_vxsubaddw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S5_asrhub_rnd_sat_goodsyntax {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S5_asrhub_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S5_asrhub_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S5_popcountp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_si_di_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S5_popcountp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S5_vasrhrnd_goodsyntax {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_di_disi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S5_vasrhrnd_goodsyntax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_p {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_p_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_p_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_p_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_p_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_p_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_p_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_p_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_p_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_p_xacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_p_xacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_r {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_iii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_r";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_r_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_iiii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_r_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_r_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_iiii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_r_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_r_nac {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_iiii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_r_nac";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_r_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_iiii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_r_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_rol_i_r_xacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_iiii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_rol_i_r_xacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_vsplatrbp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_vsplatrbp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_vtrunehb_ppp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_vtrunehb_ppp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_S6_vtrunohb_ppp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_LLiLLiLLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_S6_vtrunohb_ppp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_extractw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_iv512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_extractw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_extractw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_iv1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_extractw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_hi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v1024_Intrinsic_T
  string GCCBuiltinName = "__builtin_HEXAGON_V6_hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_hi_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v2048_Intrinsic_T
  string GCCBuiltinName = "__builtin_HEXAGON_V6_hi_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_lo {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v1024_Intrinsic_T
  string GCCBuiltinName = "__builtin_HEXAGON_V6_lo";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_lo_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v2048_Intrinsic_T
  string GCCBuiltinName = "__builtin_HEXAGON_V6_lo_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_lvsplatb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_lvsplatb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_lvsplatb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_lvsplatb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_lvsplath {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_lvsplath";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_lvsplath_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_lvsplath_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_lvsplatw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_lvsplatw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_lvsplatw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_lvsplatw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_and_n {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_and_n";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_and_n_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_and_n_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_not {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_not";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_not_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_not_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_or_n {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_or_n";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_or_n_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_or_n_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_scalar2 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_scalar2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_scalar2_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_scalar2_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_scalar2v2 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v64ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_scalar2v2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_scalar2v2_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v128ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_scalar2v2_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_pred_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_pred_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_shuffeqh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v64iv64iv64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_shuffeqh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_shuffeqh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v128iv128iv128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_shuffeqh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_shuffeqw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v64iv64iv64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_shuffeqw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_shuffeqw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v128iv128iv128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_shuffeqw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vS32b_nqpred_ai {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv64ivmemv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vS32b_nqpred_ai";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_ptr_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vS32b_nqpred_ai_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv128ivmemv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vS32b_nqpred_ai_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_ptr_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vS32b_nt_nqpred_ai {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv64ivmemv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_ptr_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vS32b_nt_nqpred_ai_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv128ivmemv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_ptr_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vS32b_nt_qpred_ai {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv64ivmemv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vS32b_nt_qpred_ai";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_ptr_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vS32b_nt_qpred_ai_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv128ivmemv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vS32b_nt_qpred_ai_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_ptr_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vS32b_qpred_ai {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv64ivmemv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vS32b_qpred_ai";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_ptr_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vS32b_qpred_ai_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv128ivmemv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vS32b_qpred_ai_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_ptr_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsb_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsb_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsb_sat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsb_sat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsdiffh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsdiffh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsdiffh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsdiffh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsdiffub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsdiffub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsdiffub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsdiffub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsdiffuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsdiffuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsdiffuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsdiffuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsdiffw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsdiffw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsdiffw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsdiffw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsh_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsh_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsh_sat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsh_sat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsw_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsw_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vabsw_sat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vabsw_sat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddb_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddb_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddb_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddb_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddbnq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddbnq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddbnq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddbnq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddbq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddbq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddbq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddbq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddbsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddbsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddbsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddbsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddbsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddbsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddbsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddbsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddcarry {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512v64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_v6_vaddcarry";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty, llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddcarry_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024v128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_v6_vaddcarry_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty, llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddclbh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddclbh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddclbh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddclbh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddclbw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddclbw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddclbw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddclbw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddh_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddh_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddh_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddh_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhnq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhnq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhnq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhnq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhw_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhw_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddhw_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddhw_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddubh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddubh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddubh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddubh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddubh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddubh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddubh_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddubh_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddubsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddubsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddubsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddubsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddubsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddubsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddubsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddubsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddububb_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddububb_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddububb_sat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddububb_sat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduhsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduhsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduhsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduhsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduhw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduhw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduhw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduhw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduhw_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduhw_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduhw_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduhw_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduwsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduwsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduwsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduwsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduwsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduwsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vadduwsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vadduwsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddw_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddw_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddw_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddw_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddwnq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddwnq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddwnq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddwnq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddwq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddwq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddwq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddwq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddwsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddwsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddwsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddwsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddwsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddwsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaddwsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaddwsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_valignb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_valignb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_valignb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_valignb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_valignbi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_valignbi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_valignbi_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_valignbi_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vand {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vand";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vand_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vand_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandnqrt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v64ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandnqrt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandnqrt_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v128ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandnqrt_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandnqrt_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v64ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandnqrt_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v512i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandnqrt_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v128ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandnqrt_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v1024i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandqrt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandqrt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandqrt_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandqrt_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandqrt_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v64ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandqrt_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v512i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandqrt_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v128ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandqrt_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v1024i1_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandvnqv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v64iv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandvnqv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandvnqv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v128iv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandvnqv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandvqv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v64iv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandvqv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandvqv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v128iv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandvqv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandvrt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandvrt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandvrt_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandvrt_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandvrt_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandvrt_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vandvrt_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vandvrt_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslh_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslh_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslhv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslhv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslhv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslhv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslw_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslw_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslw_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslw_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslwv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslwv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vaslwv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vaslwv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrh_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrh_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhbrndsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhbrndsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhbrndsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhbrndsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhbsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhbsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhbsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhbsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhubrndsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhubrndsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhubrndsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhubrndsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhubsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhubsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhubsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhubsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrhv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrhv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasruhubrndsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasruhubrndsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasruhubrndsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasruhubrndsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasruhubsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasruhubsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasruhubsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasruhubsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasruwuhrndsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasruwuhrndsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasruwuhrndsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasruwuhrndsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasruwuhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasruwuhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasruwuhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasruwuhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrw_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrw_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrw_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrw_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwhrndsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwhrndsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwhrndsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwhrndsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwuhrndsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwuhrndsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwuhrndsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwuhrndsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwuhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwuhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwuhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwuhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vasrwv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vasrwv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vassign {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vassign";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vassign_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vassign_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vassignp {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic_T
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vassignp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vassignp_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048_Intrinsic_T
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vassignp_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgbrnd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgbrnd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgbrnd_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgbrnd_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavghrnd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavghrnd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavghrnd_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavghrnd_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgubrnd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgubrnd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgubrnd_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgubrnd_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavguh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavguh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavguh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavguh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavguhrnd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavguhrnd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavguhrnd_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavguhrnd_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavguw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavguw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavguw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavguw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavguwrnd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavguwrnd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavguwrnd_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavguwrnd_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgwrnd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgwrnd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vavgwrnd_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vavgwrnd_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vcl0h {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vcl0h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vcl0h_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vcl0h_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vcl0w {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vcl0w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vcl0w_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vcl0w_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vcombine {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vcombine";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vcombine_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vcombine_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vd0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vd0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vd0_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vd0_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdd0 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdd0";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdd0_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdd0_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdealb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdealb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdealb4w {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdealb4w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdealb4w_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdealb4w_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdealb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdealb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdealh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdealh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdealh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdealh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdealvdd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdealvdd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdealvdd_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdealvdd_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdelta {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdelta";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdelta_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdelta_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpybus {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpybus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpybus_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpybus_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpybus_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpybus_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpybus_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpybus_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpybus_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpybus_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpybus_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpybus_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpybus_dv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpybus_dv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpybus_dv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpybus_dv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhb_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhb_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhb_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhb_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhb_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhb_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhb_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhb_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhb_dv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhb_dv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhb_dv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhb_dv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhisat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhisat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhisat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhisat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhisat_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhisat_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhisat_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhisat_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsat_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsat_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsat_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsat_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsuisat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsuisat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsuisat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsuisat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsuisat_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsuisat_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsuisat_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsuisat_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsusat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsusat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsusat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsusat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsusat_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsusat_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhsusat_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhsusat_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhvsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhvsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhvsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhvsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhvsat_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhvsat_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdmpyhvsat_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdmpyhvsat_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdsaduh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdsaduh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdsaduh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdsaduh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdsaduh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdsaduh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vdsaduh_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vdsaduh_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqb_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqb_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqb_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqb_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqb_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqb_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqb_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqb_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqb_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqb_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqb_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqb_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqh_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqh_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqh_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqh_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqh_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqh_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqh_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqh_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqh_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqh_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqh_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqh_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqw_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqw_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqw_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqw_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqw_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqw_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqw_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqw_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqw_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqw_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_veqw_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_veqw_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemiiv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemiiv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermhq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemv64iiiv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermhq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermhq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemv128iiiv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermhq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermhw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemiiv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermhw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermhw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemiiv2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermhw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermhwq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemv64iiiv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermhwq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermhwq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemv128iiiv2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermhwq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemiiv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemiiv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermwq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemv64iiiv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermwq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgathermwq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vvmemv128iiiv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgathermwq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtb_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtb_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtb_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtb_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtb_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtb_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtb_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtb_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtb_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtb_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtb_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtb_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgth {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgth";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgth_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgth_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgth_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgth_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgth_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgth_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgth_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgth_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgth_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgth_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgth_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgth_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgth_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgth_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtub_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtub_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtub_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtub_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtub_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtub_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtub_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtub_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtub_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtub_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtub_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtub_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuh_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuh_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuh_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuh_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuh_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuh_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuh_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuh_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuh_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuh_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuh_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuh_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuw_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuw_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuw_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuw_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuw_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuw_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuw_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuw_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuw_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuw_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtuw_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtuw_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtw_and {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtw_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtw_and_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtw_and_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtw_or {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtw_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtw_or_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtw_or_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtw_xor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v64iv64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtw_xor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vgtw_xor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v128iv128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vgtw_xor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vinsertwr {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vinsertwr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vinsertwr_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vinsertwr_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlalignb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlalignb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlalignb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlalignb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlalignbi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlalignbi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlalignbi_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlalignbi_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrhv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrhv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrhv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrhv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrwv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrwv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlsrwv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlsrwv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlut4 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlut4";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlut4_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlut4_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvb_nm {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvb_nm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvb_nm_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvb_nm_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvb_oracc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvb_oracc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvb_oracc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvb_oracc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvb_oracci {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvb_oracci";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvb_oracci_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvb_oracci_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvbi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvbi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvvbi_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvvbi_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwh_nm {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwh_nm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwh_nm_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwh_nm_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwh_oracc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwh_oracc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwh_oracc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwh_oracc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwh_oracci {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwh_oracci";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwh_oracci_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwh_oracci_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwhi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwhi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vlutvwhi_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vlutvwhi_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaskedstorenq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv64ivmemv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaskedstorenq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_ptr_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaskedstorenq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv128ivmemv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaskedstorenq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_ptr_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaskedstorentnq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv64ivmemv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaskedstorentnq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_ptr_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaskedstorentnq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv128ivmemv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaskedstorentnq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_ptr_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaskedstorentq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv64ivmemv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaskedstorentq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_ptr_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaskedstorentq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv128ivmemv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaskedstorentq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_ptr_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaskedstoreq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv64ivmemv512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaskedstoreq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_ptr_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaskedstoreq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_vv128ivmemv1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaskedstoreq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_ptr_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmaxw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmaxw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vminw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vminw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabus {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabus_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabus_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabus_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabus_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabus_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabus_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabusv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabusv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabusv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabusv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabuu {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabuu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabuu_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabuu_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabuu_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabuu_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabuu_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabuu_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabuuv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabuuv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpabuuv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpabuuv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpahb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpahb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpahb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpahb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpahb_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpahb_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpahb_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpahb_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpahhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpahhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpahhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpahhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpauhb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpauhb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpauhb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpauhb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpauhb_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpauhb_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpauhb_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpauhb_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpauhuhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpauhuhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpauhuhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpauhuhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpsuhuhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpsuhuhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpsuhuhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpsuhuhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybus {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybus_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybus_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybus_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybus_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybus_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybus_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybusv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybusv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybusv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybusv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybusv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybusv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybusv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybusv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpybv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpybv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyewuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyewuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyewuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyewuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyewuh_64 {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyewuh_64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyewuh_64_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyewuh_64_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyh_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v2048v2048v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyh_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhsat_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhsat_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhsat_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhsat_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhsrs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhsrs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhsrs_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhsrs_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhss {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhss_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhss_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhus {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhus_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhus_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhus_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhus_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhus_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhus_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhvsrs {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhvsrs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyhvsrs_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyhvsrs_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyieoh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyieoh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyieoh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyieoh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiewh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiewh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiewh_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiewh_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiewuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiewuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiewuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiewuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiewuh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiewuh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiewuh_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiewuh_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyih {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyih";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyih_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyih_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyih_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyih_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyih_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyih_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyihb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyihb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyihb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyihb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyihb_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyihb_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyihb_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyihb_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiowh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiowh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiowh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiowh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwb_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwb_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwb_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwb_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwh_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwh_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwub_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwub_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyiwub_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyiwub_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh_64_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh_64_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh_64_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh_64_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh_rnd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh_rnd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh_rnd_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh_rnd_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh_rnd_sacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh_rnd_sacc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh_sacc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh_sacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyowh_sacc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyowh_sacc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyub_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyub_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyub_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyub_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyubv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyubv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyubv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyubv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyubv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyubv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyubv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyubv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuh_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuh_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuh_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuh_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuhe {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuhe";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuhe_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuhe_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuhe_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuhe_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuhe_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuhe_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuhv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuhv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuhv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuhv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuhv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuhv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmpyuhv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmpyuhv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmux {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmux";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vmux_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vmux_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnavgb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnavgb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnavgb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnavgb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnavgh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnavgh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnavgh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnavgh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnavgub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnavgub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnavgub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnavgub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnavgw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnavgw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnavgw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnavgw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnormamth {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnormamth";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnormamth_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnormamth_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnormamtw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnormamtw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnormamtw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnormamtw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnot {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnot";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vnot_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vnot_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackeb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackeb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackeb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackeb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackeh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackeh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackeh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackeh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackhb_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackhb_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackhb_sat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackhb_sat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackhub_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackhub_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackhub_sat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackhub_sat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackob {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackob";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackob_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackob_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackoh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackoh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackoh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackoh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackwh_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackwh_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackwh_sat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackwh_sat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackwuh_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackwuh_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpackwuh_sat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpackwuh_sat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpopcounth {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpopcounth";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vpopcounth_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vpopcounth_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vprefixqb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vprefixqb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vprefixqb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vprefixqb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vprefixqh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vprefixqh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vprefixqh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vprefixqh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vprefixqw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v512v64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vprefixqw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vprefixqw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vprefixqw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrdelta {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrdelta";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrdelta_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrdelta_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybub_rtt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v512LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybub_rtt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybub_rtt_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v2048v1024LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybub_rtt_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybub_rtt_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v512LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybub_rtt_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybub_rtt_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v2048v2048v1024LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybub_rtt_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybus {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybus_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybus_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybus_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybus_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybus_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybus_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybusi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybusi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybusi_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybusi_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybusi_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybusi_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybusi_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybusi_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybusv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybusv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybusv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybusv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybusv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybusv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybusv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybusv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpybv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpybv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyub_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyub_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyub_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyub_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyub_rtt {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v512LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyub_rtt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyub_rtt_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v2048v1024LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyub_rtt_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyub_rtt_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v1024v1024v512LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyub_rtt_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyub_rtt_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_v2048v2048v1024LLi_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyubi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyubi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyubi_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyubi_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyubi_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyubi_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyubi_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyubi_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyubv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyubv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyubv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyubv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyubv_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyubv_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrmpyubv_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrmpyubv_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vror {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vror";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vror_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vror_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vroundhb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vroundhb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vroundhb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vroundhb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vroundhub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vroundhub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vroundhub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vroundhub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrounduhub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrounduhub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrounduhub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrounduhub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrounduwuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrounduwuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrounduwuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrounduwuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vroundwh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vroundwh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vroundwh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vroundwh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vroundwuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vroundwuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vroundwuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vroundwuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrsadubi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrsadubi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrsadubi_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrsadubi_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrsadubi_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrsadubi_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vrsadubi_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048ii_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vrsadubi_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsathub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsathub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsathub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsathub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsatuwuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsatuwuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsatuwuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsatuwuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsatwh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsatwh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsatwh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsatwh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermh_add {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermh_add";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermh_add_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermh_add_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermhq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vv64iiiv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermhq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermhq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vv128iiiv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermhq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermhw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermhw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermhw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermhw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v64i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermhw_add {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermhw_add";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermhw_add_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermhw_add_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v64i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermhwq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vv64iiiv1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermhwq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermhwq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vv128iiiv2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermhwq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v64i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermw_add {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermw_add";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermw_add_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_viiv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermw_add_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermwq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vv64iiiv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermwq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vscattermwq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V65_vv128iiiv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vscattermwq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshufeh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshufeh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshufeh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshufeh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffeb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffeb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffeb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffeb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffob {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffob";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffob_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffob_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffvdd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffvdd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshuffvdd_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshuffvdd_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshufoeb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshufoeb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshufoeb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshufoeb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshufoeh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshufoeh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshufoeh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshufoeh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshufoh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshufoh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vshufoh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vshufoh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubb_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubb_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubb_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubb_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubbnq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubbnq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubbnq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubbnq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubbq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubbq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubbq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubbq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubbsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubbsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubbsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubbsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubbsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubbsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubbsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubbsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubcarry {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512v64i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_v6_vsubcarry";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty, llvm_v512i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v512i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubcarry_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024v128i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_v6_vsubcarry_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty, llvm_v1024i1_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_v1024i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubh_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubh_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubh_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubh_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhnq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhnq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhnq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhnq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubhw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubhw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsububh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsububh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsububh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsububh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsububsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsububsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsububsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsububsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsububsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsububsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsububsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsububsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubububb_sat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubububb_sat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubububb_sat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubububb_sat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuhsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuhsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuhsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuhsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuhsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuhsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuhsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuhsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuhw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuhw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuhw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuhw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuwsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuwsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuwsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuwsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuwsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuwsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubuwsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_V62_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubuwsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubw_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubw_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubw_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubw_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubw_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubw_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubwnq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubwnq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubwnq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubwnq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubwq {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubwq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubwq_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubwq_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubwsat {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubwsat";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubwsat_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubwsat_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubwsat_dv {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubwsat_dv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vsubwsat_dv_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vsubwsat_dv_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vswap {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v64iv512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vswap";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v512i1_ty, llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vswap_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v128iv1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vswap_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v1024i1_ty, llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpyb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpyb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpyb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpyb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpyb_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpyb_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpyb_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpyb_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpybus {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpybus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpybus_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpybus_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpybus_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpybus_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpybus_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpybus_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpyhb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpyhb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpyhb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpyhb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpyhb_acc {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpyhb_acc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vtmpyhb_acc_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v2048i_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vtmpyhb_acc_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v64i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackob {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackob";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackob_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackob_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackoh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackoh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackoh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackoh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v64i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackub_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackub_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackuh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vunpackuh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vunpackuh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vxor {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v512v512v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vxor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vxor_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v1024v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vxor_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty, llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vzb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vzb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vzb_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vzb_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vzh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v1024v512_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vzh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v32i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_V6_vzh_128B {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v2048v1024_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_V6_vzh_128B";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v64i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_Y2_dccleana {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_Y2_dccleana";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_Y2_dccleaninva {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_Y2_dccleaninva";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_Y2_dcinva {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_Y2_dcinva";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_Y2_dczeroa {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_Y2_dczeroa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, IntrHasSideEffects];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_Y4_l2fetch {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_Y4_l2fetch";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_Y5_l2fetch {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_Y5_l2fetch";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_ldb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memmemsisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_ldb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_ldd {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memmemsisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_ldd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_ldh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memmemsisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_ldh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_ldub {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memmemsisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_ldub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_lduh {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memmemsisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_lduh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_ldw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memmemsisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_ldw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_stb {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memsisisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_stb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_std {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memdisisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_std";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_sth {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memsisisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_sth";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_sthhi {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memsisisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_sthhi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_circ_stw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_mem_memsisisi_Intrinsic
  string GCCBuiltinName = "__builtin_circ_stw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_mm256i_vaddw {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic Hexagon_v256_v256v256_Intrinsic
  string GCCBuiltinName = "__builtin__mm256i_vaddw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_hexagon_prefetch {	// GCCBuiltin SDPatternOperator Intrinsic Hexagon_Intrinsic
  string GCCBuiltinName = "__builtin_HEXAGON_prefetch";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "hexagon";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_icall_branch_funnel {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_vararg_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_init_trampoline {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_init_trampoline";
  string NAME = ?;
}
def int_instrprof_increment {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_instrprof_increment_step {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_instrprof_value_profile {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_invariant_end {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_descriptor_ty, llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_1];
  bit isTarget = 0;
  string NAME = ?;
}
def int_invariant_start {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_descriptor_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_0];
  bit isTarget = 0;
  string NAME = ?;
}
def int_launder_invariant_group {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_lifetime_end {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_0];
  bit isTarget = 0;
  string NAME = ?;
}
def int_lifetime_start {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_0];
  bit isTarget = 0;
  string NAME = ?;
}
def int_load_relative {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_anyint_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_localaddress {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_localescape {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_vararg_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_localrecover {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_log {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_log10 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_log2 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_longjmp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoReturn];
  bit isTarget = 0;
  string NAME = ?;
}
def int_masked_compressstore {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_15, anonymous_13];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_masked_expandload {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_15, anonymous_13, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_masked_gather {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_14, llvm_i32_ty, anonymous_13, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_masked_load {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyvector_ty];
  list<LLVMType> ParamTypes = [anonymous_12, llvm_i32_ty, anonymous_13, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_masked_scatter {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_14, llvm_i32_ty, anonymous_13];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_masked_store {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyvector_ty, anonymous_12, llvm_i32_ty, anonymous_13];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_maxnum {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_memcpy {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3, anonymous_0, anonymous_4, anonymous_5];
  bit isTarget = 0;
  string NAME = ?;
}
def int_memcpy_element_unordered_atomic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3, anonymous_0, anonymous_4, anonymous_5];
  bit isTarget = 0;
  string NAME = ?;
}
def int_memmove {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3, anonymous_0, anonymous_5];
  bit isTarget = 0;
  string NAME = ?;
}
def int_memmove_element_unordered_atomic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3, anonymous_0, anonymous_4, anonymous_5];
  bit isTarget = 0;
  string NAME = ?;
}
def int_memset {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3, anonymous_4];
  bit isTarget = 0;
  string NAME = ?;
}
def int_memset_element_unordered_atomic {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3, anonymous_4];
  bit isTarget = 0;
  string NAME = ?;
}
def int_minnum {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_absq_s_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_absq_s_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_absq_s_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_absq_s_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v4q7_ty];
  list<LLVMType> ParamTypes = [mips_v4q7_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_absq_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_absq_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_add_a_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_add_a_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_add_a_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_add_a_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_add_a_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_add_a_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_add_a_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_add_a_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addq_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addq_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addq_s_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addq_s_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addq_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addq_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addqh_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addqh_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addqh_r_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addqh_r_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addqh_r_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addqh_r_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addqh_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addqh_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_a_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_a_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_a_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_a_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_a_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_a_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_a_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_a_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adds_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_adds_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addsc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addsc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addu_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addu_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addu_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addu_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addu_s_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addu_s_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addu_s_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addu_s_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adduh_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_adduh_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_adduh_r_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_adduh_r_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addv_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_addv_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addv_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_addv_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addv_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_addv_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addv_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_addv_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addvi_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_addvi_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addvi_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_addvi_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addvi_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_addvi_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addvi_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_addvi_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_addwc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_addwc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_and_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_and_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_andi_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_andi_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_append {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_append";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_asub_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_asub_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_asub_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_asub_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_asub_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_asub_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_asub_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_asub_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_asub_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_asub_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_asub_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_asub_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_asub_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_asub_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_asub_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_asub_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ave_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ave_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ave_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ave_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ave_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ave_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ave_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ave_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ave_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ave_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ave_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ave_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ave_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ave_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ave_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ave_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_aver_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_aver_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_aver_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_aver_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_aver_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_aver_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_aver_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_aver_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_aver_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_aver_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_aver_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_aver_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_aver_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_aver_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_aver_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_aver_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative, IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_balign {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_balign";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bclr_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bclr_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bclr_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bclr_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bclr_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bclr_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bclr_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bclr_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bclri_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bclri_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bclri_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bclri_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bclri_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bclri_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bclri_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bclri_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsl_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsl_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsl_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsl_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsl_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsl_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsl_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsl_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsli_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsli_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsli_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsli_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsli_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsli_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsli_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsli_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsr_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsr_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsr_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsr_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsr_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsr_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsr_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsr_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsri_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsri_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsri_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsri_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsri_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsri_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_binsri_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_binsri_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bitrev {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_bitrev";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bmnz_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bmnz_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bmnzi_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bmnzi_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bmz_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bmz_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bmzi_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bmzi_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bneg_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bneg_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bneg_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bneg_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bneg_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bneg_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bneg_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bneg_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bnegi_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bnegi_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bnegi_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bnegi_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bnegi_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bnegi_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bnegi_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bnegi_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bnz_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bnz_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bnz_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bnz_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bnz_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bnz_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bnz_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bnz_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bnz_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bnz_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bposge32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_bposge32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bsel_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bsel_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bseli_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bseli_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bset_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bset_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bset_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bset_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bset_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bset_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bset_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bset_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bseti_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bseti_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bseti_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bseti_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bseti_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bseti_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bseti_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bseti_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bz_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bz_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bz_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bz_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bz_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bz_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bz_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bz_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_bz_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_bz_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ceq_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ceq_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ceq_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ceq_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ceq_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ceq_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ceq_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ceq_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ceqi_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ceqi_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ceqi_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ceqi_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ceqi_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ceqi_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ceqi_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ceqi_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cfcmsa {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_cfcmsa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cle_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_cle_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cle_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_cle_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cle_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_cle_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cle_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_cle_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cle_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_cle_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cle_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_cle_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cle_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_cle_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cle_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_cle_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clei_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clei_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clei_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clei_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clei_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clei_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clei_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clei_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clei_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clei_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clei_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clei_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clei_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clei_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clei_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clei_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clt_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clt_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clt_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clt_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clt_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clt_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clt_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clt_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clt_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clt_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clt_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clt_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clt_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clt_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clt_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clt_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clti_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clti_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clti_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clti_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clti_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clti_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clti_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clti_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clti_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clti_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clti_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clti_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clti_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clti_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_clti_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_clti_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmp_eq_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmp_eq_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmp_le_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmp_le_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmp_lt_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmp_lt_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmpgdu_eq_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmpgdu_eq_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmpgdu_le_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmpgdu_le_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmpgdu_lt_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmpgdu_lt_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmpgu_eq_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmpgu_eq_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmpgu_le_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmpgu_le_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmpgu_lt_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmpgu_lt_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmpu_eq_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmpu_eq_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmpu_le_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmpu_le_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_cmpu_lt_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_cmpu_lt_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_copy_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_copy_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_copy_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_copy_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_copy_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_copy_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_copy_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_copy_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_copy_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_copy_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_copy_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_copy_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_copy_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_copy_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_copy_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_copy_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ctcmsa {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ctcmsa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_div_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_div_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_div_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_div_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_div_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_div_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_div_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_div_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_div_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_div_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_div_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_div_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_div_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_div_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_div_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_div_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dlsa {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dlsa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dotp_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dotp_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dotp_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dotp_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dotp_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dotp_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dotp_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dotp_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dotp_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dotp_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dotp_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dotp_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpa_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpa_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpadd_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpadd_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpadd_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpadd_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpadd_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpadd_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpadd_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpadd_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpadd_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpadd_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpadd_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpadd_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpaq_s_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpaq_s_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpaq_sa_l_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpaq_sa_l_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpaqx_s_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpaqx_s_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpaqx_sa_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpaqx_sa_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpau_h_qbl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpau_h_qbl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpau_h_qbr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpau_h_qbr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpax_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpax_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dps_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dps_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsq_s_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpsq_s_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsq_sa_l_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpsq_sa_l_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsqx_s_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpsqx_s_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsqx_sa_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpsqx_sa_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsu_h_qbl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpsu_h_qbl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsu_h_qbr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpsu_h_qbr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsub_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpsub_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsub_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpsub_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsub_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpsub_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsub_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpsub_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsub_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpsub_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsub_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_dpsub_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_dpsx_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_dpsx_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_extp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_extp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_extpdp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_extpdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_extr_r_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_extr_r_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_extr_rs_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_extr_rs_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_extr_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_extr_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_extr_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_extr_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fadd_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fadd_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fadd_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fadd_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcaf_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcaf_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcaf_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcaf_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fceq_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fceq_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fceq_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fceq_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fclass_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fclass_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fclass_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fclass_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcle_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcle_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcle_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcle_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fclt_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fclt_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fclt_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fclt_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcne_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcne_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcne_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcne_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcor_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcor_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcor_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcor_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcueq_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcueq_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcueq_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcueq_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcule_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcule_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcule_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcule_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcult_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcult_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcult_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcult_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcun_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcun_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcun_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcun_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcune_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcune_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fcune_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fcune_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fdiv_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fdiv_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fdiv_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fdiv_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fexdo_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fexdo_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8f16_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fexdo_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fexdo_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fexp2_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fexp2_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fexp2_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fexp2_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fexupl_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fexupl_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fexupl_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fexupl_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fexupr_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fexupr_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fexupr_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fexupr_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ffint_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ffint_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ffint_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ffint_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ffint_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ffint_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ffint_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ffint_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ffql_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ffql_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ffql_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ffql_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ffqr_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ffqr_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ffqr_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ffqr_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fill_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fill_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fill_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fill_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fill_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fill_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fill_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fill_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_flog2_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_flog2_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_flog2_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_flog2_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmadd_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmadd_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmadd_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmadd_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmax_a_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmax_a_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmax_a_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmax_a_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmax_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmax_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmax_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmax_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmin_a_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmin_a_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmin_a_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmin_a_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmin_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmin_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmin_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmin_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmsub_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmsub_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmsub_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmsub_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmul_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmul_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fmul_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fmul_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_frcp_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_frcp_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_frcp_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_frcp_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_frint_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_frint_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_frint_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_frint_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_frsqrt_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_frsqrt_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_frsqrt_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_frsqrt_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsaf_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsaf_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsaf_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsaf_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fseq_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fseq_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fseq_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fseq_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsle_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsle_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsle_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsle_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fslt_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fslt_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fslt_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fslt_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsne_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsne_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsne_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsne_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsor_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsor_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsor_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsor_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsqrt_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsqrt_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsqrt_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsqrt_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsub_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsub_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsub_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsub_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsueq_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsueq_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsueq_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsueq_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsule_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsule_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsule_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsule_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsult_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsult_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsult_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsult_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsun_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsun_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsun_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsun_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsune_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsune_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_fsune_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_fsune_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftint_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftint_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftint_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftint_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftint_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftint_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftint_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftint_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftq_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftq_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftq_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftq_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftrunc_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftrunc_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftrunc_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftrunc_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftrunc_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftrunc_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ftrunc_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ftrunc_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hadd_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hadd_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hadd_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hadd_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hadd_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hadd_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hadd_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hadd_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hadd_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hadd_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hadd_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hadd_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hsub_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hsub_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hsub_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hsub_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hsub_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hsub_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hsub_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hsub_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hsub_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hsub_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_hsub_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_hsub_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvev_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvev_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvev_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvev_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvev_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvev_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvev_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvev_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvl_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvl_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvl_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvl_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvl_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvl_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvl_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvl_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvod_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvod_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvod_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvod_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvod_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvod_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvod_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvod_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvr_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvr_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvr_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvr_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvr_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvr_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ilvr_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ilvr_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_insert_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_insert_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_insert_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_insert_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_insert_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_insert_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_insert_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_insert_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_insv {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_insv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_insve_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_insve_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_insve_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_insve_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_insve_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_insve_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_insve_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_insve_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_lbux {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_lbux";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ld_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ld_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ld_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ld_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ld_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ld_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ld_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ld_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ldi_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ldi_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ldi_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ldi_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ldi_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ldi_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ldi_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ldi_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_lhx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_lhx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_lsa {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_lsa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_lwx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_lwx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_madd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_madd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_madd_q_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_madd_q_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_madd_q_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_madd_q_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maddr_q_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maddr_q_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maddr_q_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maddr_q_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maddu {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_maddu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maddv_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maddv_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maddv_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maddv_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maddv_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maddv_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maddv_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maddv_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maq_s_w_phl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_maq_s_w_phl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maq_s_w_phr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_maq_s_w_phr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maq_sa_w_phl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_maq_sa_w_phl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maq_sa_w_phr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_maq_sa_w_phr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_a_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_a_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_a_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_a_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_a_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_a_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_a_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_a_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_max_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_max_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maxi_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maxi_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maxi_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maxi_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maxi_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maxi_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maxi_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maxi_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maxi_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maxi_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maxi_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maxi_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maxi_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maxi_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_maxi_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_maxi_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_a_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_a_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_a_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_a_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_a_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_a_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_a_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_a_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_min_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_min_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mini_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mini_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mini_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mini_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mini_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mini_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mini_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mini_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mini_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mini_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mini_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mini_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mini_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mini_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mini_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mini_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mod_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mod_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mod_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mod_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mod_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mod_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mod_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mod_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mod_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mod_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mod_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mod_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mod_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mod_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mod_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mod_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_modsub {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_modsub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_move_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_move_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msub {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_msub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msub_q_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_msub_q_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msub_q_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_msub_q_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msubr_q_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_msubr_q_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msubr_q_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_msubr_q_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msubu {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_msubu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msubv_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_msubv_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msubv_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_msubv_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msubv_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_msubv_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_msubv_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_msubv_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mthlip {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mthlip";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mul_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mul_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mul_q_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mul_q_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mul_q_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mul_q_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mul_s_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mul_s_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_muleq_s_w_phl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_muleq_s_w_phl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_muleq_s_w_phr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_muleq_s_w_phr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_muleu_s_ph_qbl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_muleu_s_ph_qbl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_muleu_s_ph_qbr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_muleu_s_ph_qbr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulq_rs_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mulq_rs_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulq_rs_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mulq_rs_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulq_s_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mulq_s_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulq_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mulq_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulr_q_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mulr_q_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulr_q_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mulr_q_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulsa_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mulsa_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulsaq_s_w_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mulsaq_s_w_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mult {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_mult";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_multu {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_multu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulv_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mulv_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulv_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mulv_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulv_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mulv_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_mulv_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_mulv_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nloc_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nloc_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nloc_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nloc_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nloc_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nloc_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nloc_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nloc_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nlzc_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nlzc_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nlzc_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nlzc_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nlzc_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nlzc_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nlzc_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nlzc_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nor_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nor_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_nori_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_nori_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_or_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_or_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_ori_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_ori_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_packrl_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_packrl_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pckev_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pckev_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pckev_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pckev_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pckev_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pckev_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pckev_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pckev_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pckod_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pckod_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pckod_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pckod_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pckod_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pckod_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pckod_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pckod_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pcnt_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pcnt_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pcnt_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pcnt_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pcnt_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pcnt_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pcnt_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_pcnt_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pick_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_pick_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_pick_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_pick_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_preceq_w_phl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_preceq_w_phl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_preceq_w_phr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_preceq_w_phr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precequ_ph_qbl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precequ_ph_qbl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precequ_ph_qbla {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precequ_ph_qbla";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precequ_ph_qbr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precequ_ph_qbr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precequ_ph_qbra {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precequ_ph_qbra";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_preceu_ph_qbl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_preceu_ph_qbl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_preceu_ph_qbla {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_preceu_ph_qbla";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_preceu_ph_qbr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_preceu_ph_qbr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_preceu_ph_qbra {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_preceu_ph_qbra";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precr_qb_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precr_qb_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precr_sra_ph_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precr_sra_ph_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precr_sra_r_ph_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precr_sra_r_ph_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precrq_ph_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precrq_ph_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precrq_qb_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precrq_qb_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precrq_rs_ph_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precrq_rs_ph_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_precrqu_s_qb_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_precrqu_s_qb_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_prepend {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_prepend";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_raddu_w_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_raddu_w_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_rddsp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_rddsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_repl_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_repl_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_repl_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_repl_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sat_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sat_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sat_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sat_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sat_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sat_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sat_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sat_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sat_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sat_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sat_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sat_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sat_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sat_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sat_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sat_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shf_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_shf_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shf_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_shf_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shf_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_shf_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shilo {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shilo";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shll_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shll_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shll_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shll_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shll_s_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shll_s_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shll_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shll_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shra_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shra_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shra_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shra_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shra_r_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shra_r_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shra_r_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shra_r_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shra_r_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shra_r_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shrl_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shrl_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_shrl_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_shrl_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sld_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sld_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sld_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sld_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sld_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sld_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sld_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sld_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sldi_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sldi_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sldi_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sldi_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sldi_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sldi_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sldi_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sldi_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sll_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sll_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sll_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sll_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sll_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sll_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sll_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sll_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_slli_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_slli_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_slli_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_slli_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_slli_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_slli_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_slli_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_slli_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_splat_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_splat_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_splat_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_splat_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_splat_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_splat_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_splat_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_splat_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_splati_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_splati_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_splati_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_splati_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_splati_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_splati_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_splati_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_splati_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sra_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sra_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sra_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sra_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sra_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sra_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_sra_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_sra_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srai_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srai_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srai_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srai_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srai_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srai_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srai_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srai_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srar_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srar_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srar_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srar_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srar_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srar_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srar_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srar_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srari_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srari_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srari_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srari_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srari_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srari_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srari_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srari_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srl_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srl_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srl_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srl_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srl_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srl_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srl_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srl_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srli_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srli_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srli_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srli_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srli_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srli_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srli_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srli_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srlr_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srlr_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srlr_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srlr_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srlr_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srlr_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srlr_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srlr_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srlri_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srlri_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srlri_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srlri_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srlri_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srlri_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_srlri_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_srlri_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_st_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_st_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_st_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_st_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_st_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_st_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_st_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_st_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subq_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subq_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subq_s_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subq_s_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subq_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subq_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subqh_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subqh_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subqh_r_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subqh_r_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_v2q15_ty];
  list<LLVMType> ParamTypes = [mips_v2q15_ty, mips_v2q15_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subqh_r_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subqh_r_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subqh_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subqh_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [mips_q31_ty];
  list<LLVMType> ParamTypes = [mips_q31_ty, mips_q31_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subs_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subs_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subs_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subs_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subs_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subs_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subs_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subs_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subs_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subs_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subs_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subs_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subs_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subs_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subs_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subs_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subsus_u_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subsus_u_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subsus_u_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subsus_u_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subsus_u_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subsus_u_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subsus_u_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subsus_u_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subsuu_s_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subsuu_s_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subsuu_s_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subsuu_s_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subsuu_s_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subsuu_s_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subsuu_s_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subsuu_s_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subu_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subu_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subu_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subu_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subu_s_ph {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subu_s_ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i16_ty, llvm_v2i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subu_s_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subu_s_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subuh_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subuh_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subuh_r_qb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_subuh_r_qb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i8_ty, llvm_v4i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subv_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subv_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subv_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subv_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subv_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subv_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subv_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subv_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subvi_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subvi_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subvi_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subvi_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subvi_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subvi_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_subvi_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_subvi_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_vshf_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_vshf_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_vshf_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_vshf_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_vshf_h {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_vshf_h";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_vshf_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_vshf_w";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_wrdsp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_mips_wrdsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_xor_v {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_xor_v";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_mips_xori_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_msa_xori_b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "mips";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nearbyint {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rm_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rm_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rm_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rm_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rm_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rm_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rn_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rn_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rn_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rn_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rn_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rn_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rp_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rp_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rp_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rp_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rp_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rp_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rz_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rz_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_add_rz_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_add_rz_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_add_gen_f_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_add_gen_f_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_add_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_add_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_and_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_and_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_cas_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC3_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_cas_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC3_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_dec_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_dec_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_exch_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_exch_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_inc_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_inc_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_load_add_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [anonymous_24, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_load_add_f64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [anonymous_25, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_load_dec_32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [anonymous_26, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_load_inc_32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [anonymous_26, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_max_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_max_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_min_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_min_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_or_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_or_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_xor_gen_i_cta {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_atomic_xor_gen_i_sys {	// SDPatternOperator Intrinsic SCOPED_ATOMIC2_impl
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_bar_sync {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_bar_sync";
  string NAME = ?;
}
def int_nvvm_bar_warp_sync {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_bar_warp_sync";
  string NAME = ?;
}
def int_nvvm_barrier {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_bar";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_barrier0 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__syncthreads";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_barrier0_and {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_bar0_and";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_barrier0_or {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_bar0_or";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_barrier0_popc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_bar0_popc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_barrier_n {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_bar_n";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_barrier_sync {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_barrier_sync";
  string NAME = ?;
}
def int_nvvm_barrier_sync_cnt {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_barrier_sync_cnt";
  string NAME = ?;
}
def int_nvvm_bitcast_d2ll {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_bitcast_d2ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_bitcast_f2i {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_bitcast_f2i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_bitcast_i2f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_bitcast_i2f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_bitcast_ll2d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_bitcast_ll2d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ceil_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ceil_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ceil_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ceil_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ceil_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ceil_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_compiler_error {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.compiler.error";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_compiler_warn {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.compiler.warn";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_cos_approx_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_cos_approx_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_cos_approx_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_cos_approx_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2f_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2f_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2f_rm_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2f_rm_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2f_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2f_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2f_rn_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2f_rn_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2f_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2f_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2f_rp_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2f_rp_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2f_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2f_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2f_rz_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2f_rz_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2i_hi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2i_hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2i_lo {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2i_lo";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2i_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2i_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2i_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2i_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2i_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2i_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2i_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2i_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ll_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ll_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ll_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ll_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ll_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ll_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ll_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ll_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ui_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ui_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ui_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ui_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ui_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ui_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ui_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ui_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ull_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ull_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ull_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ull_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ull_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ull_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_d2ull_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_d2ull_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_approx_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_approx_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_approx_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_approx_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rm_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rm_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rm_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rm_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rm_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rm_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rn_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rn_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rn_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rn_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rn_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rn_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rp_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rp_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rp_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rp_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rp_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rp_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rz_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rz_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_div_rz_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_div_rz_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ex2_approx_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ex2_approx_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ex2_approx_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ex2_approx_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ex2_approx_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ex2_approx_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2h_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2h_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2h_rn_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2h_rn_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2i_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2i_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2i_rm_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2i_rm_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2i_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2i_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2i_rn_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2i_rn_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2i_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2i_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2i_rp_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2i_rp_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2i_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2i_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2i_rz_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2i_rz_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ll_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ll_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ll_rm_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ll_rm_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ll_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ll_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ll_rn_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ll_rn_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ll_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ll_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ll_rp_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ll_rp_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ll_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ll_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ll_rz_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ll_rz_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ui_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ui_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ui_rm_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ui_rm_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ui_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ui_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ui_rn_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ui_rn_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ui_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ui_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ui_rp_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ui_rp_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ui_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ui_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ui_rz_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ui_rz_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ull_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ull_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ull_rm_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ull_rm_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ull_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ull_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ull_rn_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ull_rn_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ull_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ull_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ull_rp_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ull_rp_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ull_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ull_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_f2ull_rz_ftz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_f2ull_rz_ftz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fabs_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fabs_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fabs_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fabs_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fabs_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fabs_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_floor_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_floor_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_floor_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_floor_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_floor_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_floor_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rm_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rm_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rm_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rm_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rm_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rm_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rn_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rn_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rn_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rn_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rn_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rn_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rp_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rp_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rp_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rp_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rp_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rp_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rz_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rz_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fma_rz_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fma_rz_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fmax_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fmax_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fmax_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fmax_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fmax_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fmax_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fmin_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fmin_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fmin_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fmin_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fmin_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fmin_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_fns {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_fns";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_i2d_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_i2d_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_i2d_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_i2d_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_i2d_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_i2d_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_i2d_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_i2d_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_i2f_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_i2f_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_i2f_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_i2f_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_i2f_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_i2f_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_i2f_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_i2f_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_isspacep_const {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.isspacep.const";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_isspacep_const";
  string NAME = ?;
}
def int_nvvm_isspacep_global {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.isspacep.global";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_isspacep_global";
  string NAME = ?;
}
def int_nvvm_isspacep_local {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.isspacep.local";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_isspacep_local";
  string NAME = ?;
}
def int_nvvm_isspacep_shared {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.isspacep.shared";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_isspacep_shared";
  string NAME = ?;
}
def int_nvvm_istypep_sampler {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.istypep.sampler";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_istypep_sampler";
  string NAME = ?;
}
def int_nvvm_istypep_surface {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.istypep.surface";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_istypep_surface";
  string NAME = ?;
}
def int_nvvm_istypep_texture {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.istypep.texture";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_istypep_texture";
  string NAME = ?;
}
def int_nvvm_ldg_global_f {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ldg.global.f";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_12, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ldg_global_i {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ldg.global.i";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ldg_global_p {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ldg.global.p";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [anonymous_12, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ldu_global_f {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ldu.global.f";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_12, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ldu_global_i {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ldu.global.i";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_12, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ldu_global_p {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ldu.global.p";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [anonymous_12, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_lg2_approx_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_lg2_approx_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_lg2_approx_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_lg2_approx_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_lg2_approx_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_lg2_approx_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ll2d_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ll2d_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ll2d_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ll2d_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ll2d_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ll2d_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ll2d_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ll2d_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ll2f_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ll2f_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ll2f_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ll2f_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ll2f_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ll2f_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ll2f_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ll2f_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_lohi_i2d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_lohi_i2d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_match_all_sync_i32p {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.match.all.sync.i32p";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_match_all_sync_i64p {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.match.all.sync.i64p";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_match_any_sync_i32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.match.any.sync.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_match_any_sync_i32";
  string NAME = ?;
}
def int_nvvm_match_any_sync_i64 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.match.any.sync.i64";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_match_any_sync_i64";
  string NAME = ?;
}
def int_nvvm_membar_cta {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_membar_cta";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_membar_gl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_membar_gl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_membar_sys {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_membar_sys";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_move_double {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.move.double";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_move_float {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.move.float";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_move_i16 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.move.i16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_move_i32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.move.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_move_i64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.move.i64";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_move_ptr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.move.ptr";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul24_i {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul24_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul24_ui {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul24_ui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rm_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rm_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rm_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rm_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rm_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rm_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rn_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rn_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rn_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rn_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rn_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rn_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rp_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rp_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rp_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rp_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rp_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rp_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rz_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rz_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mul_rz_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mul_rz_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mulhi_i {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mulhi_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mulhi_ll {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mulhi_ll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mulhi_ui {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mulhi_ui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_mulhi_ull {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_mulhi_ull";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_prmt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_prmt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ptr_constant_to_gen {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ptr.constant.to.gen";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ptr_gen_to_constant {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ptr.gen.to.constant";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ptr_gen_to_global {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ptr.gen.to.global";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ptr_gen_to_local {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ptr.gen.to.local";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ptr_gen_to_param {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ptr.gen.to.param";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ptr_gen_to_shared {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ptr.gen.to.shared";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ptr_global_to_gen {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ptr.global.to.gen";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ptr_local_to_gen {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ptr.local.to.gen";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ptr_shared_to_gen {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.ptr.shared.to.gen";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_approx_ftz_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_approx_ftz_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rm_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rm_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rm_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rm_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rm_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rm_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rn_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rn_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rn_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rn_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rn_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rn_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rp_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rp_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rp_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rp_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rp_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rp_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rz_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rz_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rcp_rz_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rcp_rz_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_clock {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_clock";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_clock64 {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r64
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_clock64";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_ctaid_w {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_ctaid_w";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_ctaid_x {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_ctaid_x";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_ctaid_y {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_ctaid_y";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_ctaid_z {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_ctaid_z";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg0 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg0";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg0";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg1 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg1";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg1";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg10 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg10";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg10";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg11 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg11";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg11";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg12 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg12";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg12";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg13 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg13";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg13";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg14 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg14";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg14";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg15 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg15";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg15";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg16 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg16";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg17 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg17";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg17";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg18 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg18";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg18";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg19 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg19";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg19";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg2 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg2";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg2";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg20 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg20";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg20";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg21 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg21";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg21";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg22 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg22";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg22";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg23 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg23";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg23";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg24 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg24";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg24";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg25 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg25";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg25";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg26 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg26";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg26";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg27 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg27";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg27";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg28 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg28";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg28";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg29 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg29";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg29";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg3 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg3";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg3";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg30 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg30";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg30";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg31 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg31";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg31";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg4 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg4";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg4";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg5 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg5";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg5";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg6 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg6";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg6";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg7 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg7";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg7";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg8 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg8";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg8";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_envreg9 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.read.ptx.sreg.envreg9";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_envreg9";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_gridid {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_gridid";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_laneid {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_laneid";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_lanemask_eq {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_lanemask_eq";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_lanemask_ge {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_lanemask_ge";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_lanemask_gt {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_lanemask_gt";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_lanemask_le {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_lanemask_le";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_lanemask_lt {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_lanemask_lt";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_nctaid_w {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_nctaid_w";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_nctaid_x {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_nctaid_x";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_nctaid_y {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_nctaid_y";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_nctaid_z {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_nctaid_z";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_nsmid {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_nsmid";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_ntid_w {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_ntid_w";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_ntid_x {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_ntid_x";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_ntid_y {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_ntid_y";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_ntid_z {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_ntid_z";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_nwarpid {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_nwarpid";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_pm0 {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_pm0";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_pm1 {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_pm1";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_pm2 {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_pm2";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_pm3 {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_pm3";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_smid {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_smid";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_tid_w {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_tid_w";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_tid_x {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_tid_x";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_tid_y {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_tid_y";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_tid_z {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_tid_z";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_warpid {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_warpid";
  string NAME = ?;
}
def int_nvvm_read_ptx_sreg_warpsize {	// SDPatternOperator Intrinsic GCCBuiltin PTXReadSRegIntrinsic_r32
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_read_ptx_sreg_warpsize";
  string NAME = ?;
}
def int_nvvm_reflect {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.reflect";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rotate_b32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.rotate.b32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_rotate_b32";
  string NAME = ?;
}
def int_nvvm_rotate_b64 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.rotate.b64";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_rotate_b64";
  string NAME = ?;
}
def int_nvvm_rotate_right_b64 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.rotate.right.b64";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_rotate_right_b64";
  string NAME = ?;
}
def int_nvvm_round_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_round_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_round_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_round_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_round_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_round_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rsqrt_approx_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rsqrt_approx_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rsqrt_approx_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rsqrt_approx_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_rsqrt_approx_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_rsqrt_approx_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sad_i {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sad_i";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sad_ui {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sad_ui";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_saturate_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_saturate_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_saturate_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_saturate_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_saturate_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_saturate_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_shfl_bfly_f32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.bfly.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_bfly_f32";
  string NAME = ?;
}
def int_nvvm_shfl_bfly_i32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.bfly.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_bfly_i32";
  string NAME = ?;
}
def int_nvvm_shfl_down_f32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.down.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_down_f32";
  string NAME = ?;
}
def int_nvvm_shfl_down_i32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.down.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_down_i32";
  string NAME = ?;
}
def int_nvvm_shfl_idx_f32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.idx.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_idx_f32";
  string NAME = ?;
}
def int_nvvm_shfl_idx_i32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.idx.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_idx_i32";
  string NAME = ?;
}
def int_nvvm_shfl_sync_bfly_f32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.sync.bfly.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_sync_bfly_f32";
  string NAME = ?;
}
def int_nvvm_shfl_sync_bfly_i32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.sync.bfly.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_sync_bfly_i32";
  string NAME = ?;
}
def int_nvvm_shfl_sync_down_f32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.sync.down.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_sync_down_f32";
  string NAME = ?;
}
def int_nvvm_shfl_sync_down_i32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.sync.down.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_sync_down_i32";
  string NAME = ?;
}
def int_nvvm_shfl_sync_idx_f32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.sync.idx.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_sync_idx_f32";
  string NAME = ?;
}
def int_nvvm_shfl_sync_idx_i32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.sync.idx.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_sync_idx_i32";
  string NAME = ?;
}
def int_nvvm_shfl_sync_up_f32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.sync.up.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_sync_up_f32";
  string NAME = ?;
}
def int_nvvm_shfl_sync_up_i32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.sync.up.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_sync_up_i32";
  string NAME = ?;
}
def int_nvvm_shfl_up_f32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.up.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_up_f32";
  string NAME = ?;
}
def int_nvvm_shfl_up_i32 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.shfl.up.i32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_shfl_up_i32";
  string NAME = ?;
}
def int_nvvm_sin_approx_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sin_approx_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sin_approx_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sin_approx_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_approx_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_approx_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_approx_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_approx_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rm_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rm_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rm_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rm_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rm_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rm_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rn_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rn_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rn_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rn_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rn_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rn_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rp_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rp_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rp_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rp_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rp_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rp_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rz_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rz_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_sqrt_rz_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_sqrt_rz_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v2i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v4i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v4i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v4i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v4i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v4i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v4i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v4i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v4i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_array_v4i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.array.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v2i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v4i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v4i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v4i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v4i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v4i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v4i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v4i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v4i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_1d_v4i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.1d.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v2i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v4i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v4i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v4i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v4i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v4i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v4i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v4i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v4i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_array_v4i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.array.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v2i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v4i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v4i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v4i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v4i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v4i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v4i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v4i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v4i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_2d_v4i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.2d.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i64_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i64_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i64_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v2i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v4i16_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v4i16_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v4i16_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v4i32_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v4i32_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v4i32_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v4i8_clamp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v4i8_trap {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suld_3d_v4i8_zero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suld.3d.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_suq_array_size {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suq.array.size";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_suq_array_size";
  string NAME = ?;
}
def int_nvvm_suq_channel_data_type {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suq.channel.data.type";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_suq_channel_data_type";
  string NAME = ?;
}
def int_nvvm_suq_channel_order {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suq.channel.order";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_suq_channel_order";
  string NAME = ?;
}
def int_nvvm_suq_depth {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suq.depth";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_suq_depth";
  string NAME = ?;
}
def int_nvvm_suq_height {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suq.height";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_suq_height";
  string NAME = ?;
}
def int_nvvm_suq_width {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.suq.width";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_suq_width";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v2i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v2i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v4i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v4i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v4i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v4i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v4i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v4i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v4i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v4i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v4i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v4i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_array_v4i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.array.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_array_v4i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v2i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v2i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v4i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v4i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v4i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v4i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v4i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v4i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v4i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v4i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v4i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v4i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_1d_v4i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.1d.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_1d_v4i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v2i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v2i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v4i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v4i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v4i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v4i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v4i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v4i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v4i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v4i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v4i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v4i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_array_v4i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.array.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_array_v4i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v2i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v2i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v4i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v4i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v4i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v4i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v4i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v4i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v4i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v4i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v4i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v4i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_2d_v4i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.2d.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_2d_v4i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i64_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i64.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i64_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i64_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i64.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i64_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i64_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i64.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i64_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v2i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v2i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v2i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v4i16_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v4i16.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v4i16_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v4i16_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v4i16.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v4i16_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v4i32_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v4i32.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v4i32_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v4i32_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v4i32.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v4i32_zero";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v4i8_clamp {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v4i8.clamp";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v4i8_clamp";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_b_3d_v4i8_zero {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.b.3d.v4i8.zero";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_b_3d_v4i8_zero";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_array_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.array.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_array_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_array_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.array.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_array_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_array_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.array.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_array_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_array_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.array.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_array_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_array_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.array.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_array_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_array_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.array.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_array_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_array_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.array.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_array_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_array_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.array.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_array_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_array_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.array.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_array_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_1d_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.1d.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_1d_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_array_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.array.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_array_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_array_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.array.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_array_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_array_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.array.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_array_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_array_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.array.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_array_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_array_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.array.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_array_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_array_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.array.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_array_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_array_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.array.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_array_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_array_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.array.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_array_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_array_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.array.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_array_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_2d_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.2d.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_2d_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_3d_i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.3d.i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_3d_i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_3d_i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.3d.i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_3d_i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_3d_i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.3d.i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_3d_i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_3d_v2i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.3d.v2i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_3d_v2i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_3d_v2i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.3d.v2i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_3d_v2i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_3d_v2i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.3d.v2i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_3d_v2i8_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_3d_v4i16_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.3d.v4i16.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_3d_v4i16_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_3d_v4i32_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.3d.v4i32.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_3d_v4i32_trap";
  string NAME = ?;
}
def int_nvvm_sust_p_3d_v4i8_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.sust.p.3d.v4i8.trap";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_sust_p_3d_v4i8_trap";
  string NAME = ?;
}
def int_nvvm_swap_lo_hi_b64 {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.swap.lo.hi.b64";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_swap_lo_hi_b64";
  string NAME = ?;
}
def int_nvvm_tex_1d_array_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_array_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.array.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_1d_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.1d.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_array_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.array.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_2d_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.2d.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_3d_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.3d.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_array_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.array.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_array_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.array.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_array_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.array.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_array_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.array.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_array_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.array.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_array_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.array.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_cube_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.cube.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_array_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.array.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_1d_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.1d.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_array_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.array.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_2d_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.2d.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_grad_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.grad.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_grad_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.grad.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_grad_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.grad.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_v4f32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.v4f32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_v4s32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.v4s32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_3d_v4u32_s32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.3d.v4u32.s32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_array_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.array.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_array_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.array.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_array_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.array.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_array_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.array.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_array_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.array.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_array_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.array.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_level_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.level.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_level_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.level.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_level_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.level.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tex_unified_cube_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tex.unified.cube.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_texsurf_handle {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.texsurf.handle";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_metadata_ty, llvm_anyi64ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_texsurf_handle_internal {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.texsurf.handle.internal";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_a_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.a.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_a_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.a.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_a_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.a.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_b_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.b.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_b_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.b.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_b_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.b.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_g_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.g.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_g_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.g.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_g_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.g.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_r_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.r.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_r_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.r.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_r_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.r.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_a_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.a.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_a_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.a.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_a_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.a.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_b_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.b.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_b_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.b.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_b_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.b.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_g_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.g.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_g_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.g.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_g_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.g.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_r_2d_v4f32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.r.2d.v4f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_r_2d_v4s32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.r.2d.v4s32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_tld4_unified_r_2d_v4u32_f32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.tld4.unified.r.2d.v4u32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_trunc_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_trunc_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_trunc_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_trunc_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_trunc_ftz_f {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_trunc_ftz_f";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_txq_array_size {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.txq.array.size";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_txq_array_size";
  string NAME = ?;
}
def int_nvvm_txq_channel_data_type {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.txq.channel.data.type";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_txq_channel_data_type";
  string NAME = ?;
}
def int_nvvm_txq_channel_order {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.txq.channel.order";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_txq_channel_order";
  string NAME = ?;
}
def int_nvvm_txq_depth {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.txq.depth";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_txq_depth";
  string NAME = ?;
}
def int_nvvm_txq_height {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.txq.height";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_txq_height";
  string NAME = ?;
}
def int_nvvm_txq_num_mipmap_levels {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.txq.num.mipmap.levels";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_txq_num_mipmap_levels";
  string NAME = ?;
}
def int_nvvm_txq_num_samples {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.txq.num.samples";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_txq_num_samples";
  string NAME = ?;
}
def int_nvvm_txq_width {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.txq.width";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_txq_width";
  string NAME = ?;
}
def int_nvvm_ui2d_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ui2d_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ui2d_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ui2d_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ui2d_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ui2d_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ui2d_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ui2d_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ui2f_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ui2f_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ui2f_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ui2f_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ui2f_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ui2f_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ui2f_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ui2f_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ull2d_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ull2d_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ull2d_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ull2d_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ull2d_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ull2d_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ull2d_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ull2d_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ull2f_rm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ull2f_rm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ull2f_rn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ull2f_rn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ull2f_rp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ull2f_rp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_ull2f_rz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__nvvm_ull2f_rz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_vote_all {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.vote.all";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_vote_all";
  string NAME = ?;
}
def int_nvvm_vote_all_sync {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.vote.all.sync";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_vote_all_sync";
  string NAME = ?;
}
def int_nvvm_vote_any {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.vote.any";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_vote_any";
  string NAME = ?;
}
def int_nvvm_vote_any_sync {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.vote.any.sync";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_vote_any_sync";
  string NAME = ?;
}
def int_nvvm_vote_ballot {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.vote.ballot";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_vote_ballot";
  string NAME = ?;
}
def int_nvvm_vote_ballot_sync {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.vote.ballot.sync";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_vote_ballot_sync";
  string NAME = ?;
}
def int_nvvm_vote_uni {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.vote.uni";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_vote_uni";
  string NAME = ?;
}
def int_nvvm_vote_uni_sync {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.vote.uni.sync";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly, IntrConvergent];
  bit isTarget = 0;
  string GCCBuiltinName = "__nvvm_vote_uni_sync";
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_a_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.a.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_a_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.a.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_a_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.a.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_a_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.a.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_b_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.b.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_b_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.b.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_b_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.b.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_b_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.b.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_c_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.c.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_c_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.c.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_c_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.c.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_c_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.c.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_c_f32_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.c.col.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_c_f32_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.c.col.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_c_f32_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.c.row.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_load_c_f32_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.load.c.row.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_col_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.col.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_col_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.col.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_col_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.col.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_col_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.col.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_col_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.col.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_col_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.col.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_col_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.col.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_col_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.col.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_row_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.row.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_row_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.row.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_row_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.row.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_row_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.row.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_row_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.row.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_row_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.row.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_row_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.row.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_col_row_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.col.row.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_col_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.col.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_col_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.col.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_col_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.col.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_col_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.col.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_col_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.col.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_col_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.col.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_col_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.col.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_col_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.col.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_row_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_row_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_row_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_row_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_row_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.row.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_row_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.row.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_row_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.row.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_mma_row_row_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.mma.row.row.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_store_d_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.store.d.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_store_d_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.store.d.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_store_d_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.store.d.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_store_d_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.store.d.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_store_d_f32_col {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.store.d.col.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_store_d_f32_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.store.d.col.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_store_d_f32_row {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.store.d.row.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m16n16k16_store_d_f32_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m16n16k16.store.d.row.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_a_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.a.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_a_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.a.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_a_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.a.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_a_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.a.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_b_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.b.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_b_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.b.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_b_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.b.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_b_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.b.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_c_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.c.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_c_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.c.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_c_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.c.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_c_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.c.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_c_f32_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.c.col.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_c_f32_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.c.col.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_c_f32_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.c.row.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_load_c_f32_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.load.c.row.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_col_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.col.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_col_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.col.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_col_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.col.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_col_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.col.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_col_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.col.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_col_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.col.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_col_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.col.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_col_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.col.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_row_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.row.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_row_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.row.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_row_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.row.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_row_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.row.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_row_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.row.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_row_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.row.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_row_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.row.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_col_row_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.col.row.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_col_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.col.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_col_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.col.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_col_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.col.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_col_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.col.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_col_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.col.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_col_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.col.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_col_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.col.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_col_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.col.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_row_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.row.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_row_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.row.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_row_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.row.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_row_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.row.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_row_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.row.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_row_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.row.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_row_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.row.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_mma_row_row_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.mma.row.row.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_store_d_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.store.d.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_store_d_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.store.d.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_store_d_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.store.d.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_store_d_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.store.d.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_store_d_f32_col {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.store.d.col.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_store_d_f32_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.store.d.col.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_store_d_f32_row {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.store.d.row.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m32n8k16_store_d_f32_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m32n8k16.store.d.row.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_a_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.a.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_a_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.a.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_a_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.a.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_a_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.a.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_b_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.b.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_b_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.b.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_b_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.b.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_b_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.b.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_c_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.c.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_c_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.c.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_c_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.c.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_c_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.c.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_c_f32_col {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.c.col.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_c_f32_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.c.col.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_c_f32_row {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.c.row.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_load_c_f32_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_LD_GALSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.load.c.row.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_col_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.col.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_col_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.col.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_col_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.col.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_col_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.col.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_col_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.col.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_col_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.col.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_col_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.col.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_col_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.col.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_row_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.row.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_row_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.row.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_row_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.row.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_row_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.row.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_row_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.row.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_row_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.row.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_row_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.row.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_col_row_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.col.row.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_col_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.col.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_col_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.col.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_col_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.col.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_col_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.col.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_col_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.col.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_col_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.col.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_col_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.col.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_col_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.col.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_row_f16_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.row.f16.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_row_f16_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.row.f16.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_row_f16_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.row.f16.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_row_f16_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.row.f16.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_row_f32_f16 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.row.f32.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_row_f32_f16_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.row.f32.f16.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_row_f32_f32 {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.row.f32.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_mma_row_row_f32_f32_satfinite {	// SDPatternOperator Intrinsic NVVM_WMMA_MMA_GABDCS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.mma.row.row.f32.f32.satfinite";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<LLVMType> ParamTypes = [llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_store_d_f16_col {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.store.d.col.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_store_d_f16_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.store.d.col.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_store_d_f16_row {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.store.d.row.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_store_d_f16_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.store.d.row.stride.f16";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_v2f16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_store_d_f32_col {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.store.d.col.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_store_d_f32_col_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.store.d.col.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_store_d_f32_row {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.store.d.row.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_nvvm_wmma_m8n32k16_store_d_f32_row_stride {	// SDPatternOperator Intrinsic NVVM_WMMA_STD_GLSTS
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.nvvm.wmma.m8n32k16.store.d.row.stride.f32";
  string TargetPrefix = "nvvm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly, anonymous_4, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_objectsize {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i1_ty, llvm_i1_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_object_size";
  string NAME = ?;
}
def int_pcmarker {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_pow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_powi {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vcipher {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vcipher";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vcipherlast {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vcipherlast";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vncipher {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vncipher";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vncipherlast {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vncipherlast";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vpermxor {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vpermxor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vpmsumb {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vpmsumb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vpmsumd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vpmsumd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vpmsumh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vpmsumh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vpmsumw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vpmsumw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vsbox {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vsbox";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vshasigmad {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vshasigmad";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_crypto_vshasigmaw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_crypto_vshasigmaw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_dss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_dss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_dssall {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_dssall";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_dst {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_dst";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_dstst {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_dstst";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_dststt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_dststt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_dstt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_dstt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_lvebx {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_lvehx {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_lvewx {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_lvsl {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_lvsr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_lvx {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_lvxl {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_mfvscr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_mfvscr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_mtvscr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_mtvscr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_stvebx {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_stvehx {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_stvewx {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_stvx {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_stvxl {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vabsdub {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vabsdub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vabsduh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vabsduh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vabsduw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vabsduw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vaddcuq {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_QQQ_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vaddcuq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v1i128_ty];
  list<LLVMType> ParamTypes = [llvm_v1i128_ty, llvm_v1i128_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vaddcuw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vaddcuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vaddecuq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vaddecuq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v1i128_ty];
  list<LLVMType> ParamTypes = [llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vaddeuqm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vaddeuqm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v1i128_ty];
  list<LLVMType> ParamTypes = [llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vaddsbs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vaddsbs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vaddshs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vaddshs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vaddsws {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vaddsws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vaddubs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vaddubs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vadduhs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vadduhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vadduws {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vadduws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vavgsb {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vavgsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vavgsh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vavgsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vavgsw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vavgsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vavgub {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vavgub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vavguh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vavguh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vavguw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vavguw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vbpermq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vbpermq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcfsx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcfsx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcfux {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcfux";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vclzlsbb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vclzlsbb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpbfp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpbfp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpbfp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpbfp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpeqfp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpeqfp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpeqfp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpeqfp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpequb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpequb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpequb_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpequb_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpequd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpequd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpequd_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpequd_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpequh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpequh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpequh_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpequh_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpequw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpequw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpequw_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpequw_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgefp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgefp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgefp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgefp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtfp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtfp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtfp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtfp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtsb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtsb_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtsb_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtsd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtsd_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtsd_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtsh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtsh_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtsh_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtsw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtsw_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtsw_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtub {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtub_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtub_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtud {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtud";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtud_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtud_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtuh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtuh_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtuh_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtuw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpgtuw_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpgtuw_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpneb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpneb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpneb_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpneb_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpneh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpneh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpneh_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpneh_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpnew {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpnew";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpnew_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpnew_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpnezb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpnezb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpnezb_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpnezb_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpnezh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpnezh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpnezh_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpnezh_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpnezw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpnezw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vcmpnezw_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vcmpnezw_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vctsxs {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vctsxs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vctuxs {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vctuxs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vctzlsbb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vctzlsbb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vexptefp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_FF_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vexptefp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vgbbd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vgbbd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vlogefp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_FF_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vlogefp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaddfp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaddfp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaxfp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaxfp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaxsb {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaxsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaxsd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaxsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaxsh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaxsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaxsw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaxsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaxub {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaxub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaxud {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaxud";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaxuh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaxuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmaxuw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmaxuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmhaddshs {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmhaddshs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmhraddshs {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmhraddshs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vminfp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vminfp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vminsb {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vminsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vminsd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vminsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vminsh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vminsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vminsw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vminsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vminub {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vminub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vminud {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vminud";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vminuh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vminuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vminuw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vminuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmladduhm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmladduhm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmsummbm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmsummbm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmsumshm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmsumshm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmsumshs {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmsumshs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmsumubm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmsumubm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmsumuhm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmsumuhm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmsumuhs {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmsumuhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmulesb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmulesb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmulesh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmulesh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmulesw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmulesw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmuleub {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmuleub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmuleuh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmuleuh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmuleuw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmuleuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmulosb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmulosb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmulosh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmulosh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmulosw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmulosw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmuloub {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmuloub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmulouh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmulouh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vmulouw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vmulouw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vnmsubfp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vnmsubfp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vperm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vperm_4si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpkpx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpkpx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpksdss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpksdss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpksdus {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpksdus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpkshss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpkshss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpkshus {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpkshus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpkswss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpkswss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpkswus {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpkswus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpkudus {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpkudus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpkuhus {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpkuhus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vpkuwus {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vpkuwus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vprtybd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vprtybd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vprtybq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vprtybq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v1i128_ty];
  list<LLVMType> ParamTypes = [llvm_v1i128_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vprtybw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vprtybw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrefp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_FF_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrefp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrfim {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrfim";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrfin {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrfin";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrfip {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrfip";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrfiz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrfiz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrlb {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrlb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrld {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrld";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrldmi {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrldmi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrldnm {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrldnm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrlh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrlh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrlw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrlw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrlwmi {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrlwmi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrlwnm {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrlwnm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vrsqrtefp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_FF_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vrsqrtefp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsel {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsel_4si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsl {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vslb {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vslb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vslh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vslh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vslo {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vslo";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vslv {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vslv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vslw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vslw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsr {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsrab {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsrab";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsrah {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsrah";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsraw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsraw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsrb {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsrb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsrh {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsrh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsro {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsro";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsrv {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsrv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsrw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsrw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsubcuq {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_QQQ_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsubcuq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v1i128_ty];
  list<LLVMType> ParamTypes = [llvm_v1i128_ty, llvm_v1i128_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsubcuw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsubcuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsubecuq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsubecuq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v1i128_ty];
  list<LLVMType> ParamTypes = [llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsubeuqm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsubeuqm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v1i128_ty];
  list<LLVMType> ParamTypes = [llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsubsbs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsubsbs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsubshs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsubshs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsubsws {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsubsws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsububs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_BBB_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsububs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsubuhs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_HHH_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsubuhs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsubuws {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_Vec_Intrinsic PowerPC_Vec_WWW_Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsubuws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsum2sws {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsum2sws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsum4sbs {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsum4sbs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsum4shs {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsum4shs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsum4ubs {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsum4ubs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vsumsws {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vsumsws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vupkhpx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vupkhpx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vupkhsb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vupkhsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vupkhsh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vupkhsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vupkhsw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vupkhsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vupklpx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vupklpx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vupklsb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vupklsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vupklsh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vupklsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_altivec_vupklsw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_altivec_vupklsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_bpermd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_bpermd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_cfence {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyint_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_dcba {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_dcbf {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_dcbi {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_dcbst {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_dcbt {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_dcbtst {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_dcbz {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_dcbzl {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_divde {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_divde";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_divdeu {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_divdeu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_divwe {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_divwe";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_divweu {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_divweu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_get_texasr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_get_texasr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_get_texasru {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_get_texasru";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_get_tfhar {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_get_tfhar";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_get_tfiar {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_get_tfiar";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_is_decremented_ctr_nonzero {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoDuplicate];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_lwsync {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_mtctr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyint_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfabs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfabs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfadd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfadds {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfadds";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfcfid {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfcfid";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfcfids {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfcfids";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfcfidu {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfcfidu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfcfidus {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfcfidus";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfcmpeq {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfcmpeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfcmpgt {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfcmpgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfcmplt {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfcmplt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfcpsgn {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfcpsgn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfctid {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfctid";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfctidu {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfctidu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfctiduz {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfctiduz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfctidz {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfctidz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfctiw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfctiw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfctiwu {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfctiwu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfctiwuz {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfctiwuz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfctiwz {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfctiwz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvflogical {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvflogical";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfmadd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfmadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfmadds {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfmadds";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfmsub {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfmsub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfmsubs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfmsubs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfmul {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfmul";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfmuls {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfmuls";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfnabs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfnabs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfneg {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfneg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfnmadd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfnmadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfnmadds {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfnmadds";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfnmsub {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfnmsub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfnmsubs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfnmsubs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfperm {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfperm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfre {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfre";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfres {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfres";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfrim {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfrim";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfrin {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfrin";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfrip {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfrip";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfriz {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfriz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfrsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfrsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfrsqrte {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfrsqrte";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfrsqrtes {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfrsqrtes";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfsel {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfsel";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfsub {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfsub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfsubs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfsubs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvftstnan {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvftstnan";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxmadd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxmadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxmadds {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxmadds";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxmul {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxmul";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxmuls {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxmuls";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxxcpnmadd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxxcpnmadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxxcpnmadds {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxxcpnmadds";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxxmadd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxxmadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxxmadds {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxxmadds";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxxnpmadd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxxnpmadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvfxxnpmadds {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_FFFF_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvfxxnpmadds";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvgpci {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvgpci";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfcd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfcd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfcda {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfcda";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfcs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfcs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfcsa {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfcsa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfda {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfda";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfiwa {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfiwa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfiwaa {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfiwaa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfiwz {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfiwz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfiwza {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfiwza";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlfsa {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Load_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlfsa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlpcld {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_LoadPerm_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlpcld";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlpcls {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_LoadPerm_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlpcls";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlpcrd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_LoadPerm_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlpcrd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvlpcrs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_LoadPerm_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvlpcrs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfcd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfcd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfcda {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfcda";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfcs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfcs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfcsa {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfcsa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfd {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfda {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfda";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfiw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfiw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfiwa {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfiwa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfs {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfs";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_qpx_qvstfsa {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_QPX_Intrinsic PowerPC_QPX_Store_Intrinsic
  string GCCBuiltinName = "__builtin_qpx_qvstfsa";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_set_texasr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_set_texasr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_set_texasru {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_set_texasru";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_set_tfhar {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_set_tfhar";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_set_tfiar {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_set_tfiar";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_sync {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tabort {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tabort";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tabortdc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tabortdc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tabortdci {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tabortdci";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tabortwc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tabortwc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tabortwci {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tabortwci";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tbegin {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tbegin";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tcheck {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tcheck";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tend {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tend";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tendall {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tendall";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_trechkpt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_trechkpt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_treclaim {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_treclaim";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tresume {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tresume";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tsr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tsr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_tsuspend {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tsuspend";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_ttest {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ttest";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_lxvd2x {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_lxvd2x_be {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_lxvl {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_lxvll {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_lxvw4x {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_lxvw4x_be {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_stxvd2x {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_stxvd2x_be {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_stxvl {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_stxvll {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_stxvw4x {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_stxvw4x_be {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrWriteMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xsmaxdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic PowerPC_VSX_Sca_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xsmaxdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xsmindp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic PowerPC_VSX_Sca_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xsmindp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_double_ty];
  list<LLVMType> ParamTypes = [llvm_double_ty, llvm_double_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpeqdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpeqdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpeqdp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpeqdp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpeqsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpeqsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpeqsp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpeqsp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpgedp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpgedp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpgedp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpgedp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpgesp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpgesp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpgesp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpgesp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpgtdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpgtdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpgtdp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpgtdp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpgtsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpgtsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcmpgtsp_p {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcmpgtsp_p";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvdpsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvdpsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvdpsxws {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvdpsxws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvdpuxws {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvdpuxws";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvhpsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvhpsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvspdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvspdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvsphp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvsphp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvsxdsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvsxdsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvsxwdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvsxwdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvuxdsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvuxdsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvcvuxwdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvcvuxwdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvdivdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic PowerPC_VSX_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvdivdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvdivsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic PowerPC_VSX_Vec_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvdivsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xviexpdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xviexpdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xviexpsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xviexpsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvmaxdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic PowerPC_VSX_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvmaxdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvmaxsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic PowerPC_VSX_Vec_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvmaxsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvmindp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic PowerPC_VSX_Vec_DDD_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvmindp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvminsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic PowerPC_VSX_Vec_FFF_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvminsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvrdpip {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvredp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvredp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvresp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvresp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvrspip {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvrsqrtedp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvrsqrtedp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvrsqrtesp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvrsqrtesp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvtstdcdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvtstdcdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvtstdcsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvtstdcsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvxexpdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvxexpdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvxexpsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvxexpsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvxsigdp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvxsigdp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xvxsigsp {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xvxsigsp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xxextractuw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xxextractuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xxinsertw {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xxinsertw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ppc_vsx_xxleqv {	// GCCBuiltin SDPatternOperator Intrinsic PowerPC_VSX_Intrinsic
  string GCCBuiltinName = "__builtin_vsx_xxleqv";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "ppc";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_prefetch {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOrArgMemOnly, anonymous_2, anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ptr_annotation {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.ptr.annotation";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [anonymous_7];
  list<LLVMType> ParamTypes = [anonymous_6, llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_cube {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_group_barrier {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_r600_group_barrier";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrConvergent];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_implicitarg_ptr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_r600_implicitarg_ptr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [anonymous_27];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_rat_store_typed {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_rat_store_typed";
  string NAME = ?;
}
def int_r600_read_global_size_x {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_read_global_size_x";
  string NAME = ?;
}
def int_r600_read_global_size_y {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_read_global_size_y";
  string NAME = ?;
}
def int_r600_read_global_size_z {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_read_global_size_z";
  string NAME = ?;
}
def int_r600_read_local_size_x {	// SDPatternOperator Intrinsic AMDGPUReadPreloadRegisterIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_read_local_size_y {	// SDPatternOperator Intrinsic AMDGPUReadPreloadRegisterIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_read_local_size_z {	// SDPatternOperator Intrinsic AMDGPUReadPreloadRegisterIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_read_ngroups_x {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_read_ngroups_x";
  string NAME = ?;
}
def int_r600_read_ngroups_y {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_read_ngroups_y";
  string NAME = ?;
}
def int_r600_read_ngroups_z {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_read_ngroups_z";
  string NAME = ?;
}
def int_r600_read_tgid_x {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_read_tgid_x";
  string NAME = ?;
}
def int_r600_read_tgid_y {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_read_tgid_y";
  string NAME = ?;
}
def int_r600_read_tgid_z {	// SDPatternOperator Intrinsic GCCBuiltin AMDGPUReadPreloadRegisterIntrinsicNamed
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_r600_read_tgid_z";
  string NAME = ?;
}
def int_r600_read_tidig_x {	// SDPatternOperator Intrinsic AMDGPUReadPreloadRegisterIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_read_tidig_y {	// SDPatternOperator Intrinsic AMDGPUReadPreloadRegisterIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_read_tidig_z {	// SDPatternOperator Intrinsic AMDGPUReadPreloadRegisterIntrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_recipsqrt_clamped {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_recipsqrt_ieee {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_r600_store_stream_output {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "r600";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_read_register {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.read_register";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_readcyclecounter {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_returnaddress {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_rint {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_round {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_efpc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_efpc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_etnd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tx_nesting_depth";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_lcbb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_lcbb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_ntstg {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_ptr64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_ppa_txassist {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tx_assist";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_sfpc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_sfpc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_tabort {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoReturn, Throws, IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_tbegin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoDuplicate, IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_tbegin_nofloat {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoDuplicate, IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_tbeginc {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoDuplicate, IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_tdc {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyfloat_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_tend {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_tend";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vaccb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vaccb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vacccq {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vacccq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vaccf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vaccf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vaccg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vaccg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vacch {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vacch";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vaccq {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vaccq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vacq {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vacq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vaq {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vaq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vavgb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vavgb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vavgf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vavgf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vavgg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vavgg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vavgh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vavgh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vavglb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vavglb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vavglf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vavglf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vavglg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vavglg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vavglh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vavglh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vbperm {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vbperm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vceqbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vceqfs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vceqgs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vceqhs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vchbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vchfs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vchgs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vchhs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vchlbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vchlfs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vchlgs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vchlhs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vcksm {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vcksm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_verimb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_verimb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZQuaternaryIntBHFG::name = ?;
  string NAME = ?;
}
def int_s390_verimf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_verimf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZQuaternaryIntBHFG::name = ?;
  string NAME = ?;
}
def int_s390_verimg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_verimg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_verimh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_verimh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZQuaternaryIntBHFG::name = ?;
  string NAME = ?;
}
def int_s390_verllb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryInt
  string GCCBuiltinName = "__builtin_s390_verllb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_verllf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryInt
  string GCCBuiltinName = "__builtin_s390_verllf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_verllg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryInt
  string GCCBuiltinName = "__builtin_s390_verllg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_verllh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryInt
  string GCCBuiltinName = "__builtin_s390_verllh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_verllvb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_verllvb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_verllvf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_verllvf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_verllvg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_verllvg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_verllvh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_verllvh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vfaeb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryInt
  string GCCBuiltinName = "__builtin_s390_vfaeb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaebs {	// SDPatternOperator Intrinsic SystemZTernaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaef {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryInt
  string GCCBuiltinName = "__builtin_s390_vfaef";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaefs {	// SDPatternOperator Intrinsic SystemZTernaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaeh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryInt
  string GCCBuiltinName = "__builtin_s390_vfaeh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaehs {	// SDPatternOperator Intrinsic SystemZTernaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaezb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryInt
  string GCCBuiltinName = "__builtin_s390_vfaezb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaezbs {	// SDPatternOperator Intrinsic SystemZTernaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaezf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryInt
  string GCCBuiltinName = "__builtin_s390_vfaezf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaezfs {	// SDPatternOperator Intrinsic SystemZTernaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaezh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryInt
  string GCCBuiltinName = "__builtin_s390_vfaezh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfaezhs {	// SDPatternOperator Intrinsic SystemZTernaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfcedbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfcesbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfchdbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfchedbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfchesbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfchsbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeeb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfeeb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeebs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeef {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfeef";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeefs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeeh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfeeh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeehs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeezb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfeezb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeezbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeezf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfeezf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeezfs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeezh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfeezh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeezhs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeneb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfeneb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenebs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenef {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfenef";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenefs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfeneh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfeneh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenehs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenezb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfenezb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenezbs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenezf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfenezf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenezfs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenezh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vfenezh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfenezhs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC SystemZBinaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfidb {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfisb {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfmaxdb {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfmaxsb {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfmindb {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vfminsb {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vftcidb {	// SDPatternOperator Intrinsic SystemZBinaryConvIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vftcisb {	// SDPatternOperator Intrinsic SystemZBinaryConvIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vgfmab {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vgfmab";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZTernaryExtBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vgfmaf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vgfmaf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZTernaryExtBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vgfmag {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vgfmag";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vgfmah {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vgfmah";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZTernaryExtBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vgfmb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vgfmb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryExtBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vgfmf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vgfmf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryExtBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vgfmg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vgfmg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vgfmh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vgfmh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryExtBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vistrb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv SystemZUnary
  string GCCBuiltinName = "__builtin_s390_vistrb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vistrbs {	// SDPatternOperator Intrinsic SystemZUnaryConvCC SystemZUnaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vistrf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv SystemZUnary
  string GCCBuiltinName = "__builtin_s390_vistrf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vistrfs {	// SDPatternOperator Intrinsic SystemZUnaryConvCC SystemZUnaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vistrh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv SystemZUnary
  string GCCBuiltinName = "__builtin_s390_vistrh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vistrhs {	// SDPatternOperator Intrinsic SystemZUnaryConvCC SystemZUnaryCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vlbb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_vlbb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vll {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_vll";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vlrl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_vlrl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmaeb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmaeb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmaef {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmaef";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmaeh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmaeh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmahb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vmahb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmahf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vmahf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmahh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vmahh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmaleb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmaleb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmalef {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmalef";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmaleh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmaleh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmalhb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vmalhb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmalhf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vmalhf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmalhh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vmalhh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmalob {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmalob";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmalof {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmalof";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmaloh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmaloh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmaob {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmaob";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmaof {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmaof";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmaoh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv
  string GCCBuiltinName = "__builtin_s390_vmaoh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmeb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmeb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmef {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmef";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmeh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmeh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmhb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vmhb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmhf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vmhf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmhh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vmhh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmleb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmleb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmlef {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmlef";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmleh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmleh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmlhb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vmlhb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmlhf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vmlhf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmlhh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vmlhh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmlob {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmlob";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmlof {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmlof";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmloh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmloh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmob {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmob";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmof {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmof";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmoh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vmoh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vmslg {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_vmslg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpdi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_vpdi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vperm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_vperm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpklsf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vpklsf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpklsfs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpklsg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vpklsg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpklsgs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpklsh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vpklsh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpklshs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpksf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vpksf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpksfs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpksg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vpksg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpksgs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpksh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vpksh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vpkshs {	// SDPatternOperator Intrinsic SystemZBinaryConvCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsbcbiq {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vsbcbiq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsbiq {	// GCCBuiltin SDPatternOperator Intrinsic SystemZTernaryConv SystemZTernary
  string GCCBuiltinName = "__builtin_s390_vsbiq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vscbib {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vscbib";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vscbif {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vscbif";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vscbig {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vscbig";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vscbih {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vscbih";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string SystemZBinaryBHFG::name = ?;
  string NAME = ?;
}
def int_s390_vscbiq {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vscbiq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsl {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vsl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vslb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vslb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsldb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_vsldb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsq {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vsq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsra {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vsra";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsrab {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vsrab";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsrl {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vsrl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsrlb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv SystemZBinary
  string GCCBuiltinName = "__builtin_s390_vsrlb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_vstl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrcb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_vstrcb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrcbs {	// SDPatternOperator Intrinsic SystemZQuaternaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrcf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_vstrcf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrcfs {	// SDPatternOperator Intrinsic SystemZQuaternaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrch {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_vstrch";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrchs {	// SDPatternOperator Intrinsic SystemZQuaternaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrczb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_vstrczb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrczbs {	// SDPatternOperator Intrinsic SystemZQuaternaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrczf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_vstrczf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrczfs {	// SDPatternOperator Intrinsic SystemZQuaternaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrczh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZQuaternaryInt
  string GCCBuiltinName = "__builtin_s390_vstrczh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrczhs {	// SDPatternOperator Intrinsic SystemZQuaternaryIntCC
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vstrl {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_s390_vstrl";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly, IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsumb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vsumb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsumgf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vsumgf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsumgh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vsumgh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsumh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vsumh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsumqf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vsumqf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vsumqg {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vsumqg";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vtm {	// GCCBuiltin SDPatternOperator Intrinsic SystemZBinaryConv
  string GCCBuiltinName = "__builtin_s390_vtm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vuphb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vuphb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vuphf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vuphf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vuphh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vuphh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vuplb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vuplb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vuplf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vuplf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vuplhb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vuplhb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vuplhf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vuplhf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vuplhh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vuplhh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vuplhw {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vuplhw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vupllb {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vupllb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vupllf {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vupllf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_s390_vupllh {	// GCCBuiltin SDPatternOperator Intrinsic SystemZUnaryConv
  string GCCBuiltinName = "__builtin_s390_vupllh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "s390";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_sadd_with_overflow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_setjmp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_sideeffect {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrInaccessibleMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_siglongjmp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoReturn];
  bit isTarget = 0;
  string NAME = ?;
}
def int_sigsetjmp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_sin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_smul_with_overflow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_sqrt {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ssa_copy {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_any_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, anonymous_16];
  bit isTarget = 0;
  string NAME = ?;
}
def int_ssub_with_overflow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_stackguard {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_stackprotector {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptrptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_stackrestore {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_stack_restore";
  string NAME = ?;
}
def int_stacksave {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_stack_save";
  string NAME = ?;
}
def int_thread_pointer {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_thread_pointer";
  string NAME = ?;
}
def int_trap {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoReturn];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_trap";
  string NAME = ?;
}
def int_trunc {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyfloat_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_type_checked_load {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_ptr_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_type_test {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_i1_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_metadata_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_uadd_with_overflow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_umul_with_overflow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_usub_with_overflow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [llvm_anyint_ty, llvm_i1_ty];
  list<LLVMType> ParamTypes = [anonymous_6, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, IntrSpeculatable];
  bit isTarget = 0;
  string NAME = ?;
}
def int_vacopy {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.va_copy";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_vaend {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.va_end";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_var_annotation {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.var.annotation";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_vastart {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.va_start";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_wasm_current_memory {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "wasm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_wasm_get_ehselector {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "wasm";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrHasSideEffects];
  bit isTarget = 0;
  string NAME = ?;
}
def int_wasm_get_exception {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "wasm";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrHasSideEffects];
  bit isTarget = 0;
  string NAME = ?;
}
def int_wasm_grow_memory {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "wasm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [anonymous_6];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_wasm_mem_grow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "wasm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, anonymous_6];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_wasm_mem_size {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "wasm";
  list<LLVMType> RetTypes = [llvm_anyint_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_wasm_rethrow {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "wasm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [Throws, IntrNoReturn];
  bit isTarget = 0;
  string NAME = ?;
}
def int_wasm_throw {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "wasm";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [Throws, IntrNoReturn];
  bit isTarget = 0;
  string NAME = ?;
}
def int_write_register {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "llvm.write_register";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_metadata_ty, llvm_anyint_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pavgusb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pavgusb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pf2id {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pf2id";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfacc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfadd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfcmpeq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfcmpeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfcmpge {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfcmpge";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfcmpgt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfcmpgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfmax {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfmax";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfmin {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfmin";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfmul {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfmul";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfrcp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfrcp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfrcpit1 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfrcpit1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfrcpit2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfrcpit2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfrsqit1 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfrsqit1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfrsqrt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfrsqrt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfsub {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfsub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pfsubr {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfsubr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pi2fd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pi2fd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnow_pmulhrw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhrw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnowa_pf2iw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pf2iw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnowa_pfnacc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfnacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnowa_pfpnacc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pfpnacc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnowa_pi2fw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pi2fw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_3dnowa_pswapd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_addcarry_u32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addcarry_u32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_addcarry_u64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addcarry_u64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_addcarryx_u32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addcarryx_u32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_addcarryx_u64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addcarryx_u64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesdec {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesdec128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesdec_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesdec256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesdec_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesdec512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesdeclast {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesdeclast128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesdeclast_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesdeclast256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesdeclast_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesdeclast512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesenc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesenc128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesenc_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesenc256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesenc_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesenc512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesenclast {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesenclast128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesenclast_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesenclast256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesenclast_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesenclast512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aesimc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aesimc128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_aesni_aeskeygenassist {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_aeskeygenassist128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_d_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherd_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_d_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherd_d256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_d_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherd_pd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_d_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherd_pd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_d_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherd_ps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_d_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherd_ps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_d_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherd_q";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_d_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherd_q256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_q_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherq_d";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_q_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherq_d256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_q_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherq_pd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_q_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherq_pd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_q_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherq_ps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_q_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherq_ps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_q_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherq_q";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_gather_q_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherq_q256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_maskload_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskloadd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_maskload_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskloadd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_maskload_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskloadq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_maskload_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskloadq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_maskstore_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskstored";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_maskstore_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskstored256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_maskstore_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskstoreq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_maskstore_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskstoreq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_mpsadbw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_mpsadbw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_packssdw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packssdw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_packsswb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packsswb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_packusdw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packusdw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_packuswb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packuswb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_padds_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddsb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_padds_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddsw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_paddus_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddusb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_paddus_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddusw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pblendvb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pblendvb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_permd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarsi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_permps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarsf256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_phadd_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phaddd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_phadd_sw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phaddsw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_phadd_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phaddw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_phsub_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phsubd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_phsub_sw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phsubsw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_phsub_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phsubw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pmadd_ub_sw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaddubsw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pmadd_wd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaddwd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pmovmskb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovmskb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pmul_hr_sw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhrsw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pmulh_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pmulhu_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhuw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psad_bw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psadbw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pshuf_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pshufb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psign_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psignb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psign_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psignd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psign_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psignw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psll_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pslld256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psll_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psll_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pslli_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pslldi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pslli_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllqi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_pslli_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllwi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psllv_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllv4si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psllv_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllv8si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psllv_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllv2di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psllv_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllv4di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psra_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrad256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psra_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrai_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psradi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrai_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrawi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrav_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrav4si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrav_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrav8si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrl_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrld256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrl_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrl_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrli_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrldi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrli_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlqi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrli_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlwi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrlv_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlv4si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrlv_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlv8si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrlv_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlv2di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psrlv_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlv4di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psubs_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubsb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psubs_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubsw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psubus_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubusb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx2_psubus_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubusw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_broadcastmb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_broadcastmb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_broadcastmb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_broadcastmb256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_broadcastmb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_broadcastmb512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_broadcastmw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_broadcastmw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_broadcastmw_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_broadcastmw256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_broadcastmw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_broadcastmw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvtsi2sd64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtsi2sd64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvtsi2ss32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtsi2ss32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvtsi2ss64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtsi2ss64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvttsd2si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvttsd2si32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvttsd2si64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvttsd2si64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvttsd2usi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvttsd2usi32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvttsd2usi64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvttsd2usi64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvttss2si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvttss2si32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvttss2si64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvttss2si64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvttss2usi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvttss2usi32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvttss2usi64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvttss2usi64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvtusi2ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtusi2ss32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvtusi642sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtusi2sd64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_cvtusi642ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtusi2ss64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_exp2_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_exp2pd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_exp2_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_exp2ps_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3div2_df {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3div2df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3div2_di {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3div2di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3div4_df {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3div4df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3div4_di {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3div4di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3div4_sf {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3div4sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3div4_si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3div4si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3div8_sf {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3div8sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3div8_si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3div8si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3siv2_df {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3siv2df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3siv2_di {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3siv2di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3siv4_df {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3siv4df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3siv4_di {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3siv4di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3siv4_sf {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3siv4sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3siv4_si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3siv4si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3siv8_sf {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3siv8sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather3siv8_si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gather3siv8si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather_dpd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gathersiv8df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather_dpi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gathersiv16si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather_dpq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gathersiv8di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather_dps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gathersiv16sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather_qpd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherdiv8df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather_qpi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherdiv16si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather_qpq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherdiv8di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gather_qps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherdiv16sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gatherpf_dpd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherpfdpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gatherpf_dps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherpfdps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i16_ty, llvm_v16i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gatherpf_qpd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherpfqpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_gatherpf_qps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_gatherpfqps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmadd_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmadd_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmadd_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmadd_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmadd_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmadd_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmadd_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsd3_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmadd_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddss3_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmaddsub_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmaddsub_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmaddsub_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmaddsub_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmaddsub_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmaddsub_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsub_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubpd128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsub_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubpd256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsub_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubpd512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsub_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubps128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsub_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubps256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsub_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubps512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsub_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubsd3_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsub_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubss3_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsubadd_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubaddpd128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsubadd_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubaddpd256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsubadd_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubaddpd512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsubadd_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubaddps128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsubadd_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubaddps256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfmsubadd_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmsubaddps512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfnmsub_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubpd128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfnmsub_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubpd256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfnmsub_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubpd512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfnmsub_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubps128_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfnmsub_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubps256_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfnmsub_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubps512_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfnmsub_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubsd3_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask3_vfnmsub_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubss3_mask3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_add_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_add_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_add_sd_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addsd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_add_ss_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cmp_pd_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i1_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cmp_pd_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i1_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cmp_pd_512 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i1_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cmp_ps_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i1_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cmp_ps_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i1_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cmp_ps_512 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i1_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cmp_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cmpsd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cmp_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cmpss_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_b_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressqi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_b_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressqi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_b_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressqi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compresssi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compresssi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compresssi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressdf128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressdf256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressdf512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compresssf128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compresssf256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compresssf512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressdi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressdi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressdi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_b_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoreqi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_b_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoreqi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_b_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoreqi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoresi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoresi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoresi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoredf128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoredf256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoredf512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoresf128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoresf256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoresf512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16f32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoredi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoredi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstoredi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstorehi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstorehi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_store_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compressstorehi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compresshi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compresshi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_compress_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_compresshi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_conflict_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpconflictsi_128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_conflict_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpconflictsi_256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_conflict_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpconflictsi_512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_conflict_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpconflictdi_128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_conflict_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpconflictdi_256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_conflict_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpconflictdi_512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtdq2ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtdq2ps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2dq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2dq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2dq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2dq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2ps_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2ps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2qq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2qq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2qq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2qq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2qq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2qq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2udq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2udq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2udq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2udq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2udq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2udq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2uqq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2uqq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2uqq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2uqq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtpd2uqq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2uqq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2dq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2dq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2dq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2dq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2dq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2dq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2pd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2qq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2qq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2qq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2qq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2qq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2qq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2udq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2udq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2udq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2udq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2udq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2udq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2uqq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2uqq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2uqq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2uqq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtps2uqq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2uqq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtqq2pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtqq2pd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtqq2ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtqq2ps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtqq2ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtqq2ps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtqq2ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtqq2ps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtsd2ss_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtsd2ss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v2f64_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtss2sd_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtss2sd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v4f32_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2dq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2dq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2dq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2dq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2qq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2qq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2qq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2qq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2qq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2qq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2udq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2udq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2udq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2udq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2udq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2udq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2uqq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2uqq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2uqq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2uqq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttpd2uqq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2uqq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2dq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2dq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2qq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2qq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2qq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2qq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2qq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2qq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2udq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2udq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2udq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2udq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2udq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2udq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2uqq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2uqq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2uqq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2uqq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvttps2uqq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2uqq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtudq2ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtudq2ps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtuqq2pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtuqq2pd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtuqq2ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtuqq2ps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtuqq2ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtuqq2ps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_cvtuqq2ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtuqq2ps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_dbpsadbw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_dbpsadbw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_dbpsadbw_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_dbpsadbw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_dbpsadbw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_dbpsadbw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_i32_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_div_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_divpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_div_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_divps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_div_sd_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_divsd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_div_ss_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_divss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_b_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandqi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_b_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandqi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_b_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandqi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandsi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandsi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandsi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_b_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadqi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_b_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadqi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_b_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadqi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadsi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadsi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadsi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloaddf128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloaddf256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloaddf512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadsf128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadsf256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadsf512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16f32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloaddi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloaddi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloaddi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadhi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadhi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_load_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandloadhi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expanddf128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expanddf256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expanddf512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandsf128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandsf256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandsf512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expanddi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expanddi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expanddi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandhi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandhi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_expand_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_expandhi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fixupimm_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2i64_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fixupimm_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4i64_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fixupimm_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8i64_ty, llvm_i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fixupimm_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fixupimm_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fixupimm_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fixupimm_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmsd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2i64_ty, llvm_i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fixupimm_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmss_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fpclass_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fpclasspd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fpclass_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fpclasspd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fpclass_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fpclasspd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fpclass_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fpclassps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fpclass_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fpclassps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fpclass_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fpclassps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fpclass_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fpclasssd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_fpclass_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fpclassss_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getexp_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getexppd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getexp_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getexppd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getexp_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getexppd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getexp_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getexpps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getexp_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getexpps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getexp_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getexpps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getexp_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getexpsd128_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getexp_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getexpss128_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getmant_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getmantpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getmant_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getmantpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_i32_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getmant_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getmantpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_i32_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getmant_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getmantps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getmant_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getmantps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_i32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getmant_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getmantps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getmant_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getmantsd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_getmant_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_getmantss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_max_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_max_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_max_sd_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxsd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_max_ss_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_min_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_min_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_min_sd_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minsd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_min_ss_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_mul_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_mulpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_mul_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_mulps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_mul_sd_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_mulsd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_mul_ss_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_mulss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_padds_b_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_padds_b_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_padds_b_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddsb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_padds_w_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_padds_w_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_padds_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddsw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_paddus_b_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_paddus_b_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_paddus_b_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddusb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_paddus_w_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_paddus_w_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_paddus_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddusw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_db_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_db_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_db_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_db_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdb128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_db_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdb256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_db_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdb512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_dw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_dw_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_dw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_dw_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdw128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_dw_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdw256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_dw_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovdw512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qb_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqb128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qb_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqb256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qb_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqb512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qd_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qd_512 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qd_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqd128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qd_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqd256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qd_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqd512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qw_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qw_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqw128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qw_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqw256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_qw_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovqw512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_wb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovwb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_wb_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_wb_512 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_wb_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovwb128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_wb_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovwb256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmov_wb_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovwb512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_db_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_db_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_db_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_db_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdb128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_db_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdb256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_db_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdb512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_dw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_dw_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_dw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_dw_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdw128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_dw_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdw256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_dw_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsdw512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qb_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqb128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qb_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqb256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qb_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqb512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qd_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqd128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qd_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqd256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qd_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqd512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qw_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qw_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqw128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qw_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqw256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_qw_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovsqw512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_wb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovswb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_wb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovswb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_wb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovswb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_wb_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovswb128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_wb_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovswb256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovs_wb_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovswb512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_db_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_db_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_db_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_db_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdb128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_db_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdb256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_db_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdb512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_dw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_dw_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_dw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_dw_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdw128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_dw_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdw256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_dw_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusdw512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qb_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqb128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qb_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqb256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qb_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqb512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qd_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqd128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qd_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqd256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qd_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqd512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qw_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qw_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqw128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qw_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqw256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_qw_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovusqw512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_wb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovuswb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_wb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovuswb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_wb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovuswb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_wb_mem_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovuswb128mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_wb_mem_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovuswb256mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmovus_wb_mem_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovuswb512mem_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmultishift_qb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmultishiftqb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmultishift_qb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmultishiftqb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pmultishift_qb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmultishiftqb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prol_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prold128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prol_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prold256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prol_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prold512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prol_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prolq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prol_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prolq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_i32_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prol_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prolq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prolv_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prolvd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prolv_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prolvd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prolv_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prolvd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prolv_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prolvq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prolv_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prolvq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prolv_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prolvq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pror_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prord128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pror_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prord256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pror_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prord512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pror_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prorq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pror_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prorq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_i32_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_pror_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prorq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prorv_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prorvd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prorv_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prorvd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prorv_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prorvd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prorv_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prorvq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prorv_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prorvq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_prorv_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_prorvq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubs_b_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubs_b_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubs_b_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubsb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubs_w_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubs_w_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubs_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubsw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubus_b_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubus_b_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubus_b_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubusb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubus_w_128 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubus_w_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_psubus_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubusw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_range_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rangepd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_range_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rangepd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i32_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_range_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rangepd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i32_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_range_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rangeps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_range_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rangeps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_range_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rangeps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_range_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rangesd128_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_range_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rangess128_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_reduce_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_reducepd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_reduce_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_reducepd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_i32_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_reduce_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_reducepd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_i32_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_reduce_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_reduceps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_reduce_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_reduceps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_i32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_reduce_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_reduceps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_reduce_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_reducesd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_reduce_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_reducess_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_rndscale_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rndscalepd_128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_rndscale_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rndscalepd_256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_i32_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_rndscale_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rndscalepd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_i32_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_rndscale_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rndscaleps_128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_rndscale_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rndscaleps_256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_i32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_rndscale_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rndscaleps_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_rndscale_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rndscalesd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_rndscale_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rndscaless_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_scalef_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scalefpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_scalef_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scalefpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_scalef_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scalefpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_scalef_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scalefps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_scalef_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scalefps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_scalef_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scalefps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_scalef_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scalefsd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_scalef_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scalefss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sqrt_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sqrt_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sqrt_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sqrt_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sqrt_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sqrt_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sqrt_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtsd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sqrt_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sub_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_subpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sub_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_subps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sub_sd_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_subsd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_sub_ss_round {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_subss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vcvtph2ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtph2ps_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vcvtph2ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtph2ps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vcvtph2ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtph2ps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vcvtps2ph_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtps2ph_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vcvtps2ph_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtps2ph256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vcvtps2ph_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtps2ph512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_i32_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmadd_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmadd_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmadd_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmadd_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmadd_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmadd_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmadd_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsd3_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmadd_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddss3_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmaddsub_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmaddsub_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmaddsub_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmaddsub_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmaddsub_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfmaddsub_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmadd_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmaddpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmadd_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmaddpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmadd_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmaddpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmadd_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmaddps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmadd_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmaddps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmadd_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmaddps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmsub_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmsub_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmsub_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmsub_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmsub_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vfnmsub_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfnmsubps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpbusd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpbusd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpbusd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpbusds_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusds128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpbusds_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusds256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpbusds_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusds512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpwssd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpwssd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpwssd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpwssds_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssds128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpwssds_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssds256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpdpwssds_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssds512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2vard128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2vard256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2vard512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_hi_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varhi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_hi_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varhi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_hi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varhi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2i64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4i64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i64_ty, llvm_v8f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16i32_ty, llvm_v16f32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_qi_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varqi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_qi_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varqi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermi2var_qi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermi2varqi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2vard128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2vard256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2vard512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_hi_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varhi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_hi_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varhi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_hi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varhi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varpd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varpd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varpd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_qi_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varqi128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_qi_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varqi256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpermt2var_qi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varqi512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpmadd52h_uq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52huq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpmadd52h_uq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52huq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpmadd52h_uq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52huq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpmadd52l_uq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52luq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpmadd52l_uq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52luq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpmadd52l_uq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52luq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshld_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshld_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshld_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshld_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshld_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_i32_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshld_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshld_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshld_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_i32_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshld_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshldv_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshldv_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshldv_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshldv_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshldv_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshldv_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshldv_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshldv_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshldv_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrd_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrd_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrd_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrd_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrd_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_i32_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrd_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrd_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrd_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_i32_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrd_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrdv_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrdv_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrdv_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrdv_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvq128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrdv_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvq256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrdv_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvq512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrdv_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvw128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrdv_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvw256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshrdv_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvw512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshufbitqmb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshufbitqmb128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshufbitqmb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshufbitqmb256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_mask_vpshufbitqmb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshufbitqmb512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_fixupimm_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmpd128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2i64_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_fixupimm_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmpd256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4i64_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_fixupimm_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmpd512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8i64_ty, llvm_i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_fixupimm_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmps128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_fixupimm_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmps256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_fixupimm_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmps512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16i32_ty, llvm_i32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_fixupimm_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmsd_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2i64_ty, llvm_i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_fixupimm_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fixupimmss_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmadd_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmadd_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmadd_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmadd_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmadd_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmadd_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmadd_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsd3_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmadd_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddss3_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmaddsub_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmaddsub_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmaddsub_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmaddsub_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmaddsub_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vfmaddsub_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpbusd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusd128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpbusd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusd256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpbusd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusd512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpbusds_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusds128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpbusds_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusds256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpbusds_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpbusds512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpwssd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssd128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpwssd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssd256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpwssd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssd512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpwssds_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssds128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpwssds_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssds256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpdpwssds_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpdpwssds512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2vard128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2vard256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2vard512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_hi_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varhi128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_hi_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varhi256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_hi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varhi512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varpd128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varpd256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varpd512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varps128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varps256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varps512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varq128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varq256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varq512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_qi_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varqi128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_qi_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varqi256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpermt2var_qi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermt2varqi512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpmadd52h_uq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52huq128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpmadd52h_uq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52huq256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpmadd52h_uq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52huq512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpmadd52l_uq_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52luq128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpmadd52l_uq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52luq256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpmadd52l_uq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadd52luq512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshldv_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvd128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshldv_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvd256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshldv_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvd512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshldv_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvq128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshldv_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvq256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshldv_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvq512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshldv_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvw128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshldv_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvw256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshldv_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshldvw512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshrdv_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvd128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshrdv_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvd256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshrdv_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvd512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshrdv_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvq128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshrdv_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvq256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshrdv_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvq512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshrdv_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvw128_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshrdv_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvw256_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_maskz_vpshrdv_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshrdvw512_maskz";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_packssdw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packssdw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_packsswb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packsswb512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_packusdw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packusdw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_packuswb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packuswb512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_df_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvardf256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_df_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvardf512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_di_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvardi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_di_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvardi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_hi_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarhi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_hi_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarhi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_hi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarhi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_qi_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarqi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_qi_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarqi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_qi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarqi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_sf_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarsf512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_permvar_si_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_permvarsi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pmaddubs_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaddubsw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pmaddw_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaddwd512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pmul_hr_sw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhrsw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pmulh_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pmulhu_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhuw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psad_bw_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psadbw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pshuf_b_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pshufb512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psll_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pslld512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psll_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllq512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psll_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pslli_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pslldi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pslli_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllqi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pslli_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllwi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psllv_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllv16si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psllv_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllv8di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psllv_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllv8hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psllv_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllv16hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psllv_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllv32hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psra_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrad512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psra_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraq128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psra_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psra_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraq512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psra_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrai_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psradi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrai_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraqi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrai_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraqi256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrai_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraqi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrai_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrawi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrav_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrav16si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrav_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psravq128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrav_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psravq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrav_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrav8di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrav_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrav8hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrav_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrav16hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrav_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrav32hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrl_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrld512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrl_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlq512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrl_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlw512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrli_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrldi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrli_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlqi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrli_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlwi512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrlv_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlv16si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrlv_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlv8di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrlv_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlv8hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrlv_w_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlv16hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i16_ty, llvm_v16i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_psrlv_w_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlv32hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i16_ty];
  list<LLVMType> ParamTypes = [llvm_v32i16_ty, llvm_v32i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pternlog_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pternlogd128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pternlog_d_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pternlogd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pternlog_d_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pternlogd512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pternlog_q_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pternlogq128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pternlog_q_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pternlogq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_pternlog_q_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pternlogq512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp14_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp14pd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp14_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp14pd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp14_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp14pd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp14_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp14ps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp14_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp14ps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp14_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp14ps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp14_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp14sd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp14_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp14ss_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp28_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp28pd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp28_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp28ps_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp28_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp28sd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rcp28_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcp28ss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt14_pd_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt14pd128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt14_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt14pd256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt14_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt14pd512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt14_ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt14ps128_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt14_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt14ps256_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt14_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt14ps512_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt14_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt14sd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt14_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt14ss_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt28_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt28pd_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt28_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt28ps_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt28_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt28sd_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_rsqrt28_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrt28ss_round_mask";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatter_dpd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv8df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v8i32_ty, llvm_v8f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatter_dpi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv16si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i16_ty, llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatter_dpq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv8di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v8i32_ty, llvm_v8i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatter_dps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv16sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i16_ty, llvm_v16i32_ty, llvm_v16f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatter_qpd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv8df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v8i64_ty, llvm_v8f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatter_qpi_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv16si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v8i64_ty, llvm_v8i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatter_qpq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv8di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatter_qps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv16sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v8i64_ty, llvm_v8f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterdiv2_df {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv2df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v2i64_ty, llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterdiv2_di {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv2di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterdiv4_df {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv4df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i64_ty, llvm_v4f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterdiv4_di {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv4di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterdiv4_sf {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv4sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v2i64_ty, llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterdiv4_si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv4si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v2i64_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterdiv8_sf {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv8sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i64_ty, llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterdiv8_si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterdiv8si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i64_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterpf_dpd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterpfdpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterpf_dps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterpfdps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i16_ty, llvm_v16i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterpf_qpd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterpfqpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scatterpf_qps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scatterpfqps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scattersiv2_df {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv2df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i32_ty, llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scattersiv2_di {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv2di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i32_ty, llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scattersiv4_df {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv4df";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i32_ty, llvm_v4f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scattersiv4_di {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv4di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i32_ty, llvm_v4i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scattersiv4_sf {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv4sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i32_ty, llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scattersiv4_si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv4si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scattersiv8_sf {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv8sf";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v8i32_ty, llvm_v8f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_scattersiv8_si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_scattersiv8si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i8_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcomi_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcomisd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcomi_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcomiss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcvtsd2si32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtsd2si32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcvtsd2si64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtsd2si64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcvtsd2usi32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtsd2usi32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcvtsd2usi64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtsd2usi64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcvtss2si32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtss2si32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcvtss2si64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtss2si64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcvtss2usi32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtss2usi32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vcvtss2usi64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtss2usi64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vpermilvar_pd_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermilvarpd512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f64_ty];
  list<LLVMType> ParamTypes = [llvm_v8f64_ty, llvm_v8i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx512_vpermilvar_ps_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermilvarps512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16f32_ty];
  list<LLVMType> ParamTypes = [llvm_v16f32_ty, llvm_v16i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_addsub_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addsubpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_addsub_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addsubps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_blendv_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_blendvpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_blendv_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_blendvps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_cmp_pd_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_cmp_ps_256 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_cvt_pd2_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2ps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_cvt_pd2dq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2dq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_cvt_ps2dq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2dq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_cvtt_pd2dq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2dq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_cvtt_ps2dq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2dq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_dp_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_dpps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_hadd_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_haddpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_hadd_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_haddps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_hsub_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_hsubpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_hsub_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_hsubps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_ldu_dq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_lddqu256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_maskload_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskloadpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_maskload_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskloadpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_maskload_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskloadps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_maskload_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskloadps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem, IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_maskstore_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskstorepd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v2i64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_maskstore_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskstorepd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_maskstore_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskstoreps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v4i32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_maskstore_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskstoreps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_v8i32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_max_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_max_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_min_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_min_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_movmsk_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_movmskpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_movmsk_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_movmskps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_ptestc_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ptestc256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_ptestnzc_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ptestnzc256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_ptestz_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ptestz256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_rcp_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcpps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_round_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_roundpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_round_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_roundps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_rsqrt_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrtps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_sqrt_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_sqrt_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vpermilvar_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermilvarpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vpermilvar_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermilvarpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vpermilvar_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermilvarps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vpermilvar_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermilvarps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestc_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestcpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestc_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestcpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestc_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestcps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestc_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestcps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestnzc_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestnzcpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestnzc_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestnzcpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestnzc_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestnzcps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestnzc_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestnzcps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestz_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestzpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestz_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestzpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestz_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestzps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vtestz_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vtestzps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vzeroall {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vzeroall";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_avx_vzeroupper {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vzeroupper";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_bmi_bextr_32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_bextr_u32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_bmi_bextr_64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_bextr_u64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_bmi_bzhi_32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_bzhi_si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_bmi_bzhi_64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_bzhi_di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_bmi_pdep_32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pdep_si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_bmi_pdep_64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pdep_di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_bmi_pext_32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pext_si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_bmi_pext_64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pext_di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_cldemote {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cldemote";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_clflushopt {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_clflushopt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_clrssbsy {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_clrssbsy";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_clwb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_clwb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_clzero {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_clzero";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_directstore32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_directstore_u32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_directstore64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_directstore_u64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_flags_read_u32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_readeflags_u32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_flags_read_u64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_readeflags_u64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_flags_write_u32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_writeeflags_u32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_flags_write_u64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_writeeflags_u64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma4_vfmadd_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma4_vfmadd_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmadd_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmadd_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmadd_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmadd_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmadd_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsd3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmadd_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddss3";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmaddsub_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmaddsub_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmaddsub_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fma_vfmaddsub_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfmaddsubps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fxrstor {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fxrstor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fxrstor64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fxrstor64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fxsave {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fxsave";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_fxsave64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_fxsave64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_incsspd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_incsspd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_incsspq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_incsspq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_int {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_llwpcb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_llwpcb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_lwpins32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_lwpins32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_lwpins64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_lwpins64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_lwpval32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_lwpval32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_lwpval64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_lwpval64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_emms {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_emms";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_femms {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_femms";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_maskmovq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskmovq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_movnt_dq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_movntq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptrx86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_packssdw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packssdw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_packsswb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packsswb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_packuswb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packuswb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_padd_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_padd_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_padd_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_padd_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_padds_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_padds_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_paddus_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddusb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_paddus_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddusw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_palignr_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_palignr";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pand {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pand";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pandn {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pandn";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pavg_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pavgb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pavg_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pavgw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pcmpeq_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpeqb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pcmpeq_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpeqd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pcmpeq_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpeqw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pcmpgt_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpgtb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pcmpgt_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpgtd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pcmpgt_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpgtw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pextr_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vec_ext_v4hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pinsr_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vec_set_v4hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pmadd_wd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaddwd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pmaxs_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaxsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pmaxu_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaxub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pmins_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pminsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pminu_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pminub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pmovmskb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovmskb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pmulh_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pmulhu_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pmull_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmullw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pmulu_dq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmuludq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_por {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_por";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psad_bw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psadbw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psll_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pslld";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psll_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psll_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pslli_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pslldi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pslli_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pslli_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllwi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psra_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrad";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psra_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psrai_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psradi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psrai_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrawi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psrl_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrld";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psrl_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psrl_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psrli_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrldi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psrli_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psrli_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlwi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psub_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psub_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psub_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psub_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psubs_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psubs_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psubus_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubusb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_psubus_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubusw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_punpckhbw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_punpckhbw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_punpckhdq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_punpckhdq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_punpckhwd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_punpckhwd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_punpcklbw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_punpcklbw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_punpckldq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_punpckldq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_punpcklwd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_punpcklwd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mmx_pxor {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pxor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_monitorx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_monitorx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_movdir64b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_movdir64b";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_mwaitx {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_mwaitx";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_pclmulqdq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pclmulqdq128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_pclmulqdq_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pclmulqdq256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_pclmulqdq_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pclmulqdq512";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ptwrite32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ptwrite32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ptwrite64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ptwrite64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdfsbase_32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdfsbase32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdfsbase_64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdfsbase64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdgsbase_32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdgsbase32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdgsbase_64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdgsbase64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdpid {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdpid";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdpkru {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdpkru";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdpmc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdpmc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdrand_16 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdrand_32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdrand_64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdseed_16 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i16_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdseed_32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdseed_64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdsspd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdsspd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdsspq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdsspq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdtsc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdtsc";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rdtscp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rdtscp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_rstorssp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rstorssp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_saveprevssp {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_saveprevssp";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_seh_ehguard {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_seh_ehregnode {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_seh_lsda {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_seh_recoverfp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_setssbsy {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_setssbsy";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sha1msg1 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sha1msg1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sha1msg2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sha1msg2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sha1nexte {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sha1nexte";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sha1rnds4 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sha1rnds4";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sha256msg1 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sha256msg1";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sha256msg2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sha256msg2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sha256rnds2 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sha256rnds2";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_slwpcb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_slwpcb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_clflush {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_clflush";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cmp_pd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cmp_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cmpsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_comieq_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comisdeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_comige_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comisdge";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_comigt_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comisdgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_comile_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comisdle";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_comilt_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comisdlt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_comineq_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comisdneq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvtpd2dq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2dq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvtpd2ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2ps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvtps2dq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2dq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvtsd2si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtsd2si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvtsd2si64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtsd2si64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvtsd2ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtsd2ss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvttpd2dq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2dq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvttps2dq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2dq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvttsd2si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttsd2si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_cvttsd2si64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttsd2si64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_lfence {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_lfence";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_maskmov_dqu {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maskmovdqu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_max_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_max_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_mfence {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_mfence";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_min_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_min_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_movmsk_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_movmskpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_packssdw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packssdw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_packsswb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packsswb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_packuswb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packuswb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_padds_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddsb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_padds_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddsw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_paddus_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddusb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_paddus_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_paddusw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_pause {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pause";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_pmadd_wd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaddwd128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_pmovmskb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmovmskb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_pmulh_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_pmulhu_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhuw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psad_bw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psadbw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psll_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pslld128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psll_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllq128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psll_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_pslli_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pslldi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_pslli_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllqi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_pslli_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psllwi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psra_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrad128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psra_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psraw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psrai_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psradi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psrai_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrawi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psrl_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrld128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psrl_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlq128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psrl_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psrli_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrldi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psrli_q {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlqi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psrli_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psrlwi128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psubs_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubsb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psubs_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubsw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psubus_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubusb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_psubus_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psubusw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_sqrt_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_sqrt_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_ucomieq_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomisdeq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_ucomige_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomisdge";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_ucomigt_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomisdgt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_ucomile_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomisdle";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_ucomilt_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomisdlt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse2_ucomineq_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomisdneq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse3_addsub_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addsubpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse3_addsub_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_addsubps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse3_hadd_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_haddpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse3_hadd_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_haddps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse3_hsub_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_hsubpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse3_hsub_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_hsubps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse3_ldu_dq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_lddqu";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse3_monitor {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_monitor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse3_mwait {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_mwait";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_blendvpd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_blendvpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_blendvps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_blendvps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_dppd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_dppd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_dpps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_dpps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_insertps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_insertps128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_mpsadbw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_mpsadbw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_packusdw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_packusdw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_pblendvb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pblendvb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_phminposuw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phminposuw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_ptestc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ptestc128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_ptestnzc {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ptestnzc128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_ptestz {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ptestz128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_round_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_roundpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_round_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_roundps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_round_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_roundsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse41_round_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_roundss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_crc32_32_16 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_crc32hi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_crc32_32_32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_crc32si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_crc32_32_8 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_crc32qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_crc32_64_64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_crc32di";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpestri128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpestri128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpestria128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpestria128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpestric128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpestric128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpestrio128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpestrio128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpestris128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpestris128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpestriz128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpestriz128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpestrm128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpestrm128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpistri128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpistri128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpistria128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpistria128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpistric128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpistric128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpistrio128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpistrio128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpistris128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpistris128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpistriz128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpistriz128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse42_pcmpistrm128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pcmpistrm128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse4a_extrq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_extrq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse4a_extrqi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_extrqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse4a_insertq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_insertq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse4a_insertqi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_insertqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cmp_ps {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cmp_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cmpss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_comieq_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comieq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_comige_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comige";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_comigt_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comigt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_comile_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comile";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_comilt_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comilt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_comineq_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_comineq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvtpd2pi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpd2pi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvtpi2pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpi2pd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvtpi2ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtpi2ps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvtps2pi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtps2pi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvtss2si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtss2si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvtss2si64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvtss2si64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvttpd2pi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttpd2pi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvttps2pi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttps2pi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvttss2si {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttss2si";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_cvttss2si64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_cvttss2si64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_ldmxcsr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_max_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_max_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_maxss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_min_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_min_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_minss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_movmsk_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_movmskps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_pshuf_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pshufw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_rcp_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcpps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_rcp_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rcpss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_rsqrt_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrtps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_rsqrt_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_rsqrtss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_sfence {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sfence";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_sqrt_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_sqrt_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_sqrtss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_stmxcsr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_ucomieq_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomieq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_ucomige_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomige";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_ucomigt_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomigt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_ucomile_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomile";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_ucomilt_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomilt";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_sse_ucomineq_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_ucomineq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_pabs_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pabsb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_pabs_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pabsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_pabs_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pabsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phadd_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phaddd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phadd_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phaddd128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phadd_sw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phaddsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phadd_sw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phaddsw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phadd_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phaddw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phadd_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phaddw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phsub_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phsubd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phsub_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phsubd128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phsub_sw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phsubsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phsub_sw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phsubsw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phsub_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phsubw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_phsub_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_phsubw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_pmadd_ub_sw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaddubsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_pmadd_ub_sw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmaddubsw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_pmul_hr_sw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhrsw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_pmul_hr_sw_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pmulhrsw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_pshuf_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pshufb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_pshuf_b_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_pshufb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_psign_b {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psignb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_psign_b_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psignb128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_psign_d {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psignd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_psign_d_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psignd128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_psign_w {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psignw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_x86mmx_ty];
  list<LLVMType> ParamTypes = [llvm_x86mmx_ty, llvm_x86mmx_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_ssse3_psign_w_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_psignw128";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_subborrow_u32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_subborrow_u32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_subborrow_u64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_subborrow_u64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i8_ty, llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [IntrArgMemOnly];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_tbm_bextri_u32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_bextri_u32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_tbm_bextri_u64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_bextri_u64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_tpause {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_tpause";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_umonitor {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_umonitor";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_umwait {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_umwait";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i8_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vcvtph2ps_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtph2ps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vcvtph2ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtph2ps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vcvtps2ph_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtps2ph";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vcvtps2ph_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vcvtps2ph256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vgf2p8affineinvqb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vgf2p8affineinvqb_v16qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vgf2p8affineinvqb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vgf2p8affineinvqb_v32qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vgf2p8affineinvqb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vgf2p8affineinvqb_v64qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vgf2p8affineqb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vgf2p8affineqb_v16qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vgf2p8affineqb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vgf2p8affineqb_v32qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vgf2p8affineqb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vgf2p8affineqb_v64qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vgf2p8mulb_128 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vgf2p8mulb_v16qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vgf2p8mulb_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vgf2p8mulb_v32qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v32i8_ty];
  list<LLVMType> ParamTypes = [llvm_v32i8_ty, llvm_v32i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_vgf2p8mulb_512 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vgf2p8mulb_v64qi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v64i8_ty];
  list<LLVMType> ParamTypes = [llvm_v64i8_ty, llvm_v64i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wbinvd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wbinvd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wbnoinvd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wbnoinvd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wrfsbase_32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wrfsbase32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wrfsbase_64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wrfsbase64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wrgsbase_32 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wrgsbase32";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wrgsbase_64 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wrgsbase64";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wrpkru {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wrpkru";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wrssd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wrssd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wrssq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wrssq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wrussd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wrussd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_wrussq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_wrussq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i64_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xabort {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_xabort";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xbegin {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_xbegin";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xend {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_xend";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xgetbv {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i64_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vfrcz_pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfrczpd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vfrcz_pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfrczpd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vfrcz_ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfrczps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vfrcz_ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfrczps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vfrcz_sd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfrczsd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vfrcz_ss {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vfrczss";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpcomb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpcomb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpcomd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpcomd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpcomq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpcomq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpcomub {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpcomub";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpcomud {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpcomud";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpcomuq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpcomuq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpcomuw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpcomuw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpcomw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpcomw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpermil2pd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermil2pd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2f64_ty];
  list<LLVMType> ParamTypes = [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpermil2pd_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermil2pd256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f64_ty];
  list<LLVMType> ParamTypes = [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpermil2ps {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermil2ps";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4f32_ty];
  list<LLVMType> ParamTypes = [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpermil2ps_256 {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpermil2ps256";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8f32_ty];
  list<LLVMType> ParamTypes = [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphaddbd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphaddbd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphaddbq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphaddbq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphaddbw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphaddbw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphadddq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphadddq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphaddubd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphaddubd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphaddubq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphaddubq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphaddubw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphaddubw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphaddudq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphaddudq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphadduwd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphadduwd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphadduwq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphadduwq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphaddwd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphaddwd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphaddwq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphaddwq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphsubbw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphsubbw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphsubdq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphsubdq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vphsubwd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vphsubwd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacsdd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacsdd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacsdqh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacsdqh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacsdql {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacsdql";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacssdd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacssdd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacssdqh {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacssdqh";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacssdql {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacssdql";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacsswd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacsswd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacssww {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacssww";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacswd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacswd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmacsww {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmacsww";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmadcsswd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadcsswd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpmadcswd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpmadcswd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem, Commutative];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpperm {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpperm";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vprotb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vprotb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vprotbi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vprotbi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vprotd {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vprotd";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vprotdi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vprotdi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vprotq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vprotq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vprotqi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vprotqi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vprotw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vprotw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vprotwi {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vprotwi";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpshab {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshab";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpshad {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshad";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpshaq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshaq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpshaw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshaw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpshlb {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshlb";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v16i8_ty];
  list<LLVMType> ParamTypes = [llvm_v16i8_ty, llvm_v16i8_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpshld {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshld";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v4i32_ty];
  list<LLVMType> ParamTypes = [llvm_v4i32_ty, llvm_v4i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpshlq {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshlq";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v2i64_ty];
  list<LLVMType> ParamTypes = [llvm_v2i64_ty, llvm_v2i64_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xop_vpshlw {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_vpshlw";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_v8i16_ty];
  list<LLVMType> ParamTypes = [llvm_v8i16_ty, llvm_v8i16_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xrstor {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xrstor64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xrstors {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xrstors64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xsave {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xsave64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xsavec {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xsavec64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xsaveopt {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xsaveopt64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xsaves {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xsaves64 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xsetbv {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_x86_xtest {	// GCCBuiltin SDPatternOperator Intrinsic
  string GCCBuiltinName = "__builtin_ia32_xtest";
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "x86";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_bitrev {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_bitrev";
  string NAME = ?;
}
def int_xcore_checkevent {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_chkct {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_clre {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_clrpt {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_clrsr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_crc32 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_crc8 {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty, llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_edu {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_eeu {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_endin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_freer {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_geted {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_getet {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_getid {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_getid";
  string NAME = ?;
}
def int_xcore_getps {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_getps";
  string NAME = ?;
}
def int_xcore_getr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_getst {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_anyptr_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_getts {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_in {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_inct {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_initcp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_initdp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_initlr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_initpc {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_initsp {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_inshr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_int {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_mjoin {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_msync {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_out {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_outct {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_outshr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_outt {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_peek {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_setc {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_setclk {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3, anonymous_0];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_setd {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_setev {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_setps {	// SDPatternOperator Intrinsic GCCBuiltin
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string GCCBuiltinName = "__builtin_setps";
  string NAME = ?;
}
def int_xcore_setpsc {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_setpt {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_setrdy {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3, anonymous_0];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_setsr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_settw {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_setv {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty, llvm_ptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_sext {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_ssync {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_syncr {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_testct {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_testwct {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_anyptr_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_waitevent {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_ptr_ty];
  list<LLVMType> ParamTypes = [];
  list<IntrinsicProperty> IntrProperties = [IntrReadMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xcore_zext {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "xcore";
  list<LLVMType> RetTypes = [llvm_i32_ty];
  list<LLVMType> ParamTypes = [llvm_i32_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [IntrNoMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xray_customevent {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_3, anonymous_2, IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def int_xray_typedevent {	// SDPatternOperator Intrinsic
  list<SDNodeProperty> Properties = [];
  string LLVMName = "";
  string TargetPrefix = "";
  list<LLVMType> RetTypes = [];
  list<LLVMType> ParamTypes = [llvm_i16_ty, llvm_ptr_ty, llvm_i32_ty];
  list<IntrinsicProperty> IntrProperties = [anonymous_0, anonymous_5, IntrWriteMem];
  bit isTarget = 0;
  string NAME = ?;
}
def interleave {
  string NAME = ?;
}
def intrinsic_void {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ISD::INTRINSIC_VOID";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_879;
  string NAME = ?;
}
def intrinsic_w_chain {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain];
  string Opcode = "ISD::INTRINSIC_W_CHAIN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_880;
  string NAME = ?;
}
def intrinsic_wo_chain {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::INTRINSIC_WO_CHAIN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_880;
  string NAME = ?;
}
def isVoid {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 111;
  string NAME = ?;
}
def ist {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMemOperand];
  string Opcode = "ISD::STORE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIStore;
  string NAME = ?;
}
def istore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (ist node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = 0;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def it_mask {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printThumbITMask";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = it_mask_asmoperand;
  string NAME = ?;
}
def it_mask_asmoperand {	// AsmOperandClass
  string Name = "ITMask";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def it_pred {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printMandatoryPredicateOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = it_pred_asmoperand;
  string NAME = ?;
}
def it_pred_asmoperand {	// AsmOperandClass
  string Name = "ITCondCode";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = "parseITCondCode";
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def itruncstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (ist node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = 1;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def jumptable {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::JumpTable";
  string SDClass = "JumpTableSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def ld {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::LOAD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTLoad;
  string NAME = ?;
}
def ldaex_1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (int_arm_ldaex node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def ldaex_2 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (int_arm_ldaex node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def ldaex_4 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (int_arm_ldaex node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def ldrex_1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (int_arm_ldrex node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def ldrex_2 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (int_arm_ldrex node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def ldrex_4 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (int_arm_ldrex node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def ldst_so_reg {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeSORegMemOperand";
  ValueType Type = i32;
  string PrintMethod = "printAddrMode2Operand";
  string EncoderMethod = "getLdStSORegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemRegOffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 3;
  string SelectFunc = "SelectLdStSOReg";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def ldstm_mode {	// DAGOperand Operand OperandWithDefaultOps OptionalDefOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = OtherVT;
  string PrintMethod = "printLdStmModeOperand";
  string EncoderMethod = "getLdStmModeOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops i32);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  dag DefaultOps = (ops (i32 1));
  string NAME = ?;
}
def llvm_any_ty {	// LLVMType
  ValueType VT = Any;
  int isAny = 1;
  string NAME = ?;
}
def llvm_anyfloat_ty {	// LLVMType
  ValueType VT = fAny;
  int isAny = 1;
  string NAME = ?;
}
def llvm_anyi64ptr_ty {	// LLVMType LLVMAnyPointerType
  ValueType VT = iPTRAny;
  int isAny = 1;
  LLVMType ElTy = llvm_i64_ty;
  string NAME = ?;
}
def llvm_anyint_ty {	// LLVMType
  ValueType VT = iAny;
  int isAny = 1;
  string NAME = ?;
}
def llvm_anyptr_ty {	// LLVMType LLVMAnyPointerType
  ValueType VT = iPTRAny;
  int isAny = 1;
  LLVMType ElTy = llvm_i8_ty;
  string NAME = ?;
}
def llvm_anyvector_ty {	// LLVMType
  ValueType VT = vAny;
  int isAny = 1;
  string NAME = ?;
}
def llvm_descriptor_ty {	// LLVMType LLVMQualPointerType LLVMPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = llvm_empty_ty;
  int AddrSpace = 0;
  string NAME = ?;
}
def llvm_double_ty {	// LLVMType
  ValueType VT = f64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_empty_ty {	// LLVMType
  ValueType VT = OtherVT;
  int isAny = 0;
  string NAME = ?;
}
def llvm_f128_ty {	// LLVMType
  ValueType VT = f128;
  int isAny = 0;
  string NAME = ?;
}
def llvm_f80_ty {	// LLVMType
  ValueType VT = f80;
  int isAny = 0;
  string NAME = ?;
}
def llvm_float_ty {	// LLVMType
  ValueType VT = f32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_half_ty {	// LLVMType
  ValueType VT = f16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_i16_ty {	// LLVMType
  ValueType VT = i16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_i1_ty {	// LLVMType
  ValueType VT = i1;
  int isAny = 0;
  string NAME = ?;
}
def llvm_i32_ty {	// LLVMType
  ValueType VT = i32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_i64_ty {	// LLVMType
  ValueType VT = i64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_i8_ty {	// LLVMType
  ValueType VT = i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_metadata_ty {	// LLVMType
  ValueType VT = MetadataVT;
  int isAny = 0;
  string NAME = ?;
}
def llvm_ppcf128_ty {	// LLVMType
  ValueType VT = ppcf128;
  int isAny = 0;
  string NAME = ?;
}
def llvm_ptr32_ty {	// LLVMType LLVMQualPointerType LLVMPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = llvm_i32_ty;
  int AddrSpace = 0;
  string NAME = ?;
}
def llvm_ptr64_ty {	// LLVMType LLVMQualPointerType LLVMPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = llvm_i64_ty;
  int AddrSpace = 0;
  string NAME = ?;
}
def llvm_ptr_ty {	// LLVMType LLVMQualPointerType LLVMPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = llvm_i8_ty;
  int AddrSpace = 0;
  string NAME = ?;
}
def llvm_ptrptr_ty {	// LLVMType LLVMQualPointerType LLVMPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = llvm_ptr_ty;
  int AddrSpace = 0;
  string NAME = ?;
}
def llvm_ptrx86mmx_ty {	// LLVMType LLVMQualPointerType LLVMPointerType
  ValueType VT = iPTR;
  int isAny = 0;
  LLVMType ElTy = llvm_x86mmx_ty;
  int AddrSpace = 0;
  string NAME = ?;
}
def llvm_token_ty {	// LLVMType
  ValueType VT = token;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v1024i1_ty {	// LLVMType
  ValueType VT = v1024i1;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v128i16_ty {	// LLVMType
  ValueType VT = v128i16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v128i8_ty {	// LLVMType
  ValueType VT = v128i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v16f32_ty {	// LLVMType
  ValueType VT = v16f32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v16i16_ty {	// LLVMType
  ValueType VT = v16i16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v16i1_ty {	// LLVMType
  ValueType VT = v16i1;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v16i32_ty {	// LLVMType
  ValueType VT = v16i32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v16i64_ty {	// LLVMType
  ValueType VT = v16i64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v16i8_ty {	// LLVMType
  ValueType VT = v16i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v1f32_ty {	// LLVMType
  ValueType VT = v1f32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v1f64_ty {	// LLVMType
  ValueType VT = v1f64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v1i128_ty {	// LLVMType
  ValueType VT = v1i128;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v1i16_ty {	// LLVMType
  ValueType VT = v1i16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v1i32_ty {	// LLVMType
  ValueType VT = v1i32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v1i64_ty {	// LLVMType
  ValueType VT = v1i64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v1i8_ty {	// LLVMType
  ValueType VT = v1i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v256i8_ty {	// LLVMType
  ValueType VT = v256i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v2f16_ty {	// LLVMType
  ValueType VT = v2f16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v2f32_ty {	// LLVMType
  ValueType VT = v2f32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v2f64_ty {	// LLVMType
  ValueType VT = v2f64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v2i16_ty {	// LLVMType
  ValueType VT = v2i16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v2i1_ty {	// LLVMType
  ValueType VT = v2i1;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v2i32_ty {	// LLVMType
  ValueType VT = v2i32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v2i64_ty {	// LLVMType
  ValueType VT = v2i64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v2i8_ty {	// LLVMType
  ValueType VT = v2i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v32i16_ty {	// LLVMType
  ValueType VT = v32i16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v32i1_ty {	// LLVMType
  ValueType VT = v32i1;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v32i32_ty {	// LLVMType
  ValueType VT = v32i32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v32i64_ty {	// LLVMType
  ValueType VT = v32i64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v32i8_ty {	// LLVMType
  ValueType VT = v32i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v4f16_ty {	// LLVMType
  ValueType VT = v4f16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v4f32_ty {	// LLVMType
  ValueType VT = v4f32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v4f64_ty {	// LLVMType
  ValueType VT = v4f64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v4i16_ty {	// LLVMType
  ValueType VT = v4i16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v4i1_ty {	// LLVMType
  ValueType VT = v4i1;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v4i32_ty {	// LLVMType
  ValueType VT = v4i32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v4i64_ty {	// LLVMType
  ValueType VT = v4i64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v4i8_ty {	// LLVMType
  ValueType VT = v4i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v512i1_ty {	// LLVMType
  ValueType VT = v512i1;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v64i16_ty {	// LLVMType
  ValueType VT = v64i16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v64i1_ty {	// LLVMType
  ValueType VT = v64i1;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v64i32_ty {	// LLVMType
  ValueType VT = v64i32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v64i8_ty {	// LLVMType
  ValueType VT = v64i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v8f16_ty {	// LLVMType
  ValueType VT = v8f16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v8f32_ty {	// LLVMType
  ValueType VT = v8f32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v8f64_ty {	// LLVMType
  ValueType VT = v8f64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v8i16_ty {	// LLVMType
  ValueType VT = v8i16;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v8i1_ty {	// LLVMType
  ValueType VT = v8i1;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v8i32_ty {	// LLVMType
  ValueType VT = v8i32;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v8i64_ty {	// LLVMType
  ValueType VT = v8i64;
  int isAny = 0;
  string NAME = ?;
}
def llvm_v8i8_ty {	// LLVMType
  ValueType VT = v8i8;
  int isAny = 0;
  string NAME = ?;
}
def llvm_vararg_ty {	// LLVMType
  ValueType VT = isVoid;
  int isAny = 0;
  string NAME = ?;
}
def llvm_void_ty {	// LLVMType
  ValueType VT = isVoid;
  int isAny = 0;
  string NAME = ?;
}
def llvm_x86mmx_ty {	// LLVMType
  ValueType VT = x86mmx;
  int isAny = 0;
  string NAME = ?;
}
def lo16AllZero {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{
  // Returns true if all low 16-bits are 0.
  return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = hi16;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def lo5AllOne {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{
  // Returns true if all low 5-bits are 1.
  return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def load {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (unindexedload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = 1;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def masked_gather {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::MGATHER";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTMaskedGather;
  string NAME = ?;
}
def masked_load {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayLoad, SDNPMemOperand];
  string Opcode = "ISD::MLOAD";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTMaskedLoad;
  string NAME = ?;
}
def masked_scatter {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMemOperand];
  string Opcode = "ISD::MSCATTER";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTMaskedScatter;
  string NAME = ?;
}
def masked_store {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMemOperand];
  string Opcode = "ISD::MSTORE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTMaskedStore;
  string NAME = ?;
}
def mcsym {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::MCSymbol";
  string SDClass = "MCSymbolSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def memb_opt {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeMemBarrierOption";
  ValueType Type = i32;
  string PrintMethod = "printMemBOption";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemBarrierOptOperand;
  string NAME = ?;
}
def mips_q31_ty {	// LLVMType
  ValueType VT = i32;
  int isAny = 0;
  string NAME = ?;
}
def mips_v2q15_ty {	// LLVMType
  ValueType VT = v2i16;
  int isAny = 0;
  string NAME = ?;
}
def mips_v4q7_ty {	// LLVMType
  ValueType VT = v4i8;
  int isAny = 0;
  string NAME = ?;
}
def mod_imm {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printModImmOperand";
  string EncoderMethod = "getModImmOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ModImmAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
    return ARM_AM::getSOImmVal(Imm) != -1;
  }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def mod_imm1_7_neg {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ThumbModImmNeg1_7AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
    unsigned Value = -(unsigned)N->getZExtValue();
    return 0 < Value && Value < 8;
  }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_neg_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def mod_imm8_255_neg {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ThumbModImmNeg8_255AsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
    unsigned Value = -(unsigned)N->getZExtValue();
    return 7 < Value && Value < 256;
  }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_neg_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def mod_imm_neg {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ModImmNegAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
    unsigned Value = -(unsigned)N->getZExtValue();
    return Value && ARM_AM::getSOImmVal(Value) != -1;
  }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_neg_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def mod_imm_not {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ModImmNotAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
    return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
  }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = imm_not_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def msr_mask {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeMSRMask";
  ValueType Type = i32;
  string PrintMethod = "printMSRMaskOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MSRMaskOperand;
  string NAME = ?;
}
def mul {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::MUL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def mulhs {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative];
  string Opcode = "ISD::MULHS";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def mulhu {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative];
  string Opcode = "ISD::MULHU";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def nImmSplatI16 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmSplatI16AsmOperand;
  string NAME = ?;
}
def nImmSplatI16AsmOperand {	// AsmOperandClass
  string Name = "NEONi16splat";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def nImmSplatI32 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmSplatI32AsmOperand;
  string NAME = ?;
}
def nImmSplatI32AsmOperand {	// AsmOperandClass
  string Name = "NEONi32splat";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def nImmSplatI64 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmSplatI64AsmOperand;
  string NAME = ?;
}
def nImmSplatI64AsmOperand {	// AsmOperandClass
  string Name = "NEONi64splat";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def nImmSplatI8 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmSplatI8AsmOperand;
  string NAME = ?;
}
def nImmSplatI8AsmOperand {	// AsmOperandClass
  string Name = "NEONi8splat";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def nImmSplatNotI16 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmSplatNotI16AsmOperand;
  string NAME = ?;
}
def nImmSplatNotI16AsmOperand {	// AsmOperandClass
  string Name = "NEONi16splatNot";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def nImmSplatNotI32 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmSplatNotI32AsmOperand;
  string NAME = ?;
}
def nImmSplatNotI32AsmOperand {	// AsmOperandClass
  string Name = "NEONi32splatNot";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def nImmVMOVF32 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printFPImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = FPImmOperand;
  string NAME = ?;
}
def nImmVMOVI32 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmVMOVI32AsmOperand;
  string NAME = ?;
}
def nImmVMOVI32AsmOperand {	// AsmOperandClass
  string Name = "NEONi32vmov";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def nImmVMOVI32Neg {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = nImmVMOVI32NegAsmOperand;
  string NAME = ?;
}
def nImmVMOVI32NegAsmOperand {	// AsmOperandClass
  string Name = "NEONi32vmovNeg";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def nModImm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNEONModImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def neon_vcvt_imm32 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeVCVTImmOperand";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getNEONVcvtImm32OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def node {
  string NAME = ?;
}
def nohash_imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printNoHashImmediate";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def non_word_alignedload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (load node:$ptr);
  code PredicateCode = [{
  return cast<LoadSDNode>(N)->getAlignment() < 4;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def non_word_alignedstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (store node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<StoreSDNode>(N)->getAlignment() < 4;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def nontemporalload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (load node:$ptr);
  code PredicateCode = [{
  return cast<LoadSDNode>(N)->isNonTemporal();
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def nontemporalstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (store node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<StoreSDNode>(N)->isNonTemporal();
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def not {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$in);
  dag Fragment = (xor node:$in, -1);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def null_frag {	// SDPatternOperator
  list<SDNodeProperty> Properties = [];
  string NAME = ?;
}
def nxv16f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 104;
  string NAME = ?;
}
def nxv16i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 16;
  int Value = 59;
  string NAME = ?;
}
def nxv16i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 71;
  string NAME = ?;
}
def nxv16i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 77;
  string NAME = ?;
}
def nxv16i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 1024;
  int Value = 83;
  string NAME = ?;
}
def nxv16i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 65;
  string NAME = ?;
}
def nxv1f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 100;
  string NAME = ?;
}
def nxv1f64 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 105;
  string NAME = ?;
}
def nxv1i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 1;
  int Value = 55;
  string NAME = ?;
}
def nxv1i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 16;
  int Value = 67;
  string NAME = ?;
}
def nxv1i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 73;
  string NAME = ?;
}
def nxv1i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 79;
  string NAME = ?;
}
def nxv1i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 8;
  int Value = 61;
  string NAME = ?;
}
def nxv2f16 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 97;
  string NAME = ?;
}
def nxv2f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 101;
  string NAME = ?;
}
def nxv2f64 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 106;
  string NAME = ?;
}
def nxv2i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 2;
  int Value = 56;
  string NAME = ?;
}
def nxv2i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 68;
  string NAME = ?;
}
def nxv2i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 74;
  string NAME = ?;
}
def nxv2i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 80;
  string NAME = ?;
}
def nxv2i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 16;
  int Value = 62;
  string NAME = ?;
}
def nxv32i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 60;
  string NAME = ?;
}
def nxv32i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 72;
  string NAME = ?;
}
def nxv32i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 1024;
  int Value = 78;
  string NAME = ?;
}
def nxv32i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 2048;
  int Value = 84;
  string NAME = ?;
}
def nxv32i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 66;
  string NAME = ?;
}
def nxv4f16 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 98;
  string NAME = ?;
}
def nxv4f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 102;
  string NAME = ?;
}
def nxv4f64 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 107;
  string NAME = ?;
}
def nxv4i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 4;
  int Value = 57;
  string NAME = ?;
}
def nxv4i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 69;
  string NAME = ?;
}
def nxv4i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 75;
  string NAME = ?;
}
def nxv4i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 81;
  string NAME = ?;
}
def nxv4i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 63;
  string NAME = ?;
}
def nxv8f16 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 99;
  string NAME = ?;
}
def nxv8f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 103;
  string NAME = ?;
}
def nxv8f64 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 108;
  string NAME = ?;
}
def nxv8i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 8;
  int Value = 58;
  string NAME = ?;
}
def nxv8i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 70;
  string NAME = ?;
}
def nxv8i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 76;
  string NAME = ?;
}
def nxv8i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 82;
  string NAME = ?;
}
def nxv8i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 64;
  string NAME = ?;
}
def ops {
  string NAME = ?;
}
def or {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::OR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def outs {
  string NAME = ?;
}
def p_imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeCoprocessor";
  ValueType Type = i32;
  string PrintMethod = "printPImmediate";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = CoprocNumAsmOperand;
  string NAME = ?;
}
def pclabel {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printPCLabel";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def pkh_asr_amt {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printPKHASRShiftImm";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = PKHASRAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm > 0 && Imm <= 32; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def pkh_lsl_amt {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printPKHLSLShiftImm";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = PKHLSLAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm >= 0 && Imm < 32; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def post_store {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr, node:$offset);
  dag Fragment = (istore node:$val, node:$ptr, node:$offset);
  code PredicateCode = [{
  ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
  return AM == ISD::POST_INC || AM == ISD::POST_DEC;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def post_truncst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (itruncstore node:$val, node:$base, node:$offset);
  code PredicateCode = [{
  ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
  return AM == ISD::POST_INC || AM == ISD::POST_DEC;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def post_truncstf32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (post_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = f32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def post_truncsti1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (post_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i1;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def post_truncsti16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (post_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def post_truncsti32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (post_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def post_truncsti8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (post_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def postidx_imm8 {	// DAGOperand Operand MemOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printPostIdxImm8Operand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = PostIdxImm8AsmOperand;
  string NAME = ?;
}
def postidx_imm8s4 {	// DAGOperand Operand MemOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printPostIdxImm8s4Operand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = PostIdxImm8s4AsmOperand;
  string NAME = ?;
}
def postidx_reg {	// DAGOperand Operand MemOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodePostIdxReg";
  ValueType Type = i32;
  string PrintMethod = "printPostIdxRegOperand";
  string EncoderMethod = "getPostIdxRegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPRnopc, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = PostIdxRegAsmOperand;
  string NAME = ?;
}
def ppcf128 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 13;
  string NAME = ?;
}
def pre_store {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (istore node:$val, node:$base, node:$offset);
  code PredicateCode = [{
  ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
  return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def pre_truncst {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (itruncstore node:$val, node:$base, node:$offset);
  code PredicateCode = [{
  ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
  return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def pre_truncstf32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (pre_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = f32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def pre_truncsti1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (pre_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i1;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def pre_truncsti16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (pre_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def pre_truncsti32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (pre_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def pre_truncsti8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$base, node:$offset);
  dag Fragment = (pre_truncst node:$val, node:$base, node:$offset);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def pred {	// DAGOperand Operand OperandWithDefaultOps PredicateOp PredicateOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodePredicateOperand";
  ValueType Type = OtherVT;
  string PrintMethod = "printPredicateOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops i32imm, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = CondCodeOperand;
  dag DefaultOps = (ops (i32 14), (i32 zero_reg));
  string NAME = ?;
}
def prefetch {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand];
  string Opcode = "ISD::PREFETCH";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTPrefetch;
  string NAME = ?;
}
def ptr_rc {	// PointerLikeRegClass
  int RegClassKind = 0;
  string NAME = ?;
}
def ptype0 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_0";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 1;
  string NAME = ?;
}
def ptype1 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_1";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 1;
  string NAME = ?;
}
def ptype2 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_2";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 1;
  string NAME = ?;
}
def ptype3 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_3";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 1;
  string NAME = ?;
}
def ptype4 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_4";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 1;
  string NAME = ?;
}
def ptype5 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_5";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 1;
  string NAME = ?;
}
def qqsub_0 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 256;
  int Offset = 0;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def qqsub_1 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 256;
  int Offset = 256;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def qsub_0 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 128;
  int Offset = 0;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def qsub_1 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 128;
  int Offset = 128;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def qsub_2 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 128;
  int Offset = 256;
  list<SubRegIndex> ComposedOf = [qqsub_1, qsub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def qsub_3 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 128;
  int Offset = 384;
  list<SubRegIndex> ComposedOf = [qqsub_1, qsub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def rGPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (sub GPR, SP, PC);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
  code AltOrderSelect = [{
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }];
  int AllocationPriority = 0;
  string DiagnosticType = "rGPR";
  string DiagnosticString = "";
  string NAME = ?;
}
def readcyclecounter {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ISD::READCYCLECOUNTER";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntLeaf;
  string NAME = ?;
}
def reglist {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeRegListOperand";
  ValueType Type = i32;
  string PrintMethod = "printRegisterList";
  string EncoderMethod = "getRegisterListOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = RegListAsmOperand;
  string NAME = ?;
}
def rot_imm {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printRotImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = RotImmAsmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{
    int32_t v = N->getZExtValue();
    return v == 8 || v == 16 || v == 24; }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = rot_imm_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def rot_imm_XFORM {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  switch (N->getZExtValue()){
  default: llvm_unreachable(nullptr);
  case 0:  return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
  case 8:  return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
  case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
  case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
  }
}];
  string NAME = ?;
}
def rotl {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ROTL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntShiftOp;
  string NAME = ?;
}
def rotr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ROTR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntShiftOp;
  string NAME = ?;
}
def s32 {	// LLT
  string NAME = ?;
}
def s64 {	// LLT
  string NAME = ?;
}
def s_cc_out {	// DAGOperand Operand OperandWithDefaultOps OptionalDefOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeCCOutOperand";
  ValueType Type = OtherVT;
  string PrintMethod = "printSBitModifierOperand";
  string EncoderMethod = "getCCOutOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops CCR);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = CCOutOperand;
  dag DefaultOps = (ops (i32 CPSR));
  string NAME = ?;
}
def scalar_to_vector {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SCALAR_TO_VECTOR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_873;
  string NAME = ?;
}
def sdiv {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SDIV";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def sdivrem {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SDIVREM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinHiLoOp;
  string NAME = ?;
}
def select {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SELECT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTSelect;
  string NAME = ?;
}
def selectcc {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SELECT_CC";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTSelectCC;
  string NAME = ?;
}
def sequence {
  string NAME = ?;
}
def set {
  string NAME = ?;
}
def setcc {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SETCC";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTSetCC;
  string NAME = ?;
}
def setend_op {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printSetendOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = SetEndAsmOperand;
  string NAME = ?;
}
def seteq {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETEQ);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setge {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETGE);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setgt {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETGT);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setle {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETLE);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setlt {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETLT);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setne {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETNE);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def seto {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETO);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setoeq {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETOEQ);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setoge {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETOGE);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setogt {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETOGT);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setole {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETOLE);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setolt {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETOLT);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setone {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETONE);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setueq {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETUEQ);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setuge {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETUGE);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setugt {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETUGT);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setule {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETULE);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setult {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETULT);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setune {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETUNE);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def setuo {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (setcc node:$lhs, node:$rhs, SETUO);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def sext {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SIGN_EXTEND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntExtendOp;
  string NAME = ?;
}
def sext_16_node {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 GPR:$a);
  code PredicateCode = [{
  if (CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17)
    return true;

  if (N->getOpcode() != ISD::SRA)
    return false;
  if (N->getOperand(0).getOpcode() != ISD::SHL)
    return false;

  auto *ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(1));
  if (!ShiftVal || ShiftVal->getZExtValue() != 16)
    return false;

  ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(0)->getOperand(1));
  if (!ShiftVal || ShiftVal->getZExtValue() != 16)
    return false;

  return true;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def sext_inreg {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SIGN_EXTEND_INREG";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTExtInreg;
  string NAME = ?;
}
def sext_invec {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SIGN_EXTEND_VECTOR_INREG";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTExtInvec;
  string NAME = ?;
}
def sextload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (unindexedload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = 1;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def sextloadi1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (sextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i1;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def sextloadi16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (sextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def sextloadi32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (sextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def sextloadi8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (sextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def sextloadvi1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (sextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i1;
  string NAME = ?;
}
def sextloadvi16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (sextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i16;
  string NAME = ?;
}
def sextloadvi32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (sextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i32;
  string NAME = ?;
}
def sextloadvi8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (sextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i8;
  string NAME = ?;
}
def shift_imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printShiftImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ShifterImmAsmOperand;
  string NAME = ?;
}
def shift_so_reg_imm {	// DAGOperand Operand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeSORegImmOperand";
  ValueType Type = i32;
  string PrintMethod = "printSORegImmOperand";
  string EncoderMethod = "getSORegImmOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops GPR, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ShiftedImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectShiftImmShifterOperand";
  list<SDNode> RootNodes = [shl, srl, sra, rotr];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def shift_so_reg_reg {	// DAGOperand Operand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeSORegRegOperand";
  ValueType Type = i32;
  string PrintMethod = "printSORegRegOperand";
  string EncoderMethod = "getSORegRegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops GPR, GPR, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ShiftedRegAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 3;
  string SelectFunc = "SelectShiftRegShifterOperand";
  list<SDNode> RootNodes = [shl, srl, sra, rotr];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def shl {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SHL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntShiftOp;
  string NAME = ?;
}
def shr_imm16 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeShiftRight16Imm";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getShiftRight16Imm";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = shr_imm16_asm_operand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm > 0 && Imm <= 16; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def shr_imm16_asm_operand {	// AsmOperandClass ImmAsmOperand
  string Name = "ShrImm16";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,16>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [1,16]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def shr_imm32 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeShiftRight32Imm";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getShiftRight32Imm";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = shr_imm32_asm_operand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm > 0 && Imm <= 32; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def shr_imm32_asm_operand {	// AsmOperandClass ImmAsmOperand
  string Name = "ShrImm32";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,32>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [1,32]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def shr_imm64 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeShiftRight64Imm";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getShiftRight64Imm";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = shr_imm64_asm_operand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm > 0 && Imm <= 64; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def shr_imm64_asm_operand {	// AsmOperandClass ImmAsmOperand
  string Name = "ShrImm64";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,64>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [1,64]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def shr_imm8 {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeShiftRight8Imm";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getShiftRight8Imm";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = shr_imm8_asm_operand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{ return Imm > 0 && Imm <= 8; }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def shr_imm8_asm_operand {	// AsmOperandClass ImmAsmOperand
  string Name = "ShrImm8";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = "isImmediate<1,8>";
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be an immediate in the range [1,8]";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def sint_to_fp {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SINT_TO_FP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntToFPOp;
  string NAME = ?;
}
def smax {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::SMAX";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def smin {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::SMIN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def smullohi {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative];
  string Opcode = "ISD::SMUL_LOHI";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinHiLoOp;
  string NAME = ?;
}
def so_reg_imm {	// DAGOperand Operand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeSORegImmOperand";
  ValueType Type = i32;
  string PrintMethod = "printSORegImmOperand";
  string EncoderMethod = "getSORegImmOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops GPR, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ShiftedImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectImmShifterOperand";
  list<SDNode> RootNodes = [shl, srl, sra, rotr];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def so_reg_reg {	// DAGOperand Operand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeSORegRegOperand";
  ValueType Type = i32;
  string PrintMethod = "printSORegRegOperand";
  string EncoderMethod = "getSORegRegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ShiftedRegAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 3;
  string SelectFunc = "SelectRegShifterOperand";
  list<SDNode> RootNodes = [shl, srl, sra, rotr];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def spr_reglist {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeSPRRegListOperand";
  ValueType Type = i32;
  string PrintMethod = "printRegisterList";
  string EncoderMethod = "getRegisterListOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = SPRRegListAsmOperand;
  string NAME = ?;
}
def sra {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SRA";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntShiftOp;
  string NAME = ?;
}
def srcvalue {
  string NAME = ?;
}
def srem {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SREM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def srl {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SRL";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntShiftOp;
  string NAME = ?;
}
def ssub_0 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 0;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_1 {	// SubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 32;
  list<SubRegIndex> ComposedOf = [];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_10 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 320;
  list<SubRegIndex> ComposedOf = [dsub_5, ssub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_11 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 352;
  list<SubRegIndex> ComposedOf = [dsub_5, ssub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_12 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 384;
  list<SubRegIndex> ComposedOf = [dsub_6, ssub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_13 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 416;
  list<SubRegIndex> ComposedOf = [dsub_6, ssub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_2 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 64;
  list<SubRegIndex> ComposedOf = [dsub_1, ssub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_3 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 96;
  list<SubRegIndex> ComposedOf = [dsub_1, ssub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_4 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 128;
  list<SubRegIndex> ComposedOf = [dsub_2, ssub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_5 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 160;
  list<SubRegIndex> ComposedOf = [dsub_2, ssub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_6 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 192;
  list<SubRegIndex> ComposedOf = [dsub_3, ssub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_7 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 224;
  list<SubRegIndex> ComposedOf = [dsub_3, ssub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_8 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 256;
  list<SubRegIndex> ComposedOf = [dsub_4, ssub_0];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def ssub_9 {	// SubRegIndex ComposedSubRegIndex
  string Namespace = "ARM";
  int Size = 32;
  int Offset = 288;
  list<SubRegIndex> ComposedOf = [dsub_4, ssub_1];
  list<SubRegIndex> CoveringSubRegIndices = [];
  string NAME = ?;
}
def st {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPMayStore, SDNPMemOperand];
  string Opcode = "ISD::STORE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTStore;
  string NAME = ?;
}
def stlex_1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (int_arm_stlex node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def stlex_2 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (int_arm_stlex node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def stlex_4 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (int_arm_stlex node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def store {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (unindexedstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = 0;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def strex_1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (int_arm_strex node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def strex_2 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (int_arm_strex node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def strex_4 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (int_arm_strex node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def sub {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::SUB";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def subc {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPOutGlue];
  string Opcode = "ISD::SUBC";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def sube {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPOutGlue, SDNPInGlue];
  string Opcode = "ISD::SUBE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def sysLDMDA {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmda${p}	$Rn, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysLDMDA_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmda${p}	$Rn!, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysLDMDB {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmdb${p}	$Rn, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysLDMDB_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmdb${p}	$Rn!, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysLDMIA {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldm${p}	$Rn, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysLDMIA_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 1, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldm${p}	$Rn!, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysLDMIB {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmib${p}	$Rn, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysLDMIB_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 1, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmib${p}	$Rn!, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysSTMDA {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmda${p}	$Rn, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysSTMDA_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmda${p}	$Rn!, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysSTMDB {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmdb${p}	$Rn, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysSTMDB_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmdb${p}	$Rn!, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysSTMIA {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stm${p}	$Rn, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysSTMIA_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 0, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stm${p}	$Rn!, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysSTMIB {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmib${p}	$Rn, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def sysSTMIB_UPD {	// Instruction InstTemplate Encoding InstARM XI AXI4
  field bits<32> Inst = { p{3}, p{2}, p{1}, p{0}, 1, 0, 0, 1, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmib${p}	$Rn!, $regs ^";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsARM];
  int Size = 4;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeMemMultipleWritebackInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrMode4;
  IndexMode IM = IndexModeUpd;
  bits<2> IndexModeBits = { 1, 1 };
  Format F = LdStMulFrm;
  bits<6> Form = { 0, 0, 1, 0, 1, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2ABS {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$dst);
  dag InOperandList = (ins rGPR:$src);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2ADCri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 1, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "adc${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMadde rGPR:$Rn, t2_so_imm:$imm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ADCrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "adc${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMadde rGPR:$Rn, rGPR:$Rm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2ADCrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "adc${s}${p}.w	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMadde rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ADDSri {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMaddc GPRnopc:$Rn, t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2ADDSrr {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMaddc GPRnopc:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2ADDSrs {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMaddc GPRnopc:$Rn, t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2ADDri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 1, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "add${s}${p}.w	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPRnopc:$Rn, t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ADDri12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 1, 0, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, imm0_4095:$imm, pred:$p);
  string AsmString = "addw${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPR:$Rn, imm0_4095:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ADDrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "add${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPRnopc:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2ADDrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "add${s}${p}.w	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (add GPRnopc:$Rn, t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ADR {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI T2PCOneRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, addr{11}, 1, 0, addr{12}, 0, addr{12}, 0, 1, 1, 1, 1, 0, addr{10}, addr{9}, addr{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins t2adrlabel:$addr, pred:$p);
  string AsmString = "adr{$p}.w	$Rd, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2Adr";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> label = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ANDanonymous_3369 {	// InstAlias Requires t2InstAlias
  string AsmString = "and${s}${p} $Rdn, $imm";
  dag ResultInst = (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ANDanonymous_3370 {	// InstAlias Requires t2InstAlias
  string AsmString = "and${s}${p}.w $Rdn, $Rm";
  dag ResultInst = (t2ANDrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ANDanonymous_3371 {	// InstAlias Requires t2InstAlias
  string AsmString = "and${s}${p}.w $Rdn, $shift";
  dag ResultInst = (t2ANDrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ANDanonymous_3372 {	// InstAlias Requires t2InstAlias
  string AsmString = "and${s}${p}.w $Rd, $Rn, $imm";
  dag ResultInst = (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ANDanonymous_3373 {	// InstAlias Requires t2InstAlias
  string AsmString = "and${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2ANDrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ANDanonymous_3374 {	// InstAlias Requires t2InstAlias
  string AsmString = "and${s}${p} $Rd, $Rn, $shift";
  dag ResultInst = (t2ANDrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ANDanonymous_3375 {	// InstAlias Requires t2InstAlias
  string AsmString = "and${s}${p}.w $Rdn, $imm";
  dag ResultInst = (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ANDanonymous_3376 {	// InstAlias Requires t2InstAlias
  string AsmString = "and${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2ANDrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ANDanonymous_3377 {	// InstAlias Requires t2InstAlias
  string AsmString = "and${s}${p} $Rdn, $shift";
  dag ResultInst = (t2ANDrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ANDri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 0, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "and${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (and rGPR:$Rn, t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ANDrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "and${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (and rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ANDrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "and${s}${p}.w	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set rGPR:$Rd, (and rGPR:$Rn, t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ASRanonymous_3378 {	// InstAlias Requires t2InstAlias
  string AsmString = "asr${s}${p}.w $Rdn, $imm";
  dag ResultInst = (t2ASRri rGPR:$Rdn, rGPR:$Rdn, imm_sr:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ASRanonymous_3379 {	// InstAlias Requires t2InstAlias
  string AsmString = "asr${s}${p}.w $Rdn, $Rm";
  dag ResultInst = (t2ASRrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ASRanonymous_3380 {	// InstAlias Requires t2InstAlias
  string AsmString = "asr${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2ASRri rGPR:$Rd, rGPR:$Rn, imm_sr:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ASRanonymous_3381 {	// InstAlias Requires t2InstAlias
  string AsmString = "asr${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2ASRrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ASRanonymous_3382 {	// InstAlias Requires t2InstAlias
  string AsmString = "asr${s}${p} $Rdn, $imm";
  dag ResultInst = (t2ASRri rGPR:$Rdn, rGPR:$Rdn, imm_sr:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ASRanonymous_3383 {	// InstAlias Requires t2InstAlias
  string AsmString = "asr${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2ASRrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ASRri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftImm Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, s{0}, 1, 1, 1, 1, ?, imm{4}, imm{3}, imm{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{1}, imm{0}, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, imm_sr:$imm, pred:$p, cc_out:$s);
  string AsmString = "asr${s}${p}.w	$Rd, $Rm, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (sra rGPR:$Rm, (i32 imm_sr:$imm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> imm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ASRrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "asr${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (sra rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2B {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, target{23}, target{20}, target{19}, target{18}, target{17}, target{16}, target{15}, target{14}, target{13}, target{12}, target{11}, 1, 0, target{22}, 1, target{21}, target{10}, target{9}, target{8}, target{7}, target{6}, target{5}, target{4}, target{3}, target{2}, target{1}, target{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins thumb_br_target:$target, pred:$p);
  string AsmString = "b${p}.w	$target";
  list<dag> Pattern = [(br bb:$target)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 1;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2BInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "cvtThumbBranches";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<24> target = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2BFC {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2BitFI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, imm{4}, imm{3}, imm{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{1}, imm{0}, 0, imm{9}, imm{8}, imm{7}, imm{6}, imm{5} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$src, bf_inv_mask_imm:$imm, pred:$p);
  string AsmString = "bfc${p}	$Rd, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAsi;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<5> msb = { imm{9}, imm{8}, imm{7}, imm{6}, imm{5} };
  bits<5> lsb = { imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  bits<10> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2BFI {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2BitFI T2TwoRegBitFI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{4}, imm{3}, imm{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{1}, imm{0}, 0, imm{9}, imm{8}, imm{7}, imm{6}, imm{5} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm, pred:$p);
  string AsmString = "bfi${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$src = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<5> msb = { imm{9}, imm{8}, imm{7}, imm{6}, imm{5} };
  bits<5> lsb = { imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<10> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2BICanonymous_3369 {	// InstAlias Requires t2InstAlias
  string AsmString = "bic${s}${p} $Rdn, $imm";
  dag ResultInst = (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2BICanonymous_3370 {	// InstAlias Requires t2InstAlias
  string AsmString = "bic${s}${p}.w $Rdn, $Rm";
  dag ResultInst = (t2BICrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2BICanonymous_3371 {	// InstAlias Requires t2InstAlias
  string AsmString = "bic${s}${p}.w $Rdn, $shift";
  dag ResultInst = (t2BICrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2BICanonymous_3372 {	// InstAlias Requires t2InstAlias
  string AsmString = "bic${s}${p}.w $Rd, $Rn, $imm";
  dag ResultInst = (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2BICanonymous_3373 {	// InstAlias Requires t2InstAlias
  string AsmString = "bic${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2BICrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2BICanonymous_3374 {	// InstAlias Requires t2InstAlias
  string AsmString = "bic${s}${p} $Rd, $Rn, $shift";
  dag ResultInst = (t2BICrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2BICanonymous_3375 {	// InstAlias Requires t2InstAlias
  string AsmString = "bic${s}${p}.w $Rdn, $imm";
  dag ResultInst = (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2BICanonymous_3376 {	// InstAlias Requires t2InstAlias
  string AsmString = "bic${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2BICrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2BICanonymous_3377 {	// InstAlias Requires t2InstAlias
  string AsmString = "bic${s}${p} $Rdn, $shift";
  dag ResultInst = (t2BICrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2BICri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 0, 0, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "bic${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (anonymous_3184 rGPR:$Rn, t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2BICrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "bic${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (anonymous_3184 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2BICrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "bic${s}${p}.w	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set rGPR:$Rd, (anonymous_3184 rGPR:$Rn, t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2BR_JT {	// Instruction InstTemplate PseudoInst t2basePseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$target, GPR:$index, i32imm:$jt);
  string AsmString = "";
  list<dag> Pattern = [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2BXJ {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, func{3}, func{2}, func{1}, func{0}, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$func, pred:$p);
  string AsmString = "bxj${p}	$func";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> func = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2Bcc {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, target{20}, p{3}, p{2}, p{1}, p{0}, target{17}, target{16}, target{15}, target{14}, target{13}, target{12}, 1, 0, target{18}, 0, target{19}, target{11}, target{10}, target{9}, target{8}, target{7}, target{6}, target{5}, target{4}, target{3}, target{2}, target{1} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins brtarget:$target, pred:$p);
  string AsmString = "b${p}.w	$target";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumb2BCCInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "cvtThumbBranches";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<21> target = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2CDP {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 1, 0, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRn{3}, CRn{2}, CRn{1}, CRn{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 0, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2, pred:$p);
  string AsmString = "cdp${p}	$cop, $opc1, $CRd, $CRn, $CRm, $opc2";
  list<dag> Pattern = [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, PreV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CDP2 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRn{3}, CRn{2}, CRn{1}, CRn{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 0, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2, pred:$p);
  string AsmString = "cdp2${p}	$cop, $opc1, $CRd, $CRn, $CRm, $opc2";
  list<dag> Pattern = [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, PreV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CLREX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "clrex${p}";
  list<dag> Pattern = [(int_arm_clrex)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2CLZ {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2I_misc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, pred:$p);
  string AsmString = "clz${p}	$Rd, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (ctlz rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CMNri {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2OneRegCmpImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, 1, 1, 1, 1, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  string AsmString = "cmn${p}.w	$Rn, $imm";
  list<dag> Pattern = [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPi;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2CMNzrr {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoRegCmp Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "cmn${p}.w	$Rn, $Rm";
  list<dag> Pattern = [(anonymous_3214 GPRnopc:$Rn, rGPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPr;
  list<SchedReadWrite> SchedRW = [WriteCMP, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CMNzrs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2OneRegCmpShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, 1, 1, 1, 1, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p);
  string AsmString = "cmn${p}.w	$Rn, $ShiftedRm";
  list<dag> Pattern = [(anonymous_3214 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPsi;
  list<SchedReadWrite> SchedRW = [WriteCMPsi, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2CMPanonymous_3384 {	// InstAlias Requires t2InstAlias
  string AsmString = "cmp${p} $Rn, $imm";
  dag ResultInst = (t2CMPri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2CMPanonymous_3385 {	// InstAlias Requires t2InstAlias
  string AsmString = "cmp${p} $Rn, $shift";
  dag ResultInst = (t2CMPrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2CMPri {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2OneRegCmpImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 1, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, 1, 1, 1, 1, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  string AsmString = "cmp${p}.w	$Rn, $imm";
  list<dag> Pattern = [(ARMcmp GPRnopc:$Rn, t2_so_imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPi;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2CMPrr {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoRegCmp Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "cmp${p}.w	$Rn, $Rm";
  list<dag> Pattern = [(ARMcmp GPRnopc:$Rn, rGPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPr;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CMPrs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2OneRegCmpShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, 1, 1, 1, 1, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p);
  string AsmString = "cmp${p}.w	$Rn, $ShiftedRm";
  list<dag> Pattern = [(ARMcmp GPRnopc:$Rn, t2_so_reg:$ShiftedRm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPsi;
  list<SchedReadWrite> SchedRW = [WriteCMPsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2CPS1p {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI Requires t2CPS
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode);
  string AsmString = "cps	$mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2CPSInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<2> imod = { 0, 0 };
  bits<3> iflags = { 0, 0, 0 };
  bits<5> mode = { ?, ?, ?, ?, ? };
  bit M = 1;
  string NAME = ?;
}
def t2CPS2p {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI Requires t2CPS
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, imod{1}, imod{0}, 0, iflags{2}, iflags{1}, iflags{0}, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imod_op:$imod, iflags_op:$iflags);
  string AsmString = "cps$imod.w	$iflags";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2CPSInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<2> imod = { ?, ? };
  bits<3> iflags = { ?, ?, ? };
  bits<5> mode = { 0, 0, 0, 0, 0 };
  bit M = 0;
  string NAME = ?;
}
def t2CPS3p {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI Requires t2CPS
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, imod{1}, imod{0}, 1, iflags{2}, iflags{1}, iflags{0}, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode);
  string AsmString = "cps$imod	$iflags, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2CPSInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<2> imod = { ?, ? };
  bits<3> iflags = { ?, ?, ? };
  bits<5> mode = { ?, ?, ?, ?, ? };
  bit M = 1;
  string NAME = ?;
}
def t2CRC32B {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI T2ThreeRegNoP Requires T2I_crc32
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm);
  string AsmString = "crc32b	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_crc32b rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CRC32CB {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI T2ThreeRegNoP Requires T2I_crc32
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm);
  string AsmString = "crc32cb	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_crc32cb rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CRC32CH {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI T2ThreeRegNoP Requires T2I_crc32
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm);
  string AsmString = "crc32ch	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_crc32ch rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CRC32CW {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI T2ThreeRegNoP Requires T2I_crc32
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm);
  string AsmString = "crc32cw	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_crc32cw rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CRC32H {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI T2ThreeRegNoP Requires T2I_crc32
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm);
  string AsmString = "crc32h	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_crc32h rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2CRC32W {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI T2ThreeRegNoP Requires T2I_crc32
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm);
  string AsmString = "crc32w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_crc32w rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8, HasCRC];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2DBG {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, opt{3}, opt{2}, opt{1}, opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_15:$opt, pred:$p);
  string AsmString = "dbg${p}	$opt";
  list<dag> Pattern = [(int_arm_dbg imm0_15:$opt)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2DCPS1 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2DCPS
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "dcps1${p}";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2DCPS2 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2DCPS
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "dcps2${p}";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2DCPS3 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2DCPS
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "dcps3${p}";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2DMB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, opt{3}, opt{2}, opt{1}, opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins memb_opt:$opt, pred:$p);
  string AsmString = "dmb${p}	$opt";
  list<dag> Pattern = [(int_arm_dmb (i32 imm0_15:$opt))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasDB];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2DSB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, opt{3}, opt{2}, opt{1}, opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins memb_opt:$opt, pred:$p);
  string AsmString = "dsb${p}	$opt";
  list<dag> Pattern = [(int_arm_dsb (i32 imm0_15:$opt))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasDB];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2EORanonymous_3369 {	// InstAlias Requires t2InstAlias
  string AsmString = "eor${s}${p} $Rdn, $imm";
  dag ResultInst = (t2EORri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2EORanonymous_3370 {	// InstAlias Requires t2InstAlias
  string AsmString = "eor${s}${p}.w $Rdn, $Rm";
  dag ResultInst = (t2EORrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2EORanonymous_3371 {	// InstAlias Requires t2InstAlias
  string AsmString = "eor${s}${p}.w $Rdn, $shift";
  dag ResultInst = (t2EORrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2EORanonymous_3372 {	// InstAlias Requires t2InstAlias
  string AsmString = "eor${s}${p}.w $Rd, $Rn, $imm";
  dag ResultInst = (t2EORri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2EORanonymous_3373 {	// InstAlias Requires t2InstAlias
  string AsmString = "eor${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2EORrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2EORanonymous_3374 {	// InstAlias Requires t2InstAlias
  string AsmString = "eor${s}${p} $Rd, $Rn, $shift";
  dag ResultInst = (t2EORrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2EORanonymous_3375 {	// InstAlias Requires t2InstAlias
  string AsmString = "eor${s}${p}.w $Rdn, $imm";
  dag ResultInst = (t2EORri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2EORanonymous_3376 {	// InstAlias Requires t2InstAlias
  string AsmString = "eor${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2EORrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2EORanonymous_3377 {	// InstAlias Requires t2InstAlias
  string AsmString = "eor${s}${p} $Rdn, $shift";
  dag ResultInst = (t2EORrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2EORri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 0, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "eor${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (xor rGPR:$Rn, t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2EORrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "eor${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (xor rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2EORrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "eor${s}${p}.w	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set rGPR:$Rd, (xor rGPR:$Rn, t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ERET {	// InstAlias Requires
  string AsmString = "eret${p}";
  dag ResultInst = (t2SUBS_PC_LR 0, pred:$p);
  int EmitPriority = 1;
  list<Predicate> Predicates = [IsThumb2, HasVirtualization];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2HINT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_239:$imm, pred:$p);
  string AsmString = "hint${p}.w	$imm";
  list<dag> Pattern = [(int_arm_hint imm0_239:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> imm = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2HVC {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, imm16{15}, imm16{14}, imm16{13}, imm16{12}, 1, 0, 0, 0, imm16{11}, imm16{10}, imm16{9}, imm16{8}, imm16{7}, imm16{6}, imm16{5}, imm16{4}, imm16{3}, imm16{2}, imm16{1}, imm16{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_65535:$imm16);
  string AsmString = "hvc.w	$imm16";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasVirtualization];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<16> imm16 = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ISB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, opt{3}, opt{2}, opt{1}, opt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins instsyncb_opt:$opt, pred:$p);
  string AsmString = "isb${p}	$opt";
  list<dag> Pattern = [(int_arm_isb (i32 imm0_15:$opt))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasDB];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2IT {	// Instruction InstTemplate Encoding InstARM Thumb2XI ComplexDeprecationPredicate
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, cc{3}, cc{2}, cc{1}, cc{0}, mask{3}, mask{2}, mask{1}, mask{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins it_pred:$cc, it_mask:$mask);
  string AsmString = "it$mask	$cc";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [ITSTATE];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 2;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUx;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeIT";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string ComplexDeprecationPredicate = "IT";
  bits<4> cc = { ?, ?, ?, ? };
  bits<4> mask = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2Int_eh_sjlj_setjmp {	// Instruction InstTemplate Encoding InstARM Thumb2XI Requires
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$src, tGPR:$val);
  string AsmString = "";
  list<dag> Pattern = [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))];
  list<Register> Uses = [];
  list<Register> Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15];
  list<Predicate> Predicates = [IsThumb2, HasVFP2];
  int Size = 0;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2Int_eh_sjlj_setjmp_nofp {	// Instruction InstTemplate Encoding InstARM Thumb2XI Requires
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$src, tGPR:$val);
  string AsmString = "";
  list<dag> Pattern = [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))];
  list<Register> Uses = [];
  list<Register> Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR];
  list<Predicate> Predicates = [IsThumb2, NoVFP];
  int Size = 0;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LDA {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires T2Ildacq Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "lda${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDAB {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires T2Ildacq Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldab${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDAEX {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldaex${p}	$Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDAEXB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_ldrex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldaexb${p}	$Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDAEXD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_ldrex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, 1, 1, 1, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt, rGPR:$Rt2);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldaexd${p}	$Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDAEXH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_ldrex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldaexh${p}	$Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDAH {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires T2Ildacq Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldah${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC2L_OFFSET {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 1, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "ldc2l${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC2L_OPTION {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "ldc2l${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC2L_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, offset{8}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "ldc2l${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC2L_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 1, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "ldc2l${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC2_OFFSET {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "ldc2${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC2_OPTION {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "ldc2${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC2_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, offset{8}, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "ldc2${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC2_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "ldc2${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDCL_OFFSET {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 1, addr{8}, 1, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "ldcl${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDCL_OPTION {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "ldcl${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDCL_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, offset{8}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "ldcl${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDCL_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 1, addr{8}, 1, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "ldcl${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC_OFFSET {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 1, addr{8}, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "ldc${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC_OPTION {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "ldc${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, offset{8}, 0, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "ldc${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDC_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 1, addr{8}, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "ldc${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDMDB {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmdb${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDMDB_UPD {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XIt
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldmdb${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDMIA {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldm${p}.w	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDMIA_RET {	// Instruction InstTemplate PseudoInst t2PseudoInst PseudoInstExpansion t2PseudoExpand RegConstraint
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mBr;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs);
  string NAME = ?;
}
def t2LDMIA_UPD {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XIt
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, regs{15}, regs{14}, regs{13}, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldm${p}.w	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRBT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched T2IldT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_posimm8:$addr, pred:$p);
  string AsmString = "ldrbt${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadT";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRB_POST {	// Instruction InstTemplate Encoding InstARM T2Ipostldst
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, offset{8}, 1, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $Rn$offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRB_PRE {	// Instruction InstTemplate Encoding InstARM T2Ipreldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins t2addrmode_imm8_pre:$addr, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRBi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "ldrb${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi8 t2addrmode_imm12:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm12";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRBi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi8 t2addrmode_negimm8:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm8";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRBpci {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ipc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, addr{12}, 0, 0, 1, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2ldrlabel:$addr, pred:$p);
  string AsmString = "ldrb${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi8 (ARMWrapper tconstpool:$addr)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadLabel";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_pc;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRBpcrel {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  string AsmString = "ldrb${p} $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LDRBs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, addr{9}, addr{8}, addr{7}, addr{6}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "ldrb${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi8 t2addrmode_so_reg:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_si;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadShift";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRConstPool {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, const_pool_asm_imm:$immediate, pred:$p);
  string AsmString = "ldr${p} $Rt, $immediate";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LDRD_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8s4post Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, imm{8}, 1, 1, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb);
  dag InOperandList = (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm, pred:$p);
  string AsmString = "ldrd${p}	$Rt, $Rt2, $addr$imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_d_ru;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$addr.base = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8s4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<9> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRD_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8s4 Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, addr{8}, 1, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb);
  dag InOperandList = (ins t2addrmode_imm8s4_pre:$addr, pred:$p);
  string AsmString = "ldrd${p}	$Rt, $Rt2, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_d_ru;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$addr.base = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LDRDPreInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8s4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRDi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8s4 Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, addr{8}, 1, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt, rGPR:$Rt2);
  dag InOperandList = (ins t2addrmode_imm8s4:$addr, pred:$p);
  string AsmString = "ldrd${p}	$Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_d_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8s4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDREX {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, addr{11}, addr{10}, addr{9}, addr{8}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_imm0_1020s4:$addr, pred:$p);
  string AsmString = "ldrex${p}	$Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<12> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDREXB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_ldrex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldrexb${p}	$Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDREXD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_ldrex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, 0, 1, 1, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt, rGPR:$Rt2);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldrexd${p}	$Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDREXH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_ldrex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins addr_offset_none:$addr, pred:$p);
  string AsmString = "ldrexh${p}	$Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRHT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched T2IldT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_posimm8:$addr, pred:$p);
  string AsmString = "ldrht${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadT";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRH_POST {	// Instruction InstTemplate Encoding InstARM T2Ipostldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, offset{8}, 1, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "ldrh${p}	$Rt, $Rn$offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$Rn = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRH_PRE {	// Instruction InstTemplate Encoding InstARM T2Ipreldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins t2addrmode_imm8_pre:$addr, pred:$p);
  string AsmString = "ldrh${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRHi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "ldrh${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi16 t2addrmode_imm12:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm12";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRHi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "ldrh${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi16 t2addrmode_negimm8:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm8";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRHpci {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ipc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, addr{12}, 0, 1, 1, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2ldrlabel:$addr, pred:$p);
  string AsmString = "ldrh${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi16 (ARMWrapper tconstpool:$addr)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadLabel";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_pc;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRHpcrel {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  string AsmString = "ldrh${p} $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LDRHs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, addr{9}, addr{8}, addr{7}, addr{6}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "ldrh${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (zextloadi16 t2addrmode_so_reg:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_si;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadShift";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSBT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched T2IldT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_posimm8:$addr, pred:$p);
  string AsmString = "ldrsbt${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadT";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSB_POST {	// Instruction InstTemplate Encoding InstARM T2Ipostldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, offset{8}, 1, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "ldrsb${p}	$Rt, $Rn$offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$Rn = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSB_PRE {	// Instruction InstTemplate Encoding InstARM T2Ipreldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins t2addrmode_imm8_pre:$addr, pred:$p);
  string AsmString = "ldrsb${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSBi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "ldrsb${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (sextloadi8 t2addrmode_imm12:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm12";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSBi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "ldrsb${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (sextloadi8 t2addrmode_negimm8:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm8";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSBpci {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ipc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, addr{12}, 0, 0, 1, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2ldrlabel:$addr, pred:$p);
  string AsmString = "ldrsb${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (sextloadi8 (ARMWrapper tconstpool:$addr)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadLabel";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_pc;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSBpcrel {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  string AsmString = "ldrsb${p} $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LDRSBs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, addr{9}, addr{8}, addr{7}, addr{6}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "ldrsb${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (sextloadi8 t2addrmode_so_reg:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_si;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadShift";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSHT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched T2IldT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_posimm8:$addr, pred:$p);
  string AsmString = "ldrsht${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadT";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSH_POST {	// Instruction InstTemplate Encoding InstARM T2Ipostldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, offset{8}, 1, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "ldrsh${p}	$Rt, $Rn$offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$Rn = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSH_PRE {	// Instruction InstTemplate Encoding InstARM T2Ipreldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins t2addrmode_imm8_pre:$addr, pred:$p);
  string AsmString = "ldrsh${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSHi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "ldrsh${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (sextloadi16 t2addrmode_imm12:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm12";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSHi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "ldrsh${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (sextloadi16 t2addrmode_negimm8:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm8";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSHpci {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ipc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, addr{12}, 0, 1, 1, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2ldrlabel:$addr, pred:$p);
  string AsmString = "ldrsh${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (sextloadi16 (ARMWrapper tconstpool:$addr)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadLabel";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_pc;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRSHpcrel {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  string AsmString = "ldrsh${p} $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LDRSHs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, addr{9}, addr{8}, addr{7}, addr{6}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rt);
  dag InOperandList = (ins t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "ldrsh${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPRnopc:$Rt, (sextloadi16 t2addrmode_so_reg:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_si;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadShift";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched T2IldT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_posimm8:$addr, pred:$p);
  string AsmString = "ldrt${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadT";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDR_POST {	// Instruction InstTemplate Encoding InstARM T2Ipostldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, offset{8}, 1, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "ldr${p}	$Rt, $Rn$offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_iu;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$Rn = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDR_PRE {	// Instruction InstTemplate Encoding InstARM T2Ipreldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rn_wb);
  dag InOperandList = (ins t2addrmode_imm8_pre:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_iu;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "$addr.base = $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "ldr${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (load t2addrmode_imm12:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm12";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (load t2addrmode_negimm8:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm8";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRpci {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ipc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, addr{12}, 1, 0, 1, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins t2ldrlabel:$addr, pred:$p);
  string AsmString = "ldr${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (load (ARMWrapper tconstpool:$addr)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_i;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadLabel";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_pc;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LDRpci_pic {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$dst);
  dag InOperandList = (ins i32imm:$addr, pclabel:$cp);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), imm:$cp))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoadiALU;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LDRpcrel {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p);
  string AsmString = "ldr${p} $Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LDRs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, addr{9}, addr{8}, addr{7}, addr{6}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt);
  dag InOperandList = (ins t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "ldr${p}.w	$Rt, $addr";
  list<dag> Pattern = [(set GPR:$Rt, (load t2addrmode_so_reg:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_si;
  list<SchedReadWrite> SchedRW = [WriteLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadShift";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LEApcrel {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins i32imm:$label, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LEApcrelJT {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins i32imm:$label, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2LSLanonymous_3378 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsl${s}${p}.w $Rdn, $imm";
  dag ResultInst = (t2LSLri rGPR:$Rdn, rGPR:$Rdn, imm1_31:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSLanonymous_3379 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsl${s}${p}.w $Rdn, $Rm";
  dag ResultInst = (t2LSLrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSLanonymous_3380 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsl${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2LSLri rGPR:$Rd, rGPR:$Rn, imm1_31:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSLanonymous_3381 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsl${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2LSLrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSLanonymous_3382 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsl${s}${p} $Rdn, $imm";
  dag ResultInst = (t2LSLri rGPR:$Rdn, rGPR:$Rdn, imm1_31:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSLanonymous_3383 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsl${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2LSLrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSLri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftImm Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, s{0}, 1, 1, 1, 1, ?, imm{4}, imm{3}, imm{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{1}, imm{0}, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, imm1_31:$imm, pred:$p, cc_out:$s);
  string AsmString = "lsl${s}${p}.w	$Rd, $Rm, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (shl rGPR:$Rm, (i32 imm1_31:$imm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> imm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LSLrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "lsl${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (shl rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2LSRanonymous_3378 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsr${s}${p}.w $Rdn, $imm";
  dag ResultInst = (t2LSRri rGPR:$Rdn, rGPR:$Rdn, imm_sr:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSRanonymous_3379 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsr${s}${p}.w $Rdn, $Rm";
  dag ResultInst = (t2LSRrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSRanonymous_3380 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsr${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2LSRri rGPR:$Rd, rGPR:$Rn, imm_sr:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSRanonymous_3381 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsr${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2LSRrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSRanonymous_3382 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsr${s}${p} $Rdn, $imm";
  dag ResultInst = (t2LSRri rGPR:$Rdn, rGPR:$Rdn, imm_sr:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSRanonymous_3383 {	// InstAlias Requires t2InstAlias
  string AsmString = "lsr${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2LSRrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2LSRri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftImm Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, s{0}, 1, 1, 1, 1, ?, imm{4}, imm{3}, imm{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{1}, imm{0}, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, imm_sr:$imm, pred:$p, cc_out:$s);
  string AsmString = "lsr${s}${p}.w	$Rd, $Rm, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (srl rGPR:$Rm, (i32 imm_sr:$imm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> imm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2LSRrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "lsr${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (srl rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MCR {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop t2MovRCopro ComplexDeprecationPredicate
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, 0, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2, pred:$p);
  string AsmString = "mcr${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2";
  list<dag> Pattern = [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string ComplexDeprecationPredicate = "MCR";
  string NAME = ?;
}
def t2MCR2 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop t2MovRCopro
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, 0, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2, pred:$p);
  string AsmString = "mcr2${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2";
  list<dag> Pattern = [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, imm:$CRm, imm:$opc2)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, PreV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MCRR {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop t2MovRRCopro
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm, pred:$p);
  string AsmString = "mcrr${p}	$cop, $opc1, $Rt, $Rt2, $CRm";
  list<dag> Pattern = [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MCRR2 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop t2MovRRCopro
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm, pred:$p);
  string AsmString = "mcrr2${p}	$cop, $opc1, $Rt, $Rt2, $CRm";
  list<dag> Pattern = [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, PreV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MLA {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "mla${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MLS {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "mls${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MOVCCasr {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint Sched MOVCCShPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMcmov rGPR:$false, (sra rGPR:$Rm, (i32 imm_sr:$imm)), cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVCCi {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMcmov rGPR:$false, t2_so_imm:$imm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVCCi16 {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVCCi32imm {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$dst);
  dag InOperandList = (ins rGPR:$false, i32imm:$src, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 8;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVix2;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$false = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVCClsl {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint Sched MOVCCShPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMcmov rGPR:$false, (shl rGPR:$Rm, (i32 imm0_31:$imm)), cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVCClsr {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint Sched MOVCCShPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMcmov rGPR:$false, (srl rGPR:$Rm, (i32 imm_sr:$imm)), cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVCCr {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$false, rGPR:$Rm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 1;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVCCror {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint Sched MOVCCShPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMcmov rGPR:$false, (rotr rGPR:$Rm, (i32 imm0_31:$imm)), cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVSsi {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p);
  string AsmString = "movs${p} $Rd, $shift";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVSsr {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p);
  string AsmString = "movs${p} $Rd, $shift";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVTi16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 1, 0, 1, 1, 0, 0, imm{15}, imm{14}, imm{13}, imm{12}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$src, imm0_65535_expr:$imm, pred:$p);
  string AsmString = "movt${p}	$Rd, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (or (and rGPR:$src, 65535), lo16AllZero:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$src = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2MOVTWInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<16> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2MOVTi16_ga_pcrel {	// Instruction InstTemplate PseudoInst Sched Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$src, i32imm:$addr, pclabel:$id);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$src = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOV_ga_pcrel {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$dst);
  dag InOperandList = (ins i32imm:$addr);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline, UseMovtInPic];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVix2addpc;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVi {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sOneRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 0, 0, 1, 0, s{0}, 1, 1, 1, 1, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "mov${s}${p}.w	$Rd, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, t2_so_imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 1;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2MOVi16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 1, 0, 0, 1, 0, 0, imm{15}, imm{14}, imm{13}, imm{12}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins imm0_65535_expr:$imm, pred:$p);
  string AsmString = "movw${p}	$Rd, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, imm0_65535:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2MOVTWInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<16> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2MOVi16_ga_pcrel {	// Instruction InstTemplate PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins i32imm:$addr, pclabel:$id);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVi32imm {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$dst);
  dag InOperandList = (ins i32imm:$src);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$dst, (i32 imm:$src))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, UseMovt];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVix2;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, s{0}, 1, 1, 1, 1, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rm, pred:$p, cc_out:$s);
  string AsmString = "mov${s}${p}.w	$Rd, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MOVsi {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p);
  string AsmString = "mov${p} $Rd, $shift";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVsr {	// Instruction InstTemplate AsmPseudoInst Requires t2AsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p);
  string AsmString = "mov${p} $Rd, $shift";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MOVsra_flag {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoRegShiftImm Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, pred:$p);
  string AsmString = "asrs${p}.w	$Rd, $Rm, #1";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> imm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2MOVsrl_flag {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoRegShiftImm Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, pred:$p);
  string AsmString = "lsrs${p}.w	$Rd, $Rm, #1";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> imm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2MRC {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop t2MovRCopro
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, 1, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRwithAPSR:$Rt);
  dag InOperandList = (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2, pred:$p);
  string AsmString = "mrc${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MRC2 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop t2MovRCopro
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 1, 0, opc1{2}, opc1{1}, opc1{0}, 1, CRn{3}, CRn{2}, CRn{1}, CRn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc2{2}, opc2{1}, opc2{0}, 1, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRwithAPSR:$Rt);
  dag InOperandList = (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2, pred:$p);
  string AsmString = "mrc2${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, PreV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<3> opc1 = { ?, ?, ? };
  bits<3> opc2 = { ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  bits<4> CRn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MRRC {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop t2MovRRCopro
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, 0, 1, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rt2);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm, pred:$p);
  string AsmString = "mrrc${p}	$cop, $opc1, $Rt, $Rt2, $CRm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MRRC2 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2Cop t2MovRRCopro
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, cop{3}, cop{2}, cop{1}, cop{0}, opc1{3}, opc1{2}, opc1{1}, opc1{0}, CRm{3}, CRm{2}, CRm{1}, CRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rt, GPR:$Rt2);
  dag InOperandList = (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm, pred:$p);
  string AsmString = "mrrc2${p}	$cop, $opc1, $Rt, $Rt2, $CRm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, PreV8];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> opc1 = { ?, ?, ?, ? };
  bits<4> CRm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MRS_AR {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins pred:$p);
  string AsmString = "mrs${p}	$Rd, apsr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MRS_M {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, SYSm{7}, SYSm{6}, SYSm{5}, SYSm{4}, SYSm{3}, SYSm{2}, SYSm{1}, SYSm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins msr_mask:$SYSm, pred:$p);
  string AsmString = "mrs${p}	$Rd, $SYSm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<8> SYSm = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2MRSbanked {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, banked{5}, banked{3}, banked{2}, banked{1}, banked{0}, 1, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, banked{4}, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins banked_reg:$banked, pred:$p);
  string AsmString = "mrs${p}	$Rd, $banked";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasVirtualization];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<6> banked = { ?, ?, ?, ?, ?, ? };
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MRSsys_AR {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins pred:$p);
  string AsmString = "mrs${p}	$Rd, spsr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MSR_AR {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, mask{4}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 0, 0, 0, mask{3}, mask{2}, mask{1}, mask{0}, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins msr_mask:$mask, rGPR:$Rn, pred:$p);
  string AsmString = "msr${p}	$mask, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mask = { ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MSR_M {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 0, 0, 0, SYSm{11}, SYSm{10}, 0, 0, SYSm{7}, SYSm{6}, SYSm{5}, SYSm{4}, SYSm{3}, SYSm{2}, SYSm{1}, SYSm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins msr_mask:$SYSm, rGPR:$Rn, pred:$p);
  string AsmString = "msr${p}	$SYSm, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb, IsMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<12> SYSm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MSRbanked {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, banked{5}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 0, 0, 0, banked{3}, banked{2}, banked{1}, banked{0}, 0, 0, 1, banked{4}, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins banked_reg:$banked, rGPR:$Rn, pred:$p);
  string AsmString = "msr${p}	$banked, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasVirtualization];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<6> banked = { ?, ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MUL {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "mul${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL32;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MVNCCi {	// Instruction InstTemplate PseudoInst t2PseudoInst RegConstraint Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMcmov rGPR:$false, t2_so_imm_not:$imm, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$false = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2MVNi {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sOneRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 0, 0, 1, 1, s{0}, 1, 1, 1, 1, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "mvn${s}${p}	$Rd, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (not t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 1;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 1;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMVNi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2MVNr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, s{0}, 1, 1, 1, 1, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "mvn${s}${p}.w	$Rd, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (not rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 1;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMVNr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2MVNs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sOneRegShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, s{0}, 1, 1, 1, 1, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "mvn${s}${p}.w	$Rd, $ShiftedRm";
  list<dag> Pattern = [(set rGPR:$Rd, (not t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 1;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMVNsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ORNanonymous_3369 {	// InstAlias Requires t2InstAlias
  string AsmString = "orn${s}${p} $Rdn, $imm";
  dag ResultInst = (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ORNanonymous_3370 {	// InstAlias Requires t2InstAlias
  string AsmString = "orn${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2ORNrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ORNanonymous_3371 {	// InstAlias Requires t2InstAlias
  string AsmString = "orn${s}${p} $Rdn, $shift";
  dag ResultInst = (t2ORNrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ORNri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 0, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "orn${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (anonymous_3460 rGPR:$Rn, t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ORNrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "orn${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (anonymous_3460 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2ORNrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "orn${s}${p}	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set rGPR:$Rd, (anonymous_3460 rGPR:$Rn, t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2ORRanonymous_3369 {	// InstAlias Requires t2InstAlias
  string AsmString = "orr${s}${p} $Rdn, $imm";
  dag ResultInst = (t2ORRri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ORRanonymous_3370 {	// InstAlias Requires t2InstAlias
  string AsmString = "orr${s}${p}.w $Rdn, $Rm";
  dag ResultInst = (t2ORRrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ORRanonymous_3371 {	// InstAlias Requires t2InstAlias
  string AsmString = "orr${s}${p}.w $Rdn, $shift";
  dag ResultInst = (t2ORRrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ORRanonymous_3372 {	// InstAlias Requires t2InstAlias
  string AsmString = "orr${s}${p}.w $Rd, $Rn, $imm";
  dag ResultInst = (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ORRanonymous_3373 {	// InstAlias Requires t2InstAlias
  string AsmString = "orr${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2ORRrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ORRanonymous_3374 {	// InstAlias Requires t2InstAlias
  string AsmString = "orr${s}${p} $Rd, $Rn, $shift";
  dag ResultInst = (t2ORRrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ORRanonymous_3375 {	// InstAlias Requires t2InstAlias
  string AsmString = "orr${s}${p}.w $Rdn, $imm";
  dag ResultInst = (t2ORRri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ORRanonymous_3376 {	// InstAlias Requires t2InstAlias
  string AsmString = "orr${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2ORRrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ORRanonymous_3377 {	// InstAlias Requires t2InstAlias
  string AsmString = "orr${s}${p} $Rdn, $shift";
  dag ResultInst = (t2ORRrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2ORRri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 0, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "orr${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (or rGPR:$Rn, t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ORRrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "orr${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (or rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2ORRrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "orr${s}${p}.w	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set rGPR:$Rd, (or rGPR:$Rn, t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> T2I_bin_w_irs::opcod = { ?, ?, ?, ? };
  string T2I_bin_w_irs::opc = ?;
  InstrItinClass T2I_bin_w_irs::iii = ?;
  InstrItinClass T2I_bin_w_irs::iir = ?;
  InstrItinClass T2I_bin_w_irs::iis = ?;
  SDPatternOperator T2I_bin_w_irs::opnode = ?;
  bit T2I_bin_w_irs::Commutable = 0;
  string NAME = ?;
}
def t2PKHBT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, sh{4}, sh{3}, sh{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{1}, sh{0}, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh, pred:$p);
  string AsmString = "pkhbt${p}	$Rd, $Rn, $Rm$sh";
  list<dag> Pattern = [(set rGPR:$Rd, (or (and rGPR:$Rn, 65535), (and (shl rGPR:$Rm, pkh_lsl_amt:$sh), 4294901760)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> sh = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PKHTB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, sh{4}, sh{3}, sh{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{1}, sh{0}, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh, pred:$p);
  string AsmString = "pkhtb${p}	$Rd, $Rn, $Rm$sh";
  list<dag> Pattern = [(set rGPR:$Rd, (or (and rGPR:$Rn, 4294901760), (and (sra rGPR:$Rm, pkh_asr_amt:$sh), 65535)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> sh = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLDWi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, addr{16}, addr{15}, addr{14}, addr{13}, 1, 1, 1, 1, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "pldw${p}	$addr";
  list<dag> Pattern = [(ARMPreload t2addrmode_imm12:$addr, (i32 1), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV7, HasMP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm12";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLDWi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, addr{12}, addr{11}, addr{10}, addr{9}, 1, 1, 1, 1, 1, 1, 0, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "pldw${p}	$addr";
  list<dag> Pattern = [(ARMPreload t2addrmode_negimm8:$addr, (i32 1), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV7, HasMP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm8";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLDWs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, addr{9}, addr{8}, addr{7}, addr{6}, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "pldw${p}	$addr";
  list<dag> Pattern = [(ARMPreload t2addrmode_so_reg:$addr, (i32 1), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV7, HasMP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadShift";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLDi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, 1, 1, 1, 1, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "pld${p}	$addr";
  list<dag> Pattern = [(ARMPreload t2addrmode_imm12:$addr, (i32 0), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm12";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLDi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, 1, 1, 1, 1, 1, 1, 0, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "pld${p}	$addr";
  list<dag> Pattern = [(ARMPreload t2addrmode_negimm8:$addr, (i32 0), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm8";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLDpci {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched T2Iplpci Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, addr{12}, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2ldrlabel:$addr, pred:$p);
  string AsmString = "pld${p}	$addr";
  list<dag> Pattern = [(ARMPreload (ARMWrapper tconstpool:$addr), (i32 0), (i32 { 0 }))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadLabel";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLDs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, addr{9}, addr{8}, addr{7}, addr{6}, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "pld${p}	$addr";
  list<dag> Pattern = [(ARMPreload t2addrmode_so_reg:$addr, (i32 0), (i32 0))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadShift";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLIi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, addr{16}, addr{15}, addr{14}, addr{13}, 1, 1, 1, 1, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "pli${p}	$addr";
  list<dag> Pattern = [(ARMPreload t2addrmode_imm12:$addr, (i32 0), (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV7];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm12";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<17> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLIi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, addr{12}, addr{11}, addr{10}, addr{9}, 1, 1, 1, 1, 1, 1, 0, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "pli${p}	$addr";
  list<dag> Pattern = [(ARMPreload t2addrmode_negimm8:$addr, (i32 0), (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV7];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadImm8";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLIpci {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched T2Iplpci Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, addr{12}, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2ldrlabel:$addr, pred:$p);
  string AsmString = "pli${p}	$addr";
  list<dag> Pattern = [(ARMPreload (ARMWrapper tconstpool:$addr), (i32 0), (i32 { 1 }))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV7];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadLabel";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2PLIs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, addr{9}, addr{8}, addr{7}, addr{6}, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "pli${p}	$addr";
  list<dag> Pattern = [(ARMPreload t2addrmode_so_reg:$addr, (i32 0), (i32 1))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV7];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Preload;
  list<SchedReadWrite> SchedRW = [WritePreLd];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LoadShift";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2QADD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics_rev
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rGPR:$Rn, pred:$p);
  string AsmString = "qadd${p}	$Rd, $Rm, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2QADD16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "qadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_qadd16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2QADD8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "qadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_qadd8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2QASX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "qasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_qasx rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2QDADD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics_rev
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rGPR:$Rn, pred:$p);
  string AsmString = "qdadd${p}	$Rd, $Rm, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2QDSUB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics_rev
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rGPR:$Rn, pred:$p);
  string AsmString = "qdsub${p}	$Rd, $Rm, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2QSAX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "qsax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_qsax rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2QSUB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics_rev
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rGPR:$Rn, pred:$p);
  string AsmString = "qsub${p}	$Rd, $Rm, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2QSUB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "qsub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_qsub16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2QSUB8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "qsub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_qsub8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2RBIT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2I_misc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, pred:$p);
  string AsmString = "rbit${p}	$Rd, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (bitreverse rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2REV {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2I_misc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, pred:$p);
  string AsmString = "rev${p}.w	$Rd, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (bswap rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2REV16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2I_misc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, pred:$p);
  string AsmString = "rev16${p}.w	$Rd, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2REVSH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2I_misc Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, pred:$p);
  string AsmString = "revsh${p}.w	$Rd, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2RFEDB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2RFE
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p);
  string AsmString = "rfedb${p}	$Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [PC];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2RFEDBW {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2RFE
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p);
  string AsmString = "rfedb${p}	$Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [PC];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2RFEIA {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2RFE
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p);
  string AsmString = "rfeia${p}	$Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [PC];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2RFEIAW {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2RFE
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p);
  string AsmString = "rfeia${p}	$Rn!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [PC];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2RORanonymous_3378 {	// InstAlias Requires t2InstAlias
  string AsmString = "ror${s}${p}.w $Rdn, $imm";
  dag ResultInst = (t2RORri rGPR:$Rdn, rGPR:$Rdn, imm0_31:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2RORanonymous_3379 {	// InstAlias Requires t2InstAlias
  string AsmString = "ror${s}${p}.w $Rdn, $Rm";
  dag ResultInst = (t2RORrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2RORanonymous_3380 {	// InstAlias Requires t2InstAlias
  string AsmString = "ror${s}${p} $Rd, $Rn, $imm";
  dag ResultInst = (t2RORri rGPR:$Rd, rGPR:$Rn, imm0_31:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2RORanonymous_3381 {	// InstAlias Requires t2InstAlias
  string AsmString = "ror${s}${p} $Rd, $Rn, $Rm";
  dag ResultInst = (t2RORrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2RORanonymous_3382 {	// InstAlias Requires t2InstAlias
  string AsmString = "ror${s}${p} $Rdn, $imm";
  dag ResultInst = (t2RORri rGPR:$Rdn, rGPR:$Rdn, imm0_31:$imm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2RORanonymous_3383 {	// InstAlias Requires t2InstAlias
  string AsmString = "ror${s}${p} $Rdn, $Rm";
  dag ResultInst = (t2RORrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2RORri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftImm Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, s{0}, 1, 1, 1, 1, ?, imm{4}, imm{3}, imm{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{1}, imm{0}, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s);
  string AsmString = "ror${s}${p}.w	$Rd, $Rm, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (rotr rGPR:$Rm, (i32 imm0_31:$imm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<5> imm = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2RORrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "ror${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (rotr rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2RRX {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, s{0}, 1, 1, 1, 1, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "rrx${s}${p}	$Rd, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2RSBSri {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMsubc t2_so_imm:$imm, rGPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2RSBSrs {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMsubc t2_so_reg:$ShiftedRm, rGPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2RSBri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 1, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "rsb${s}${p}.w	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, (sub t2_so_imm:$imm, rGPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2RSBrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "rsb${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2RSBrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "rsb${s}${p}	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set rGPR:$Rd, (sub t2_so_reg:$ShiftedRm, rGPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsir;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SADD16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "sadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_sadd16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SADD8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "sadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_sadd8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SASX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "sasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_sasx rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SBCri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 1, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "sbc${s}${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMsube rGPR:$Rn, t2_so_imm:$imm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SBCrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "sbc${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMsube rGPR:$Rn, rGPR:$Rm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SBCrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "sbc${s}${p}.w	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMsube rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SBFX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2BitFI T2TwoRegBitFI
  field bits<32> Inst = { 1, 1, 1, 1, 0, ?, 1, 1, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, lsb{4}, lsb{3}, lsb{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, lsb{1}, lsb{0}, ?, msb{4}, msb{3}, msb{2}, msb{1}, msb{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb, pred:$p);
  string AsmString = "sbfx${p}	$Rd, $Rn, $lsb, $msb";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAsi;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<5> msb = { ?, ?, ?, ?, ? };
  bits<5> lsb = { ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SDIV {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "sdiv${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDivideInThumb, IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iDIV;
  list<SchedReadWrite> SchedRW = [WriteDIV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SEL {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "sel${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SETPAN {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Misc Requires
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, imm{0}, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_1:$imm);
  string AsmString = "setpan	$imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasV8, HasV8_1a];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> imm = { ? };
  string NAME = ?;
}
def t2SG {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "sg${p}";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [Has8MSecExt];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2SHADD16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "shadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_shadd16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SHADD8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "shadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_shadd8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SHASX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "shasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_shasx rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SHSAX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "shsax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_shsax rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SHSUB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "shsub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_shsub16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SHSUB8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "shsub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_shsub8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMC {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, opt{3}, opt{2}, opt{1}, opt{0}, 1, 0, 0, 0, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_15:$opt, pred:$p);
  string AsmString = "smc${p}	$opt";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasTrustZone];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> opt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLABB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smlabb${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16), (sext_inreg rGPR:$Rm, i16))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLABT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smlabt${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16), (sra rGPR:$Rm, (i32 16)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLAD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac Requires T2DualHalfMulAdd
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smlad${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_smlad rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLADX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac Requires T2DualHalfMulAdd
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smladx${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_smladx rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLAL {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I RegConstraint Sched T2MlaLong
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "smlal${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLALBB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I RegConstraint Sched T2MlaLong Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, 1, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "smlalbb${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLALBT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I RegConstraint Sched T2MlaLong Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "smlalbt${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLALD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac RegConstraint Requires Sched T2DualHalfMulAddLong
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Ra, rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "smlald${p}	$Ra, $Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$Ra = $RLo, $Rd = $RHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLALDX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac RegConstraint Requires Sched T2DualHalfMulAddLong
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Ra, rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "smlaldx${p}	$Ra, $Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$Ra = $RLo, $Rd = $RHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLALTB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I RegConstraint Sched T2MlaLong Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, 1, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "smlaltb${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLALTT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I RegConstraint Sched T2MlaLong Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, 1, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "smlaltt${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLATB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smlatb${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)), (sext_inreg rGPR:$Rm, i16))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLATT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smlatt${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)), (sra rGPR:$Rm, (i32 16)))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLAWB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smlawb${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLAWT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smlawt${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMAC16, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLSD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac Requires T2DualHalfMulAdd
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smlsd${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_smlsd rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLSDX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac Requires T2DualHalfMulAdd
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smlsdx${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_smlsdx rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLSLD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac RegConstraint Requires Sched T2DualHalfMulAddLong
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Ra, rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "smlsld${p}	$Ra, $Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$Ra = $RLo, $Rd = $RHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMLSLDX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac RegConstraint Requires Sched T2DualHalfMulAddLong
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Ra, rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "smlsldx${p}	$Ra, $Rd, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$Ra = $RLo, $Rd = $RHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMMLA {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smmla${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMMLAR {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smmlar${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMMLS {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smmls${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMMLSR {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg Requires Sched T2FourRegSMMLA
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "smmlsr${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMsmmlsr rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP, UseMulOps];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMMUL {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2SMMUL
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smmul${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL32;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMMULR {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2SMMUL
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smmulr${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, (i32 0)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL32;
  list<SchedReadWrite> SchedRW = [WriteMUL32, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMUAD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2ThreeReg_mac Requires Sched T2DualHalfMul
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smuad${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_smuad rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMUADX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2ThreeReg_mac Requires Sched T2DualHalfMul
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smuadx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_smuadx rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMULBB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2ThreeRegSMUL
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smulbb${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16), (sext_inreg rGPR:$Rm, i16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMULBT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2ThreeRegSMUL
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smulbt${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16), (sra rGPR:$Rm, (i32 16))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMULL {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched T2MulLong
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smull${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$RdLo, rGPR:$RdHi, (smullohi rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL64;
  list<SchedReadWrite> SchedRW = [WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMULTB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2ThreeRegSMUL
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smultb${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)), (sext_inreg rGPR:$Rm, i16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMULTT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2ThreeRegSMUL
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smultt${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)), (sra rGPR:$Rm, (i32 16))))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMULWB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2ThreeRegSMUL
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smulwb${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMULWT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2ThreeRegSMUL
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smulwt${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL16;
  list<SchedReadWrite> SchedRW = [WriteMUL16, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMUSD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2ThreeReg_mac Requires Sched T2DualHalfMul
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smusd${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_smusd rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SMUSDX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2ThreeReg_mac Requires Sched T2DualHalfMul
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "smusdx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_smusdx rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC32;
  list<SchedReadWrite> SchedRW = [WriteMAC32, ReadMUL, ReadMUL, ReadMAC];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SRSDB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2SRS
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode, pred:$p);
  string AsmString = "srsdb${p}	sp, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SRSDB_UPD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2SRS
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode, pred:$p);
  string AsmString = "srsdb${p}	sp!, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SRSIA {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2SRS
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode, pred:$p);
  string AsmString = "srsia${p}	sp, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SRSIA_UPD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2SRS
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, mode{4}, mode{3}, mode{2}, mode{1}, mode{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_31:$mode, pred:$p);
  string AsmString = "srsia${p}	sp!, $mode";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<5> mode = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SSAT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2SatI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, sh{5}, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, sh{4}, sh{3}, sh{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{1}, sh{0}, 0, sat_imm{4}, sat_imm{3}, sat_imm{2}, sat_imm{1}, sat_imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh, pred:$p);
  string AsmString = "ssat${p}	$Rd, $sat_imm, $Rn$sh";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<5> sat_imm = { ?, ?, ?, ?, ? };
  bits<6> sh = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SSAT16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2SatI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, sat_imm{3}, sat_imm{2}, sat_imm{1}, sat_imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins imm1_16:$sat_imm, rGPR:$Rn, pred:$p);
  string AsmString = "ssat16${p}	$Rd, $sat_imm, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<5> sat_imm = { ?, ?, ?, ?, ? };
  bits<6> sh = { 1, 0, 0, 0, 0, 0 };
  string NAME = ?;
}
def t2SSAX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "ssax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_ssax rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SSUB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "ssub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_ssub16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SSUB8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "ssub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_ssub8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC2L_OFFSET {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 1, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "stc2l${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC2L_OPTION {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "stc2l${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC2L_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, offset{8}, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "stc2l${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC2L_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 1, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "stc2l${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC2_OFFSET {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 0, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "stc2${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC2_OPTION {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "stc2${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC2_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 0, offset{8}, 0, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "stc2${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC2_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 1, 0, 1, addr{8}, 0, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "stc2${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [PreV8, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STCL_OFFSET {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 1, addr{8}, 1, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "stcl${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STCL_OPTION {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "stcl${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STCL_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, offset{8}, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "stcl${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STCL_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 1, addr{8}, 1, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "stcl${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC_OFFSET {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 1, addr{8}, 0, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr, pred:$p);
  string AsmString = "stc${p}	$cop, $CRd, $addr";
  list<dag> Pattern = [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC_OPTION {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, option{7}, option{6}, option{5}, option{4}, option{3}, option{2}, option{1}, option{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option, pred:$p);
  string AsmString = "stc${p}	$cop, $CRd, $addr, $option";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> option = { ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 0, offset{8}, 0, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset, pred:$p);
  string AsmString = "stc${p}	$cop, $CRd, $addr, $offset";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STC_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2CI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 1, 0, 1, addr{8}, 0, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, CRd{3}, CRd{2}, CRd{1}, CRd{0}, cop{3}, cop{2}, cop{1}, cop{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr, pred:$p);
  string AsmString = "stc${p}	$cop, $CRd, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2CoProc";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeCopMemInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  bits<4> cop = { ?, ?, ?, ? };
  bits<4> CRd = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STL {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires Sched T2Istrrel
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stl${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STLB {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires Sched T2Istrrel
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlb${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STLEX {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 1, 1, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlex${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rd, (stlex_4 rGPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STLEXB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_strex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 1, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlexb${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rd, (stlex_1 rGPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STLEXD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_strex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlexd${p}	$Rd, $Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STLEXH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_strex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 1, 0, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlexh${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rd, (stlex_2 rGPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STLH {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires Sched T2Istrrel
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "stlh${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasAcquireRelease];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STMDB {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, regs{14}, 0, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmdb${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STMDB_UPD {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XIt
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, regs{14}, 0, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stmdb${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STMIA {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, regs{14}, 0, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stm${p}.w	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STMIA_UPD {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XIt
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, regs{14}, 0, regs{12}, regs{11}, regs{10}, regs{9}, regs{8}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stm${p}.w	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRBT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched T2IstT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_imm8:$addr, pred:$p);
  string AsmString = "strbt${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_i;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRB_POST {	// Instruction InstTemplate Encoding InstARM T2Ipostldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, offset{8}, 1, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rn_wb);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "strb${p}	$Rt, $Rn$offset";
  list<dag> Pattern = [(set GPRnopc:$Rn_wb, (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRB_PRE {	// Instruction InstTemplate Encoding InstARM T2Ipreldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rn_wb);
  dag InOperandList = (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p);
  string AsmString = "strb${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRB_preidx {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rn_wb);
  dag InOperandList = (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPRnopc:$Rn_wb, (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2STRBi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "strb${p}.w	$Rt, $addr";
  list<dag> Pattern = [(truncstorei8 rGPR:$Rt, t2addrmode_imm12:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_i;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, 1, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRBi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "strb${p}	$Rt, $addr";
  list<dag> Pattern = [(truncstorei8 rGPR:$Rt, t2addrmode_negimm8:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_i;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRBs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, addr{9}, addr{8}, addr{7}, addr{6}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "strb${p}.w	$Rt, $addr";
  list<dag> Pattern = [(truncstorei8 rGPR:$Rt, t2addrmode_so_reg:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_si;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRD_POST {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8s4post Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, imm{8}, 1, 1, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr, t2am_imm8s4_offset:$imm, pred:$p);
  string AsmString = "strd${p}	$Rt, $Rt2, $addr$imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_d_ru;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$addr.base = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8s4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<9> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRD_PRE {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8s4 Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, addr{8}, 1, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr, pred:$p);
  string AsmString = "strd${p}	$Rt, $Rt2, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_d_ru;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$addr.base = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2STRDPreInstruction";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8s4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRDi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8s4 Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 1, addr{8}, 1, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr, pred:$p);
  string AsmString = "strd${p}	$Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_d_r;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8s4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STREX {	// Instruction InstTemplate Encoding InstARM Thumb2I Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, addr{11}, addr{10}, addr{9}, addr{8}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rt, t2addrmode_imm0_1020s4:$addr, pred:$p);
  string AsmString = "strex${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rd, (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<12> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STREXB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_strex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 0, 1, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "strexb${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rd, (strex_1 rGPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STREXD {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_strex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, Rt2{3}, Rt2{2}, Rt2{1}, Rt2{0}, 0, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr, pred:$p);
  string AsmString = "strexd${p}	$Rd, $Rt, $Rt2, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rt2 = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STREXH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I_strex Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, addr{3}, addr{2}, addr{1}, addr{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 1, 0, 1, 0, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$addr, pred:$p);
  string AsmString = "strexh${p}	$Rd, $Rt, $addr";
  list<dag> Pattern = [(set rGPR:$Rd, (strex_2 rGPR:$Rt, addr_offset_none:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "@earlyclobber $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> addr = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRHT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched T2IstT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_imm8:$addr, pred:$p);
  string AsmString = "strht${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_i;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRH_POST {	// Instruction InstTemplate Encoding InstARM T2Ipostldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, offset{8}, 1, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rn_wb);
  dag InOperandList = (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "strh${p}	$Rt, $Rn$offset";
  list<dag> Pattern = [(set GPRnopc:$Rn_wb, (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_iu;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRH_PRE {	// Instruction InstTemplate Encoding InstARM T2Ipreldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rn_wb);
  dag InOperandList = (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p);
  string AsmString = "strh${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_iu;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRH_preidx {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rn_wb);
  dag InOperandList = (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPRnopc:$Rn_wb, (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2STRHi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "strh${p}.w	$Rt, $addr";
  list<dag> Pattern = [(truncstorei16 rGPR:$Rt, t2addrmode_imm12:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_i;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, 1, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRHi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "strh${p}	$Rt, $addr";
  list<dag> Pattern = [(truncstorei16 rGPR:$Rt, t2addrmode_negimm8:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_i;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRHs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, addr{9}, addr{8}, addr{7}, addr{6}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "strh${p}.w	$Rt, $addr";
  list<dag> Pattern = [(truncstorei16 rGPR:$Rt, t2addrmode_so_reg:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_si;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched T2IstT
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins t2addrmode_imm8:$addr, pred:$p);
  string AsmString = "strt${p}	$Rt, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_i;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STR_POST {	// Instruction InstTemplate Encoding InstARM T2Ipostldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, offset{8}, 1, offset{7}, offset{6}, offset{5}, offset{4}, offset{3}, offset{2}, offset{1}, offset{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rn_wb);
  dag InOperandList = (ins GPRnopc:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "str${p}	$Rt, $Rn$offset";
  list<dag> Pattern = [(set GPRnopc:$Rn_wb, (post_store GPRnopc:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_iu;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePost;
  bits<2> IndexModeBits = { 1, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<9> offset = { ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STR_PRE {	// Instruction InstTemplate Encoding InstARM T2Ipreldst Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rn_wb);
  dag InOperandList = (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr, pred:$p);
  string AsmString = "str${p}	$Rt, $addr!";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_iu;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$addr.base = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeT2LdStPre";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModePre;
  bits<2> IndexModeBits = { 0, 1 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STR_preidx {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rn_wb);
  dag InOperandList = (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set GPRnopc:$Rn_wb, (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2STRi12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii12 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, addr{16}, addr{15}, addr{14}, addr{13}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, addr{11}, addr{10}, addr{9}, addr{8}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, t2addrmode_imm12:$addr, pred:$p);
  string AsmString = "str${p}.w	$Rt, $addr";
  list<dag> Pattern = [(store GPR:$Rt, t2addrmode_imm12:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_i;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i12;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<17> addr = { ?, ?, ?, ?, 1, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRi8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Ii8 Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, addr{12}, addr{11}, addr{10}, addr{9}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, addr{8}, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p);
  string AsmString = "str${p}	$Rt, $addr";
  list<dag> Pattern = [(store GPR:$Rt, t2addrmode_negimm8:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_i;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_i8;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<13> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2STRs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2Iso Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, addr{9}, addr{8}, addr{7}, addr{6}, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 0, 0, addr{1}, addr{0}, addr{5}, addr{4}, addr{3}, addr{2} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p);
  string AsmString = "str${p}.w	$Rt, $addr";
  list<dag> Pattern = [(store GPR:$Rt, t2addrmode_so_reg:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_si;
  list<SchedReadWrite> SchedRW = [WriteST];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT2_so;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rt = { ?, ?, ?, ? };
  bits<10> addr = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SUBS_PC_LR {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 1, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_255:$imm, pred:$p);
  string AsmString = "subs${p}	pc, lr, $imm";
  list<dag> Pattern = [(ARMintretflag imm0_255:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [PC];
  list<Predicate> Predicates = [IsThumb2, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> imm = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SUBSri {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMsubc GPRnopc:$Rn, t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2SUBSrr {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMsubc GPRnopc:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2SUBSrs {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set rGPR:$Rd, CPSR, (ARMsubc GPRnopc:$Rn, t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALUsr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2SUBri {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 1, 1, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s);
  string AsmString = "sub${s}${p}.w	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (sub GPRnopc:$Rn, t2_so_imm:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SUBri12 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 1, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPR:$Rn, imm0_4095:$imm, pred:$p);
  string AsmString = "subw${p}	$Rd, $Rn, $imm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (sub GPR:$Rn, imm0_4095:$imm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SUBrr {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sThreeReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s);
  string AsmString = "sub${s}${p}.w	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (sub GPRnopc:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2SUBrs {	// Instruction InstTemplate Encoding InstARM Thumb2sI T2sI T2sTwoRegShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, 1, s{0}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRnopc:$Rd);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s);
  string AsmString = "sub${s}${p}.w	$Rd, $Rn, $ShiftedRm";
  list<dag> Pattern = [(set GPRnopc:$Rd, (sub GPRnopc:$Rn, t2_so_reg:$ShiftedRm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUsi;
  list<SchedReadWrite> SchedRW = [WriteALUsi, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<1> s = { ? };
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2SXTAB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2I_exta_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtab${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAsr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2SXTAB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2I_exta_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtab16${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAsr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2SXTAH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2I_exta_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtah${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAsr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2SXTB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoReg T2I_ext_rrot_base Requires Sched T2I_ext_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtb${p}.w	$Rd, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2SXTB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoReg T2I_ext_rrot_base Requires Sched T2I_ext_rrot_xtb16
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxtb16${p}	$Rd, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2SXTH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoReg T2I_ext_rrot_base Requires Sched T2I_ext_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "sxth${p}.w	$Rd, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2TBB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode_tbb:$addr, pred:$p);
  string AsmString = "tbb${p}	$addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrTbl];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumbTableBranch";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2TBB_JT {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2TBH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins addrmode_tbh:$addr, pred:$p);
  string AsmString = "tbh${p}	$addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrTbl];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumbTableBranch";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2TBH_JT {	// Instruction InstTemplate PseudoInst t2PseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t2TEQanonymous_3384 {	// InstAlias Requires t2InstAlias
  string AsmString = "teq${p} $Rn, $imm";
  dag ResultInst = (t2TEQri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2TEQanonymous_3385 {	// InstAlias Requires t2InstAlias
  string AsmString = "teq${p} $Rn, $shift";
  dag ResultInst = (t2TEQrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2TEQri {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2OneRegCmpImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, 1, 1, 1, 1, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  string AsmString = "teq${p}.w	$Rn, $imm";
  list<dag> Pattern = [(anonymous_3218 GPRnopc:$Rn, t2_so_imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTi;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2TEQrr {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoRegCmp Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "teq${p}.w	$Rn, $Rm";
  list<dag> Pattern = [(anonymous_3218 GPRnopc:$Rn, rGPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTr;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2TEQrs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2OneRegCmpShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, 1, 1, 1, 1, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p);
  string AsmString = "teq${p}.w	$Rn, $ShiftedRm";
  list<dag> Pattern = [(anonymous_3218 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTsi;
  list<SchedReadWrite> SchedRW = [WriteCMPsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2TSTanonymous_3384 {	// InstAlias Requires t2InstAlias
  string AsmString = "tst${p} $Rn, $imm";
  dag ResultInst = (t2TSTri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2TSTanonymous_3385 {	// InstAlias Requires t2InstAlias
  string AsmString = "tst${p} $Rn, $shift";
  dag ResultInst = (t2TSTrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p);
  int EmitPriority = 0;
  list<Predicate> Predicates = [IsThumb2];
  bit UseInstAsmMatchConverter = 1;
  string AsmVariantName = "";
  string NAME = ?;
}
def t2TSTri {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2OneRegCmpImm Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, imm{11}, 0, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, imm{10}, imm{9}, imm{8}, 1, 1, 1, 1, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p);
  string AsmString = "tst${p}.w	$Rn, $imm";
  list<dag> Pattern = [(anonymous_3217 GPRnopc:$Rn, t2_so_imm:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTi;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> imm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2TSTrr {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoRegCmp Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "tst${p}.w	$Rn, $Rm";
  list<dag> Pattern = [(anonymous_3217 GPRnopc:$Rn, rGPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTr;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2TSTrs {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2OneRegCmpShiftedReg Sched
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, ?, ShiftedRm{11}, ShiftedRm{10}, ShiftedRm{9}, 1, 1, 1, 1, ShiftedRm{8}, ShiftedRm{7}, ShiftedRm{6}, ShiftedRm{5}, ShiftedRm{3}, ShiftedRm{2}, ShiftedRm{1}, ShiftedRm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p);
  string AsmString = "tst${p}.w	$Rn, $ShiftedRm";
  list<dag> Pattern = [(anonymous_3217 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTsi;
  list<SchedReadWrite> SchedRW = [WriteCMPsi];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<12> ShiftedRm = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2TT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TT Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins GPRnopc:$Rn, pred:$p);
  string AsmString = "tt${p}	$Rt, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, Has8MSecExt];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2TTA {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TT Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins GPRnopc:$Rn, pred:$p);
  string AsmString = "tta${p}	$Rt, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, Has8MSecExt];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2TTAT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TT Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 1, 1, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins GPRnopc:$Rn, pred:$p);
  string AsmString = "ttat${p}	$Rt, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, Has8MSecExt];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2TTT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TT Requires
  field bits<32> Inst = { 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rt{3}, Rt{2}, Rt{1}, Rt{0}, 0, 1, 0, 0, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt);
  dag InOperandList = (ins GPRnopc:$Rn, pred:$p);
  string AsmString = "ttt${p}	$Rt, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, Has8MSecExt];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rt = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UADD16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uadd16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UADD8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uadd8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UASX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uasx rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UBFX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2BitFI T2TwoRegBitFI
  field bits<32> Inst = { 1, 1, 1, 1, 0, ?, 1, 1, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, lsb{4}, lsb{3}, lsb{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, lsb{1}, lsb{0}, ?, msb{4}, msb{3}, msb{2}, msb{1}, msb{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb, pred:$p);
  string AsmString = "ubfx${p}	$Rd, $Rn, $lsb, $msb";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAsi;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<5> msb = { ?, ?, ?, ?, ? };
  bits<5> lsb = { ?, ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UDF {	// Instruction InstTemplate Encoding InstARM Thumb2XI T2XI
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, imm16{15}, imm16{14}, imm16{13}, imm16{12}, 1, 0, 1, 0, imm16{11}, imm16{10}, imm16{9}, imm16{8}, imm16{7}, imm16{6}, imm16{5}, imm16{4}, imm16{3}, imm16{2}, imm16{1}, imm16{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_65535:$imm16);
  string AsmString = "udf.w	$imm16";
  list<dag> Pattern = [(int_arm_undefined imm0_65535:$imm16)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<16> imm16 = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2UDIV {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, 1, 1, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "udiv${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDivideInThumb, IsThumb, HasV8MBaseline];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iDIV;
  list<SchedReadWrite> SchedRW = [WriteDIV];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UHADD16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uhadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uhadd16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UHADD8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uhadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uhadd8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UHASX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uhasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uhasx rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UHSAX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uhsax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uhsax rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UHSUB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uhsub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uhsub16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UHSUB8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uhsub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uhsub8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UMAAL {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I RegConstraint Sched T2MlaLong Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, 0, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "umaal${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UMLAL {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I RegConstraint Sched T2MlaLong
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi, pred:$p);
  string AsmString = "umlal${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMAC64;
  list<SchedReadWrite> SchedRW = [WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC];
  string Constraints = "$RLo = $RdLo, $RHi = $RdHi";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UMULL {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Sched T2MulLong
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, RdLo{3}, RdLo{2}, RdLo{1}, RdLo{0}, RdHi{3}, RdHi{2}, RdHi{1}, RdHi{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$RdLo, rGPR:$RdHi);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "umull${p}	$RdLo, $RdHi, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$RdLo, rGPR:$RdHi, (umullohi rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL64;
  list<SchedReadWrite> SchedRW = [WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> RdLo = { ?, ?, ?, ? };
  bits<4> RdHi = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UQADD16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uqadd16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uqadd16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UQADD8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uqadd8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uqadd8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UQASX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uqasx${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uqasx rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UQSAX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uqsax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uqsax rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UQSUB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uqsub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uqsub16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UQSUB8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "uqsub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_uqsub8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2USAD8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg T2ThreeReg_mac Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "usad8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_usad8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2USADA8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2FourReg T2FourReg_mac Requires
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra, pred:$p);
  string AsmString = "usada8${p}	$Rd, $Rn, $Rm, $Ra";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Ra = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2USAT {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2SatI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, sh{5}, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, sh{4}, sh{3}, sh{2}, Rd{3}, Rd{2}, Rd{1}, Rd{0}, sh{1}, sh{0}, 0, sat_imm{4}, sat_imm{3}, sat_imm{2}, sat_imm{1}, sat_imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh, pred:$p);
  string AsmString = "usat${p}	$Rd, $sat_imm, $Rn$sh";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<5> sat_imm = { ?, ?, ?, ?, ? };
  bits<6> sh = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def t2USAT16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2SatI Requires
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 0, 0, 0, 0, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 0, 0, 0, sat_imm{3}, sat_imm{2}, sat_imm{1}, sat_imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins imm0_15:$sat_imm, rGPR:$Rn, pred:$p);
  string AsmString = "usat16${p}	$Rd, $sat_imm, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<5> sat_imm = { ?, ?, ?, ?, ? };
  bits<6> sh = { 1, 0, 0, 0, 0, 0 };
  string NAME = ?;
}
def t2USAX {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "usax${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_usax rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2USUB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "usub16${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_usub16 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2USUB8 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I Requires T2I_pam T2I_pam_intrinsics
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 0, 1, 0, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, pred:$p);
  string AsmString = "usub8${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set rGPR:$Rd, (int_arm_usub8 rGPR:$Rn, rGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, HasDSP];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def t2UXTAB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2I_exta_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtab${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAsr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2UXTAB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2I_exta_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtab16${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAsr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2UXTAH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2ThreeReg Requires Sched T2I_exta_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, Rn{3}, Rn{2}, Rn{1}, Rn{0}, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtah${p}	$Rd, $Rn, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTAsr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2UXTB {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoReg T2I_ext_rrot_base Requires Sched T2I_ext_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtb${p}.w	$Rd, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2UXTB16 {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoReg T2I_ext_rrot_base Requires Sched T2I_ext_rrot_xtb16
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxtb16${p}	$Rd, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [HasDSP, IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2UXTH {	// Instruction InstTemplate Encoding InstARM Thumb2I T2I T2TwoReg T2I_ext_rrot_base Requires Sched T2I_ext_rrot
  field bits<32> Inst = { 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, Rd{3}, Rd{2}, Rd{1}, Rd{0}, 1, ?, rot{1}, rot{0}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rd);
  dag InOperandList = (ins rGPR:$Rm, rot_imm:$rot, pred:$p);
  string AsmString = "uxth${p}.w	$Rd, $Rm$rot";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2];
  int Size = 4;
  string DecoderNamespace = "Thumb2";
  int CodeSize = 0;
  int AddedComplexity = 16;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iEXTr;
  list<SchedReadWrite> SchedRW = [WriteALU, ReadALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  bits<2> rot = { ?, ? };
  string NAME = ?;
}
def t2_shift_imm {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2ShifterImmOperand";
  ValueType Type = i32;
  string PrintMethod = "printShiftImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ShifterImmAsmOperand;
  string NAME = ?;
}
def t2_so_imm {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2SOImm";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getT2SOImmOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t2_so_imm_asmoperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
    return ARM_AM::getT2SOImmVal(Imm) != -1;
  }];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def t2_so_imm_asmoperand {	// AsmOperandClass
  string Name = "T2SOImm";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = "addImmOperands";
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t2_so_imm_neg {	// DAGOperand Operand SDPatternOperator PatFrag ImmLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t2_so_imm_neg_asmoperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 imm);
  code PredicateCode = [{}];
  code ImmediateCode = [{
  return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
}];
  SDNodeXForm OperandTransform = t2_so_imm_neg_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  bit FastIselShouldIgnore = 0;
  bit IsAPInt = 0;
  bit IsAPFloat = 0;
  string NAME = ?;
}
def t2_so_imm_neg_XFORM {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def t2_so_imm_neg_asmoperand {	// AsmOperandClass
  string Name = "T2SOImmNeg";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t2_so_imm_not {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t2_so_imm_not_asmoperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
  return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = t2_so_imm_not_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def t2_so_imm_notSext {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t2_so_imm_not_asmoperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
    APInt apIntN = N->getAPIntValue();
    if (!apIntN.isIntN(16)) return false;
    unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
    return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
  }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = t2_so_imm_notSext16_XFORM;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def t2_so_imm_notSext16_XFORM {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  APInt apIntN = N->getAPIntValue();
  unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
  return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def t2_so_imm_not_XFORM {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
                                   MVT::i32);
}];
  string NAME = ?;
}
def t2_so_imm_not_asmoperand {	// AsmOperandClass
  string Name = "T2SOImmNot";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t2_so_reg {	// DAGOperand Operand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeSORegImmOperand";
  ValueType Type = i32;
  string PrintMethod = "printT2SOOperand";
  string EncoderMethod = "getT2SORegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops rGPR, i32imm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ShiftedImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectShiftImmShifterOperand";
  list<SDNode> RootNodes = [shl, srl, sra, rotr];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t2addrmode_imm0_1020s4 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeImm0_1020s4Operand";
  string EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectT2AddrModeExclusive";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t2addrmode_imm12 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm12";
  ValueType Type = i32;
  string PrintMethod = "printAddrModeImm12Operand<false>";
  string EncoderMethod = "getAddrModeImm12OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t2addrmode_imm12_asmoperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectT2AddrModeImm12";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t2addrmode_imm12_asmoperand {	// AsmOperandClass
  string Name = "MemUImm12Offset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t2addrmode_imm8 {	// DAGOperand Operand MemOperand ComplexPattern T2AddrMode_Imm8
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm8";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeImm8Operand<false>";
  string EncoderMethod = "getT2AddrModeImm8OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm8OffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectT2AddrModeImm8";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t2addrmode_imm8_pre {	// DAGOperand Operand MemOperand ComplexPattern T2AddrMode_Imm8
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm8";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeImm8Operand<true>";
  string EncoderMethod = "getT2AddrModeImm8OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm8OffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectT2AddrModeImm8";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t2addrmode_imm8s4 {	// DAGOperand Operand MemOperand T2AddrMode_Imm8s4
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm8s4";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeImm8s4Operand<false>";
  string EncoderMethod = "getT2AddrModeImm8s4OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm8s4OffsetAsmOperand;
  string NAME = ?;
}
def t2addrmode_imm8s4_pre {	// DAGOperand Operand MemOperand T2AddrMode_Imm8s4
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm8s4";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeImm8s4Operand<true>";
  string EncoderMethod = "getT2AddrModeImm8s4OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemImm8s4OffsetAsmOperand;
  string NAME = ?;
}
def t2addrmode_negimm8 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm8";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeImm8Operand<false>";
  string EncoderMethod = "getT2AddrModeImm8OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemNegImm8OffsetAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectT2AddrModeImm8";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t2addrmode_posimm8 {	// DAGOperand Operand MemOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeImm8";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeImm8Operand<false>";
  string EncoderMethod = "getT2AddrModeImm8OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = MemPosImm8OffsetAsmOperand;
  string NAME = ?;
}
def t2addrmode_so_reg {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2AddrModeSOReg";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeSoRegOperand";
  string EncoderMethod = "getT2AddrModeSORegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t2addrmode_so_reg_asmoperand;
  ValueType Ty = i32;
  int NumOperands = 3;
  string SelectFunc = "SelectT2AddrModeSoReg";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t2addrmode_so_reg_asmoperand {	// AsmOperandClass
  string Name = "T2MemRegOffset";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t2adrlabel {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAdrLabelOperand<0>";
  string EncoderMethod = "getT2AdrLabelOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def t2am_imm8_offset {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2Imm8";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeImm8OffsetOperand";
  string EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  ValueType Ty = i32;
  int NumOperands = 1;
  string SelectFunc = "SelectT2AddrModeImm8Offset";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [SDNPWantRoot];
  int Complexity = -1;
  string NAME = ?;
}
def t2am_imm8s4_offset {	// DAGOperand Operand MemOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeT2Imm8S4";
  ValueType Type = i32;
  string PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
  string EncoderMethod = "getT2Imm8s4OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def t2am_imm8s4_offset_asmoperand {	// AsmOperandClass
  string Name = "Imm8s4";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t2ldr_pcrel_imm12 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
  string NAME = ?;
}
def t2ldr_pcrel_imm12_asmoperand {	// AsmOperandClass
  string Name = "MemPCRelImm12";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t2ldrlabel {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printThumbLdrLabelOperand";
  string EncoderMethod = "getAddrModeImm12OpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def tADC {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "adc${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tADCS {	// Instruction InstTemplate PseudoInst tPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tADDSi3 {	// Instruction InstTemplate PseudoInst tPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm, imm0_7:$imm3);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm, imm0_7:$imm3))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tADDSi8 {	// Instruction InstTemplate PseudoInst tPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn);
  dag InOperandList = (ins tGPR:$Rn, imm0_255:$imm8);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$Rdn, CPSR, (ARMaddc tGPR:$Rn, imm8_255:$imm8))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tADDSrr {	// Instruction InstTemplate PseudoInst tPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tADDframe {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$dst);
  dag InOperandList = (ins i32imm:$base, i32imm:$offset);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tADDhirr {	// Instruction InstTemplate InstThumb Thumb1pI T1pIt Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, Rdn{3}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rdn);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "add${p}	$Rdn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rdn = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def tADDi3 {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General T1sIGenEncodeImm Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, imm3{2}, imm3{1}, imm3{0}, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rm, imm0_7:$imm3, pred:$p);
  string AsmString = "add${s}${p}	$Rd, $Rm, $imm3";
  list<dag> Pattern = [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  bits<3> imm3 = { ?, ?, ? };
  string NAME = ?;
}
def tADDi8 {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1General T1sItGenEncodeImm Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, Rdn{2}, Rdn{1}, Rdn{0}, imm8{7}, imm8{6}, imm8{5}, imm8{4}, imm8{3}, imm8{2}, imm8{1}, imm8{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, imm0_255:$imm8, pred:$p);
  string AsmString = "add${s}${p}	$Rdn, $imm8";
  list<dag> Pattern = [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<8> imm8 = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tADDrSP {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, Rdn{3}, 1, 1, 0, 1, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rdn);
  dag InOperandList = (ins GPRsp:$sp, GPR:$Rn, pred:$p);
  string AsmString = "add${p}	$Rdn, $sp, $Rn";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumbAddSPReg";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rdn = { ?, ?, ?, ? };
  string NAME = ?;
}
def tADDrSPi {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Encoding Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, dst{2}, dst{1}, dst{0}, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$dst);
  dag InOperandList = (ins GPRsp:$sp, t_imm0_1020s4:$imm, pred:$p);
  string AsmString = "add${p}	$dst, $sp, $imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumbAddSpecialReg";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> dst = { ?, ?, ? };
  bits<8> imm = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tADDrr {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General T1sIGenEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, Rm{2}, Rm{1}, Rm{0}, Rn{2}, Rn{1}, Rn{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "add${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 1;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
def tADDspi {	// Instruction InstTemplate InstThumb Thumb1pI T1pIt Encoding Encoding16 T1Misc Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRsp:$Rdn);
  dag InOperandList = (ins GPRsp:$Rn, t_imm0_508s4:$imm, pred:$p);
  string AsmString = "add${p}	$Rdn, $imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumbAddSPImm";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<7> imm = { ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tADDspr {	// Instruction InstTemplate InstThumb Thumb1pI T1pIt Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRsp:$Rdn);
  dag InOperandList = (ins GPRsp:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "add${p}	$Rdn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumbAddSPReg";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def tADJCALLSTACKDOWN {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$amt, i32imm:$amt2);
  string AsmString = "";
  list<dag> Pattern = [(ARMcallseq_start imm:$amt, imm:$amt2)];
  list<Register> Uses = [SP];
  list<Register> Defs = [SP];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tADJCALLSTACKUP {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins i32imm:$amt1, i32imm:$amt2);
  string AsmString = "";
  list<dag> Pattern = [(ARMcallseq_end imm:$amt1, imm:$amt2)];
  list<Register> Uses = [SP];
  list<Register> Defs = [SP];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tADR {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Encoding Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, Rd{2}, Rd{1}, Rd{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins t_adrlabel:$addr, pred:$p);
  string AsmString = "adr{$p}	$Rd, $addr";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumbAddSpecialReg";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rd = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tAND {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "and${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tASRri {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General T1sIGenEncodeImm Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, imm5{4}, imm5{3}, imm5{2}, imm5{1}, imm5{0}, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rm, imm_sr:$imm5, pred:$p);
  string AsmString = "asr${s}${p}	$Rd, $Rm, $imm5";
  list<dag> Pattern = [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  bits<5> imm5 = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tASRrr {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "asr${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tB {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Encoding Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, target{10}, target{9}, target{8}, target{7}, target{6}, target{5}, target{4}, target{3}, target{2}, target{1}, target{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t_brtarget:$target, pred:$p);
  string AsmString = "b${p}	$target";
  list<dag> Pattern = [(br bb:$target)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 1;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "cvtThumbBranches";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<11> target = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tBIC {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "bic${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tBKPT {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Encoding
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, val{7}, val{6}, val{5}, val{4}, val{3}, val{2}, val{1}, val{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_255:$val);
  string AsmString = "bkpt	$val";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> val = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tBL {	// Instruction InstTemplate InstThumb ThumbI Encoding TIx2 Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, func{23}, func{20}, func{19}, func{18}, func{17}, func{16}, func{15}, func{14}, func{13}, func{12}, func{11}, 1, 1, func{22}, 1, func{21}, func{10}, func{9}, func{8}, func{7}, func{6}, func{5}, func{4}, func{3}, func{2}, func{1}, func{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p, thumb_bl_target:$func);
  string AsmString = "bl${p}	$func";
  list<dag> Pattern = [(ARMcall tglobaladdr:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsThumb];
  int Size = 4;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<24> func = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tBLXNSr {	// Instruction InstTemplate InstThumb ThumbI TI Requires Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, func{3}, func{2}, func{1}, func{0}, 1, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p, GPRnopc:$func);
  string AsmString = "blxns${p}	$func";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsThumb, Has8MSecExt];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> func = { ?, ?, ?, ? };
  string NAME = ?;
}
def tBLXi {	// Instruction InstTemplate InstThumb ThumbI Encoding TIx2 Requires Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, func{23}, func{20}, func{19}, func{18}, func{17}, func{16}, func{15}, func{14}, func{13}, func{12}, func{11}, 1, 1, func{22}, 0, func{21}, func{10}, func{9}, func{8}, func{7}, func{6}, func{5}, func{4}, func{3}, func{2}, func{1}, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p, thumb_blx_target:$func);
  string AsmString = "blx${p}	$func";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsThumb, HasV5T, IsNotMClass];
  int Size = 4;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<24> func = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tBLXr {	// Instruction InstTemplate InstThumb ThumbI TI Requires Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, func{3}, func{2}, func{1}, func{0}, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p, GPR:$func);
  string AsmString = "blx${p}	$func";
  list<dag> Pattern = [(ARMcall GPR:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsThumb, HasV5T];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> func = { ?, ?, ?, ? };
  string NAME = ?;
}
def tBRIND {	// Instruction InstTemplate PseudoInst tPseudoInst PseudoInstExpansion tPseudoExpand Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(brind GPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (tMOVr PC, GPR:$Rm, pred:$p);
  string NAME = ?;
}
def tBR_JTr {	// Instruction InstTemplate PseudoInst tPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$target, i32imm:$jt);
  string AsmString = "";
  list<dag> Pattern = [(ARMbrjt tGPR:$target, tjumptable:$jt)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrTbl];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tBX {	// Instruction InstTemplate InstThumb ThumbI TI Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rm, pred:$p);
  string AsmString = "bx${p}	$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def tBXNS {	// Instruction InstTemplate InstThumb ThumbI TI Requires Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 1, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rm, pred:$p);
  string AsmString = "bxns${p}	$Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, Has8MSecExt];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def tBX_CALL {	// Instruction InstTemplate PseudoInst tPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$func);
  string AsmString = "";
  list<dag> Pattern = [(ARMcall_nolink tGPR:$func)];
  list<Register> Uses = [SP];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tBX_RET {	// Instruction InstTemplate PseudoInst tPseudoInst PseudoInstExpansion tPseudoExpand Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p);
  string AsmString = "";
  list<dag> Pattern = [(ARMretflag)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (tBX LR, pred:$p);
  string NAME = ?;
}
def tBX_RET_vararg {	// Instruction InstTemplate PseudoInst tPseudoInst PseudoInstExpansion tPseudoExpand Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rm, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (tBX GPR:$Rm, pred:$p);
  string NAME = ?;
}
def tBcc {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1BranchCond Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, p{3}, p{2}, p{1}, p{0}, target{7}, target{6}, target{5}, target{4}, target{3}, target{2}, target{1}, target{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins thumb_bcc_target:$target, pred:$p);
  string AsmString = "b${p}	$target";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "cvtThumbBranches";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> p = { ?, ?, ?, ? };
  bits<8> target = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tBfar {	// Instruction InstTemplate PseudoInst tPseudoInst PseudoInstExpansion tPseudoExpand Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins thumb_bl_target:$target, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [LR];
  list<Predicate> Predicates = [IsThumb];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBrTbl];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (tBL pred:$p, thumb_bl_target:$target);
  string NAME = ?;
}
def tCBNZ {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Misc Requires Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, target{5}, 1, target{4}, target{3}, target{2}, target{1}, target{0}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rn, thumb_cb_target:$target);
  string AsmString = "cbnz	$Rn, $target";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<6> target = { ?, ?, ?, ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
def tCBZ {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Misc Requires Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, target{5}, 1, target{4}, target{3}, target{2}, target{1}, target{0}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rn, thumb_cb_target:$target);
  string AsmString = "cbz	$Rn, $target";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8MBaseline];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<6> target = { ?, ?, ?, ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
def tCMNz {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1DataProcessing T1pIDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1, Rm{2}, Rm{1}, Rm{0}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "cmn${p}	$Rn, $Rm";
  list<dag> Pattern = [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPr;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
def tCMPhir {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, Rn{3}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$Rn, GPR:$Rm, pred:$p);
  string AsmString = "cmp${p}	$Rn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPr;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rm = { ?, ?, ?, ? };
  bits<4> Rn = { ?, ?, ?, ? };
  string NAME = ?;
}
def tCMPi8 {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1General Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, Rn{2}, Rn{1}, Rn{0}, imm8{7}, imm8{6}, imm8{5}, imm8{4}, imm8{3}, imm8{2}, imm8{1}, imm8{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rn, imm0_255:$imm8, pred:$p);
  string AsmString = "cmp${p}	$Rn, $imm8";
  list<dag> Pattern = [(ARMcmp tGPR:$Rn, imm0_255:$imm8)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPi;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rn = { ?, ?, ? };
  bits<8> imm8 = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tCMPr {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1DataProcessing T1pIDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, Rm{2}, Rm{1}, Rm{0}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "cmp${p}	$Rn, $Rm";
  list<dag> Pattern = [(ARMcmp tGPR:$Rn, tGPR:$Rm)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iCMPr;
  list<SchedReadWrite> SchedRW = [WriteCMP];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
def tCPS {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Misc
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 1, imod, 0, iflags{2}, iflags{1}, iflags{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imod_op:$imod, iflags_op:$iflags);
  string AsmString = "cps$imod $iflags";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumbCPS";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bit imod = ?;
  bits<3> iflags = { ?, ?, ? };
  string NAME = ?;
}
def tEOR {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "eor${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tGPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (trunc GPR, 8);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "operand must be a register in range [r0, r7]";
  string NAME = ?;
}
def tGPRwithpc {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (add tGPR, PC);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [];
  code AltOrderSelect = [{}];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def tHINT {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Encoding T1SystemEncoding Requires
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, imm{3}, imm{2}, imm{1}, imm{0}, 0, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_15:$imm, pred:$p);
  string AsmString = "hint${p}	$imm";
  list<dag> Pattern = [(int_arm_hint imm0_15:$imm)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV6M];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> imm = { ?, ?, ?, ? };
  string NAME = ?;
}
def tHLT {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Encoding Requires
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 1, 0, val{5}, val{4}, val{3}, val{2}, val{1}, val{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_63:$val);
  string AsmString = "hlt	$val";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, HasV8];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<6> val = { ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tInt_WIN_eh_sjlj_longjmp {	// Instruction InstTemplate Encoding InstARM XI Requires
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$src, GPR:$scratch);
  string AsmString = "";
  list<dag> Pattern = [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)];
  list<Register> Uses = [];
  list<Register> Defs = [R11, LR, SP];
  list<Predicate> Predicates = [IsThumb, IsWindows];
  int Size = 0;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tInt_eh_sjlj_longjmp {	// Instruction InstTemplate Encoding InstARM XI Requires
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins GPR:$src, GPR:$scratch);
  string AsmString = "";
  list<dag> Pattern = [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)];
  list<Register> Uses = [];
  list<Register> Defs = [R7, LR, SP];
  list<Predicate> Predicates = [IsThumb, IsNotWindows];
  int Size = 0;
  string DecoderNamespace = "ARM";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tInt_eh_sjlj_setjmp {	// Instruction InstTemplate Encoding InstARM ThumbXI
  field bits<32> Inst = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$src, tGPR:$val);
  string AsmString = "";
  list<dag> Pattern = [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))];
  list<Register> Uses = [];
  list<Register> Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 0;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tLDMIA {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Encoding
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, Rn{2}, Rn{1}, Rn{0}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "ldm${p}	$Rn, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rn = { ?, ?, ? };
  bits<8> regs = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDMIA_UPD {	// Instruction InstTemplate PseudoInstExpansion
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs);
  string NAME = ?;
}
def tLDRBi {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncodeImm
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_is1:$addr, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (zextloadi8 t_addrmode_is1:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDRBr {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncode
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_rr:$addr, pred:$p);
  string AsmString = "ldrb${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (zextloadi8 t_addrmode_rr:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDRConstPool {	// Instruction InstTemplate AsmPseudoInst Requires tAsmPseudo
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rt, const_pool_asm_imm:$immediate, pred:$p);
  string AsmString = "ldr${p} $Rt, $immediate";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tLDRHi {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncodeImm
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_is2:$addr, pred:$p);
  string AsmString = "ldrh${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (zextloadi16 t_addrmode_is2:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_2;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDRHr {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncode
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_rr:$addr, pred:$p);
  string AsmString = "ldrh${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (zextloadi16 t_addrmode_rr:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_2;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDRLIT_ga_abs {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$dst);
  dag InOperandList = (ins i32imm:$src);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$dst, (ARMWrapper tglobaladdr:$src))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, DontUseMovt];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tLDRLIT_ga_pcrel {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$dst);
  dag InOperandList = (ins i32imm:$addr);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, DontUseMovtInPic];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoadiALU;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tLDRSB {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncode
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_rr:$addr, pred:$p);
  string AsmString = "ldrsb${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDRSH {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncode
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_rr:$addr, pred:$p);
  string AsmString = "ldrsh${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_2;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDR_postidx {	// Instruction InstTemplate PseudoInst tPseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs rGPR:$Rt, rGPR:$Rn_wb);
  dag InOperandList = (ins rGPR:$Rn, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_ru;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tLDRi {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncodeImm
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_is4:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (load t_addrmode_is4:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDRpci {	// Instruction InstTemplate InstThumb Thumb1pI T1pIs Encoding Encoding16 T1Encoding
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_pc:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 10;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_s;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDRpci_pic {	// Instruction InstTemplate PseudoInst Requires
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins i32imm:$addr, pclabel:$cp);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), imm:$cp))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tLDRr {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncode
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_rr:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (load t_addrmode_rr:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLDRspi {	// Instruction InstTemplate InstThumb Thumb1pI T1pIs Encoding Encoding16 T1LoadStore T1LdStSP
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rt);
  dag InOperandList = (ins t_addrmode_sp:$addr, pred:$p);
  string AsmString = "ldr${p}	$Rt, $addr";
  list<dag> Pattern = [(set tGPR:$Rt, (load t_addrmode_sp:$addr))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 1;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iLoad_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_s;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLEApcrel {	// Instruction InstTemplate PseudoInst tPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins i32imm:$label, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 1;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tLEApcrelJT {	// Instruction InstTemplate PseudoInst tPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins i32imm:$label, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 1;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tLSLri {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General T1sIGenEncodeImm Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, imm5{4}, imm5{3}, imm5{2}, imm5{1}, imm5{0}, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rm, imm0_31:$imm5, pred:$p);
  string AsmString = "lsl${s}${p}	$Rd, $Rm, $imm5";
  list<dag> Pattern = [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  bits<5> imm5 = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLSLrr {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "lsl${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tLSRri {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General T1sIGenEncodeImm Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, imm5{4}, imm5{3}, imm5{2}, imm5{1}, imm5{0}, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rm, imm_sr:$imm5, pred:$p);
  string AsmString = "lsr${s}${p}	$Rd, $Rm, $imm5";
  list<dag> Pattern = [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  bits<5> imm5 = { ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tLSRrr {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "lsr${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tMOVCCr_pseudo {	// Instruction InstTemplate PseudoInst
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$dst);
  dag InOperandList = (ins tGPR:$false, tGPR:$true, cmovpred:$p);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [];
  int Size = 0;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 1;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tMOVSr {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm);
  string AsmString = "movs	$Rd, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tMOVi8 {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, Rd{2}, Rd{1}, Rd{0}, imm8{7}, imm8{6}, imm8{5}, imm8{4}, imm8{3}, imm8{2}, imm8{1}, imm8{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins imm0_255:$imm8, pred:$p);
  string AsmString = "mov${s}${p}	$Rd, $imm8";
  list<dag> Pattern = [(set tGPR:$Rd, imm0_255:$imm8)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 1;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<8> imm8 = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tMOVr {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, Rd{3}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$Rd);
  dag InOperandList = (ins GPR:$Rm, pred:$p);
  string AsmString = "mov${p}	$Rd, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<4> Rd = { ?, ?, ?, ? };
  bits<4> Rm = { ?, ?, ?, ? };
  string NAME = ?;
}
def tMUL {	// Instruction InstTemplate InstThumb Thumb1sI Encoding Encoding16 T1DataProcessing
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, Rn{2}, Rn{1}, Rn{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "mul${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMUL32;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rm = $Rd";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "cvtThumbMultiply";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
def tMVN {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1DataProcessing T1sIDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, Rn{2}, Rn{1}, Rn{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, pred:$p);
  string AsmString = "mvn${s}${p}	$Rd, $Rn";
  list<dag> Pattern = [(set tGPR:$Rd, (not tGPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMVNr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
def tORR {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "orr${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iBITr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tPICADD {	// Instruction InstTemplate InstThumb ThumbI TIt Encoding Encoding16 T1Special Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, ?, 1, 1, 1, 1, dst{2}, dst{1}, dst{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$dst);
  dag InOperandList = (ins GPR:$lhs, pclabel:$cp);
  string AsmString = "";
  list<dag> Pattern = [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 1;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$lhs = $dst";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> dst = { ?, ?, ? };
  string NAME = ?;
}
def tPOP {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Misc
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, regs{15}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p, reglist:$regs, variable_ops);
  string AsmString = "pop${p}	$regs";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [SP];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iPop;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tPOP_RET {	// Instruction InstTemplate PseudoInst tPseudoInst PseudoInstExpansion tPseudoExpand Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p, reglist:$regs, variable_ops);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = 1;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 1;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iPop_Br;
  list<SchedReadWrite> SchedRW = [WriteBrL];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (tPOP pred:$p, reglist:$regs);
  string NAME = ?;
}
def tPUSH {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Misc
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, regs{14}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins pred:$p, reglist:$regs, variable_ops);
  string AsmString = "push${p}	$regs";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [SP];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_m;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<16> regs = { ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tREV {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Misc T1pIMiscEncode Requires Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm, pred:$p);
  string AsmString = "rev${p}	$Rd, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (bswap tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
def tREV16 {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Misc T1pIMiscEncode Requires Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 1, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm, pred:$p);
  string AsmString = "rev16${p}	$Rd, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
def tREVSH {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Misc T1pIMiscEncode Requires Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 1, 1, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm, pred:$p);
  string AsmString = "revsh${p}	$Rd, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
def tROR {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "ror${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iMOVsr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tRSB {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1DataProcessing T1sIDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, Rn{2}, Rn{1}, Rn{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, pred:$p);
  string AsmString = "rsb${s}${p}	$Rd, $Rn, #0";
  list<dag> Pattern = [(set tGPR:$Rd, (ineg tGPR:$Rn))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
def tSBC {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1DataProcessing T1sItDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, Rm{2}, Rm{1}, Rm{0}, Rdn{2}, Rdn{1}, Rdn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "sbc${s}${p}	$Rdn, $Rm";
  list<dag> Pattern = [];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  string NAME = ?;
}
def tSBCS {	// Instruction InstTemplate PseudoInst tPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$Rdn, CPSR, (ARMsube tGPR:$Rn, tGPR:$Rm, CPSR))];
  list<Register> Uses = [CPSR];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tSETEND {	// Instruction InstTemplate InstThumb Thumb1I T1I Encoding Encoding16 T1Encoding Requires Deprecated
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 0, 1, end{0}, 0, 0, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins setend_op:$end);
  string AsmString = "setend	$end";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsNotMClass];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = NoItinerary;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  SubtargetFeature DeprecatedFeatureMask = HasV8Ops;
  bits<1> end = { ? };
  string NAME = ?;
}
def tSTMIA_UPD {	// Instruction InstTemplate InstThumb Thumb1I Encoding Encoding16 T1Encoding
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, Rn{2}, Rn{1}, Rn{0}, regs{7}, regs{6}, regs{5}, regs{4}, regs{3}, regs{2}, regs{1}, regs{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPR:$wb);
  dag InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops);
  string AsmString = "stm${p}	$Rn!, $regs";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = 1;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 1;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = 0;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_mu;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "$Rn = $wb";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rn = { ?, ?, ? };
  bits<8> regs = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSTRBi {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncodeImm
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rt, t_addrmode_is1:$addr, pred:$p);
  string AsmString = "strb${p}	$Rt, $addr";
  list<dag> Pattern = [(truncstorei8 tGPR:$Rt, t_addrmode_is1:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSTRBr {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncode
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rt, t_addrmode_rr:$addr, pred:$p);
  string AsmString = "strb${p}	$Rt, $addr";
  list<dag> Pattern = [(truncstorei8 tGPR:$Rt, t_addrmode_rr:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_1;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSTRHi {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncodeImm
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rt, t_addrmode_is2:$addr, pred:$p);
  string AsmString = "strh${p}	$Rt, $addr";
  list<dag> Pattern = [(truncstorei16 tGPR:$Rt, t_addrmode_is2:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_2;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSTRHr {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncode
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rt, t_addrmode_rr:$addr, pred:$p);
  string AsmString = "strh${p}	$Rt, $addr";
  list<dag> Pattern = [(truncstorei16 tGPR:$Rt, t_addrmode_rr:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_bh_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_2;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSTRi {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncodeImm
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rt, t_addrmode_is4:$addr, pred:$p);
  string AsmString = "str${p}	$Rt, $addr";
  list<dag> Pattern = [(store tGPR:$Rt, t_addrmode_is4:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSTRr {	// Instruction InstTemplate InstThumb Thumb1pI Encoding Encoding16 T1LoadStore T1pILdStEncode
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0}, Rt{2}, Rt{1}, Rt{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rt, t_addrmode_rr:$addr, pred:$p);
  string AsmString = "str${p}	$Rt, $addr";
  list<dag> Pattern = [(store tGPR:$Rt, t_addrmode_rr:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_r;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_4;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSTRspi {	// Instruction InstTemplate InstThumb Thumb1pI T1pIs Encoding Encoding16 T1LoadStore T1LdStSP
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, Rt{2}, Rt{1}, Rt{0}, addr{7}, addr{6}, addr{5}, addr{4}, addr{3}, addr{2}, addr{1}, addr{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rt, t_addrmode_sp:$addr, pred:$p);
  string AsmString = "str${p}	$Rt, $addr";
  list<dag> Pattern = [(store tGPR:$Rt, t_addrmode_sp:$addr)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iStore_i;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeT1_s;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rt = { ?, ?, ? };
  bits<8> addr = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSUBSi3 {	// Instruction InstTemplate PseudoInst tPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm, imm0_7:$imm3);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rm, imm0_7:$imm3))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tSUBSi8 {	// Instruction InstTemplate PseudoInst tPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn);
  dag InOperandList = (ins tGPR:$Rn, imm0_255:$imm8);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$Rdn, CPSR, (ARMsubc tGPR:$Rn, imm8_255:$imm8))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tSUBSrr {	// Instruction InstTemplate PseudoInst tPseudoInst Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm);
  string AsmString = "";
  list<dag> Pattern = [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 1;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tSUBi3 {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General T1sIGenEncodeImm Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, imm3{2}, imm3{1}, imm3{0}, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rm, imm0_7:$imm3, pred:$p);
  string AsmString = "sub${s}${p}	$Rd, $Rm, $imm3";
  list<dag> Pattern = [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rd = { ?, ?, ? };
  bits<3> Rm = { ?, ?, ? };
  bits<3> imm3 = { ?, ?, ? };
  string NAME = ?;
}
def tSUBi8 {	// Instruction InstTemplate InstThumb Thumb1sI T1sIt Encoding Encoding16 T1General T1sItGenEncodeImm Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, Rdn{2}, Rdn{1}, Rdn{0}, imm8{7}, imm8{6}, imm8{5}, imm8{4}, imm8{3}, imm8{2}, imm8{1}, imm8{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rdn, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, imm0_255:$imm8, pred:$p);
  string AsmString = "sub${s}${p}	$Rdn, $imm8";
  list<dag> Pattern = [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rdn = { ?, ?, ? };
  bits<8> imm8 = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSUBrr {	// Instruction InstTemplate InstThumb Thumb1sI T1sI Encoding Encoding16 T1General T1sIGenEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, Rm{2}, Rm{1}, Rm{0}, Rn{2}, Rn{1}, Rn{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd, s_cc_out:$s);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "sub${s}${p}	$Rd, $Rn, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "ThumbSBit";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 1;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
def tSUBspi {	// Instruction InstTemplate InstThumb Thumb1pI T1pIt Encoding Encoding16 T1Misc Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 1, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs GPRsp:$Rdn);
  dag InOperandList = (ins GPRsp:$Rn, t_imm0_508s4:$imm, pred:$p);
  string AsmString = "sub${p}	$Rdn, $imm";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iALUi;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "$Rn = $Rdn";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "DecodeThumbAddSPImm";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<7> imm = { ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSVC {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, imm{7}, imm{6}, imm{5}, imm{4}, imm{3}, imm{2}, imm{1}, imm{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_255:$imm, pred:$p);
  string AsmString = "svc${p}	$imm";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> imm = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tSXTB {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Misc T1pIMiscEncode Requires Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 1, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm, pred:$p);
  string AsmString = "sxtb${p}	$Rd, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
def tSXTH {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Misc T1pIMiscEncode Requires Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm, pred:$p);
  string AsmString = "sxth${p}	$Rd, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
def tTAILJMPd {	// Instruction InstTemplate PseudoInst tPseudoInst PseudoInstExpansion tPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins thumb_br_target:$dst, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb2, IsMachO];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (t2B thumb_br_target:$dst, pred:$p);
  string NAME = ?;
}
def tTAILJMPdND {	// Instruction InstTemplate PseudoInst tPseudoInst PseudoInstExpansion tPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins t_brtarget:$dst, pred:$p);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsNotMachO];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (tB t_brtarget:$dst, pred:$p);
  string NAME = ?;
}
def tTAILJMPr {	// Instruction InstTemplate PseudoInst tPseudoInst PseudoInstExpansion tPseudoExpand Requires Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tcGPR:$dst);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [SP];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 1;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  dag ResultInst = (tBX GPR:$dst, (ops 14, zero_reg));
  string NAME = ?;
}
def tTBB_JT {	// Instruction InstTemplate PseudoInst tPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tTBH_JT {	// Instruction InstTemplate PseudoInst tPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl);
  string AsmString = "";
  list<dag> Pattern = [];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 1;
  bit isIndirectBranch = 1;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tTPsoft {	// Instruction InstTemplate PseudoInst tPseudoInst Sched
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "";
  list<dag> Pattern = [(set R0, ARMthread_pointer)];
  list<Register> Uses = [SP];
  list<Register> Defs = [R0, R12, LR, CPSR];
  list<Predicate> Predicates = [IsThumb];
  int Size = 4;
  string DecoderNamespace = "";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 1;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 1;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 1;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = Pseudo;
  bits<6> Form = { 0, 0, 0, 0, 0, 0 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tTRAP {	// Instruction InstTemplate InstThumb ThumbI TI Encoding Encoding16 Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "trap";
  list<dag> Pattern = [(trap)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 1;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = [WriteBr];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def tTST {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1DataProcessing T1pIDPEncode Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, Rm{2}, Rm{1}, Rm{0}, Rn{2}, Rn{1}, Rn{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins tGPR:$Rn, tGPR:$Rm, pred:$p);
  string AsmString = "tst${p}	$Rn, $Rm";
  list<dag> Pattern = [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)];
  list<Register> Uses = [];
  list<Register> Defs = [CPSR];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 1;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 1;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iTSTr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rn = { ?, ?, ? };
  string NAME = ?;
}
def tUDF {	// Instruction InstTemplate InstThumb ThumbI TI Encoding Encoding16
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 0, imm8{7}, imm8{6}, imm8{5}, imm8{4}, imm8{3}, imm8{2}, imm8{1}, imm8{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins imm0_255:$imm8);
  string AsmString = "udf	$imm8";
  list<dag> Pattern = [(int_arm_undefined imm0_255:$imm8)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<8> imm8 = { ?, ?, ?, ?, ?, ?, ?, ? };
  string NAME = ?;
}
def tUXTB {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Misc T1pIMiscEncode Requires Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm, pred:$p);
  string AsmString = "uxtb${p}	$Rd, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (and tGPR:$Rm, 255))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
def tUXTH {	// Instruction InstTemplate InstThumb Thumb1pI T1pI Encoding Encoding16 T1Misc T1pIMiscEncode Requires Sched
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 0, Rm{2}, Rm{1}, Rm{0}, Rd{2}, Rd{1}, Rd{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs tGPR:$Rd);
  dag InOperandList = (ins tGPR:$Rm, pred:$p);
  string AsmString = "uxth${p}	$Rd, $Rm";
  list<dag> Pattern = [(set tGPR:$Rd, (and tGPR:$Rm, 65535))];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV6];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 0;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_iUNAr;
  list<SchedReadWrite> SchedRW = [WriteALU];
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  bits<3> Rm = { ?, ?, ? };
  bits<3> Rd = { ?, ?, ? };
  string NAME = ?;
}
def t__brkdiv0 {	// Instruction InstTemplate InstThumb ThumbI TI Encoding Encoding16 Requires
  field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1 };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ARM";
  dag OutOperandList = (outs);
  dag InOperandList = (ins);
  string AsmString = "__brkdiv0";
  list<dag> Pattern = [(int_arm_undefined 249)];
  list<Register> Uses = [];
  list<Register> Defs = [];
  list<Predicate> Predicates = [IsThumb, IsWindows];
  int Size = 2;
  string DecoderNamespace = "Thumb";
  int CodeSize = 0;
  int AddedComplexity = 0;
  bit isReturn = 0;
  bit isBranch = 0;
  bit isIndirectBranch = 0;
  bit isCompare = 0;
  bit isMoveImm = 0;
  bit isBitcast = 0;
  bit isSelect = 0;
  bit isBarrier = 0;
  bit isCall = 0;
  bit isAdd = 0;
  bit canFoldAsLoad = 0;
  bit mayLoad = ?;
  bit mayStore = ?;
  bit isConvertibleToThreeAddress = 0;
  bit isCommutable = 0;
  bit isTerminator = 1;
  bit isReMaterializable = 0;
  bit isPredicable = 0;
  bit hasDelaySlot = 0;
  bit usesCustomInserter = 0;
  bit hasPostISelHook = 0;
  bit hasCtrlDep = 0;
  bit isNotDuplicable = 0;
  bit isConvergent = 0;
  bit isAsCheapAsAMove = 0;
  bit hasExtraSrcRegAllocReq = 0;
  bit hasExtraDefRegAllocReq = 0;
  bit isRegSequence = 0;
  bit isPseudo = 0;
  bit isExtractSubreg = 0;
  bit isInsertSubreg = 0;
  bit hasSideEffects = ?;
  bit isCodeGenOnly = 0;
  bit isAsmParserOnly = 0;
  bit hasNoSchedulingInfo = 0;
  InstrItinClass Itinerary = IIC_Br;
  list<SchedReadWrite> SchedRW = ?;
  string Constraints = "";
  string DisableEncoding = "";
  string PostEncoderMethod = "";
  string DecoderMethod = "";
  bit hasCompleteDecoder = 1;
  bits<64> TSFlags = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 };
  string AsmMatchConverter = "";
  string TwoOperandAliasConstraint = "";
  string AsmVariantName = "";
  bit UseNamedOperandTable = 0;
  AddrMode AM = AddrModeNone;
  IndexMode IM = IndexModeNone;
  bits<2> IndexModeBits = { 0, 0 };
  Format F = ThumbFrm;
  bits<6> Form = { 0, 1, 1, 0, 0, 1 };
  Domain D = GenericDomain;
  bit isUnaryDataProc = 0;
  bit canXformTo16Bit = 0;
  bit thumbArithFlagSetting = 0;
  string NAME = ?;
}
def t_addrmode_is1 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbAddrModeIS";
  ValueType Type = i32;
  string PrintMethod = "printThumbAddrModeImm5S1Operand";
  string EncoderMethod = "getAddrModeISOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_addrmode_is1_asm_operand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectThumbAddrModeImm5S1";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t_addrmode_is1_asm_operand {	// AsmOperandClass
  string Name = "MemThumbRIs1";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t_addrmode_is2 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbAddrModeIS";
  ValueType Type = i32;
  string PrintMethod = "printThumbAddrModeImm5S2Operand";
  string EncoderMethod = "getAddrModeISOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_addrmode_is2_asm_operand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectThumbAddrModeImm5S2";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t_addrmode_is2_asm_operand {	// AsmOperandClass
  string Name = "MemThumbRIs2";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t_addrmode_is4 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbAddrModeIS";
  ValueType Type = i32;
  string PrintMethod = "printThumbAddrModeImm5S4Operand";
  string EncoderMethod = "getAddrModeISOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_addrmode_is4_asm_operand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectThumbAddrModeImm5S4";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t_addrmode_is4_asm_operand {	// AsmOperandClass
  string Name = "MemThumbRIs4";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t_addrmode_pc {	// DAGOperand Operand MemOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbAddrModePC";
  ValueType Type = i32;
  string PrintMethod = "printThumbLdrLabelOperand";
  string EncoderMethod = "getAddrModePCOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ThumbMemPC;
  string NAME = ?;
}
def t_addrmode_rr {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbAddrModeRR";
  ValueType Type = i32;
  string PrintMethod = "printThumbAddrModeRROperand";
  string EncoderMethod = "getThumbAddrModeRegRegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_addrmode_rr_asm_operand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectThumbAddrModeRR";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t_addrmode_rr_asm_operand {	// AsmOperandClass
  string Name = "MemThumbRR";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t_addrmode_rrs1 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbAddrModeRR";
  ValueType Type = i32;
  string PrintMethod = "printThumbAddrModeRROperand";
  string EncoderMethod = "getThumbAddrModeRegRegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_addrmode_rr_asm_operand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectThumbAddrModeRI5S1";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t_addrmode_rrs2 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbAddrModeRR";
  ValueType Type = i32;
  string PrintMethod = "printThumbAddrModeRROperand";
  string EncoderMethod = "getThumbAddrModeRegRegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_addrmode_rr_asm_operand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectThumbAddrModeRI5S2";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t_addrmode_rrs4 {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbAddrModeRR";
  ValueType Type = i32;
  string PrintMethod = "printThumbAddrModeRROperand";
  string EncoderMethod = "getThumbAddrModeRegRegOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_addrmode_rr_asm_operand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectThumbAddrModeRI5S4";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t_addrmode_sp {	// DAGOperand Operand MemOperand ComplexPattern
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbAddrModeSP";
  ValueType Type = i32;
  string PrintMethod = "printThumbAddrModeSPOperand";
  string EncoderMethod = "getAddrModeThumbSPOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_MEMORY";
  dag MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_addrmode_sp_asm_operand;
  ValueType Ty = i32;
  int NumOperands = 2;
  string SelectFunc = "SelectThumbAddrModeSP";
  list<SDNode> RootNodes = [];
  list<SDNodeProperty> Properties = [];
  int Complexity = -1;
  string NAME = ?;
}
def t_addrmode_sp_asm_operand {	// AsmOperandClass
  string Name = "MemThumbSPI";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t_adrlabel {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printAdrLabelOperand<2>";
  string EncoderMethod = "getThumbAdrLabelOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = UnsignedOffset_b8s2;
  string NAME = ?;
}
def t_brtarget {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbBROperand";
  ValueType Type = OtherVT;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getThumbBRTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  string NAME = ?;
}
def t_imm0_1020s4 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printThumbS4ImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_imm0_1020s4_asmoperand;
  string NAME = ?;
}
def t_imm0_1020s4_asmoperand {	// AsmOperandClass
  string Name = "Imm0_1020s4";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t_imm0_508s4 {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printThumbS4ImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_imm0_508s4_asmoperand;
  string NAME = ?;
}
def t_imm0_508s4_asmoperand {	// AsmOperandClass
  string Name = "Imm0_508s4";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def t_imm0_508s4_neg {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_IMMEDIATE";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = t_imm0_508s4_neg_asmoperand;
  string NAME = ?;
}
def t_imm0_508s4_neg_asmoperand {	// AsmOperandClass
  string Name = "Imm0_508s4Neg";
  list<AsmOperandClass> SuperClasses = [];
  string PredicateMethod = ?;
  string RenderMethod = ?;
  string ParserMethod = ?;
  string DiagnosticType = "";
  string DiagnosticString = "";
  bit IsOptional = 0;
  string DefaultMethod = ?;
  string NAME = ?;
}
def tblockaddress {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::TargetBlockAddress";
  string SDClass = "BlockAddressSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def tcGPR {	// DAGOperand RegisterClass
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  string Namespace = "ARM";
  RegInfoByHwMode RegInfos = ?;
  list<ValueType> RegTypes = [i32];
  int Size = 0;
  int Alignment = 32;
  int CopyCost = 1;
  dag MemberList = (add R0, R1, R2, R3, R12);
  RegAltNameIndex altNameIndex = NoRegAltName;
  bit isAllocatable = 1;
  list<dag> AltOrders = [(and tcGPR, tGPR)];
  code AltOrderSelect = [{
      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }];
  int AllocationPriority = 0;
  string DiagnosticType = "";
  string DiagnosticString = "";
  string NAME = ?;
}
def tconstpool {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::TargetConstantPool";
  string SDClass = "ConstantPoolSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def texternalsym {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::TargetExternalSymbol";
  string SDClass = "ExternalSymbolSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def tframeindex {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::TargetFrameIndex";
  string SDClass = "FrameIndexSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def tglobaladdr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::TargetGlobalAddress";
  string SDClass = "GlobalAddressSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def tglobaltlsaddr {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::TargetGlobalTLSAddress";
  string SDClass = "GlobalAddressSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def thumb_bcc_target {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbBCCTargetOperand";
  ValueType Type = OtherVT;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getThumbBCCTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ThumbBranchTarget;
  string NAME = ?;
}
def thumb_bl_target {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbBLTargetOperand";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getThumbBLTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ThumbBranchTarget;
  string NAME = ?;
}
def thumb_blx_target {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbBLXOffset";
  ValueType Type = i32;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getThumbBLXTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ARMBranchTarget;
  string NAME = ?;
}
def thumb_br_target {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = OtherVT;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getThumbBranchTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ThumbBranchTarget;
  string NAME = ?;
}
def thumb_cb_target {	// DAGOperand Operand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "DecodeThumbCmpBROperand";
  ValueType Type = OtherVT;
  string PrintMethod = "printOperand";
  string EncoderMethod = "getThumbCBTargetOpValue";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_PCREL";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ThumbBranchTarget;
  string NAME = ?;
}
def thumb_imm256_510_addend {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def thumb_immshifted {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (imm);
  code PredicateCode = [{
  return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def thumb_immshifted_shamt {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
  return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def thumb_immshifted_val {	// SDNodeXForm
  SDNode Opcode = imm;
  code XFormFunction = [{
  unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
  return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
}];
  string NAME = ?;
}
def timm {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::TargetConstant";
  string SDClass = "ConstantSDNode";
  SDTypeProfile TypeProfile = SDTIntLeaf;
  string NAME = ?;
}
def tjumptable {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::TargetJumpTable";
  string SDClass = "JumpTableSDNode";
  SDTypeProfile TypeProfile = SDTPtrLeaf;
  string NAME = ?;
}
def token {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 248;
  string NAME = ?;
}
def top16Zero {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (i32 rGPR:$src);
  code PredicateCode = [{
  return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
  }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def trap {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ISD::TRAP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTNone;
  string NAME = ?;
}
def trunc {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::TRUNCATE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntTruncOp;
  string NAME = ?;
}
def truncstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (unindexedstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = 1;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def truncstoref32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (truncstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = f32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def truncstoref64 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (truncstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = f64;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def truncstorei16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (truncstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def truncstorei32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (truncstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def truncstorei8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (truncstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def truncstorevi16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (truncstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i16;
  string NAME = ?;
}
def truncstorevi32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (truncstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i32;
  string NAME = ?;
}
def truncstorevi8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (truncstore node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i8;
  string NAME = ?;
}
def type0 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_0";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 0;
  string NAME = ?;
}
def type1 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_1";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 0;
  string NAME = ?;
}
def type2 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_2";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 0;
  string NAME = ?;
}
def type3 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_3";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 0;
  string NAME = ?;
}
def type4 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_4";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 0;
  string NAME = ?;
}
def type5 {	// DAGOperand Operand TypedOperand
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = untyped;
  string PrintMethod = "printOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_GENERIC_5";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = ImmAsmOperand;
  bit IsPointer = 0;
  string NAME = ?;
}
def udiv {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::UDIV";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def udivrem {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::UDIVREM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinHiLoOp;
  string NAME = ?;
}
def uint_to_fp {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::UINT_TO_FP";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntToFPOp;
  string NAME = ?;
}
def umax {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::UMAX";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def umin {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::UMIN";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def umullohi {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative];
  string Opcode = "ISD::UMUL_LOHI";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinHiLoOp;
  string NAME = ?;
}
def unalignednontemporalstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (nontemporalstore node:$val, node:$ptr);
  code PredicateCode = [{
  StoreSDNode *St = cast<StoreSDNode>(N);
  return St->getAlignment() < St->getMemoryVT().getStoreSize();
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def undef {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::UNDEF";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTUNDEF;
  string NAME = ?;
}
def unindexedload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (ld node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = 1;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def unindexedstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (st node:$val, node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = 1;
  bit IsAtomic = ?;
  bit IsUnindexed = 1;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def unknown {	// unknown_class
  string NAME = ?;
}
def untyped {	// ValueType
  string Namespace = "MVT";
  int Size = 8;
  int Value = 112;
  string NAME = ?;
}
def urem {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::UREM";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def v1024i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 1024;
  int Value = 23;
  string NAME = ?;
}
def v128i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 21;
  string NAME = ?;
}
def v128i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 2048;
  int Value = 40;
  string NAME = ?;
}
def v128i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 1024;
  int Value = 31;
  string NAME = ?;
}
def v16f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 92;
  string NAME = ?;
}
def v16i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 16;
  int Value = 18;
  string NAME = ?;
}
def v16i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 37;
  string NAME = ?;
}
def v16i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 45;
  string NAME = ?;
}
def v16i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 1024;
  int Value = 52;
  string NAME = ?;
}
def v16i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 28;
  string NAME = ?;
}
def v1f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 88;
  string NAME = ?;
}
def v1f64 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 93;
  string NAME = ?;
}
def v1i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 1;
  int Value = 14;
  string NAME = ?;
}
def v1i128 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 54;
  string NAME = ?;
}
def v1i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 16;
  int Value = 33;
  string NAME = ?;
}
def v1i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 41;
  string NAME = ?;
}
def v1i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 48;
  string NAME = ?;
}
def v1i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 8;
  int Value = 24;
  string NAME = ?;
}
def v256i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 2048;
  int Value = 32;
  string NAME = ?;
}
def v2f16 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 85;
  string NAME = ?;
}
def v2f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 89;
  string NAME = ?;
}
def v2f64 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 94;
  string NAME = ?;
}
def v2i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 2;
  int Value = 15;
  string NAME = ?;
}
def v2i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 34;
  string NAME = ?;
}
def v2i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 42;
  string NAME = ?;
}
def v2i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 49;
  string NAME = ?;
}
def v2i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 16;
  int Value = 25;
  string NAME = ?;
}
def v32i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 19;
  string NAME = ?;
}
def v32i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 38;
  string NAME = ?;
}
def v32i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 1024;
  int Value = 46;
  string NAME = ?;
}
def v32i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 2048;
  int Value = 53;
  string NAME = ?;
}
def v32i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 29;
  string NAME = ?;
}
def v4f16 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 86;
  string NAME = ?;
}
def v4f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 90;
  string NAME = ?;
}
def v4f64 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 95;
  string NAME = ?;
}
def v4i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 4;
  int Value = 16;
  string NAME = ?;
}
def v4i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 35;
  string NAME = ?;
}
def v4i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 43;
  string NAME = ?;
}
def v4i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 50;
  string NAME = ?;
}
def v4i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 32;
  int Value = 26;
  string NAME = ?;
}
def v512i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 22;
  string NAME = ?;
}
def v64i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 20;
  string NAME = ?;
}
def v64i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 1024;
  int Value = 39;
  string NAME = ?;
}
def v64i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 2048;
  int Value = 47;
  string NAME = ?;
}
def v64i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 30;
  string NAME = ?;
}
def v8f16 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 87;
  string NAME = ?;
}
def v8f32 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 91;
  string NAME = ?;
}
def v8f64 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 96;
  string NAME = ?;
}
def v8i1 {	// ValueType
  string Namespace = "MVT";
  int Size = 8;
  int Value = 17;
  string NAME = ?;
}
def v8i16 {	// ValueType
  string Namespace = "MVT";
  int Size = 128;
  int Value = 36;
  string NAME = ?;
}
def v8i32 {	// ValueType
  string Namespace = "MVT";
  int Size = 256;
  int Value = 44;
  string NAME = ?;
}
def v8i64 {	// ValueType
  string Namespace = "MVT";
  int Size = 512;
  int Value = 51;
  string NAME = ?;
}
def v8i8 {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 27;
  string NAME = ?;
}
def vAny {	// ValueType
  string Namespace = "MVT";
  int Size = 0;
  int Value = 251;
  string NAME = ?;
}
def variable_ops {
  string NAME = ?;
}
def vector_extract {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::EXTRACT_VECTOR_ELT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_874;
  string NAME = ?;
}
def vector_extract_subvec {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::EXTRACT_SUBVECTOR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_878;
  string NAME = ?;
}
def vector_insert {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::INSERT_VECTOR_ELT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = anonymous_875;
  string NAME = ?;
}
def vector_shuffle {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::VECTOR_SHUFFLE";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTVecShuffle;
  string NAME = ?;
}
def vfp_f16imm {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = f16;
  string PrintMethod = "printFPImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = FPImmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (f16 fpimm);
  code PredicateCode = [{
      return ARM_AM::getFP16Imm(N->getValueAPF()) != -1;
    }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = anonymous_3715;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def vfp_f32imm {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = f32;
  string PrintMethod = "printFPImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = FPImmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (f32 fpimm);
  code PredicateCode = [{
      return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
    }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = anonymous_3716;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def vfp_f64imm {	// DAGOperand Operand SDPatternOperator PatFrag PatLeaf
  string OperandNamespace = "MCOI";
  string DecoderMethod = "";
  ValueType Type = f64;
  string PrintMethod = "printFPImmOperand";
  string EncoderMethod = "";
  bit hasCompleteDecoder = 1;
  string OperandType = "OPERAND_UNKNOWN";
  dag MIOperandInfo = (ops);
  code MCOperandPredicate = ?;
  AsmOperandClass ParserMatchClass = FPImmOperand;
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (f64 fpimm);
  code PredicateCode = [{
      return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
    }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = anonymous_3717;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def vnegd {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$in);
  dag Fragment = (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def vnegq {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$in);
  dag Fragment = (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def vnot {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$in);
  dag Fragment = (xor node:$in, immAllOnesV);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def vnotd {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$in);
  dag Fragment = (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def vnotq {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$in);
  dag Fragment = (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)));
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def vselect {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::VSELECT";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTVSelect;
  string NAME = ?;
}
def vt {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::VALUETYPE";
  string SDClass = "VTSDNode";
  SDTypeProfile TypeProfile = SDTOther;
  string NAME = ?;
}
def vtFP {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (vt);
  code PredicateCode = [{ return N->getVT().isFloatingPoint(); }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def vtInt {	// SDPatternOperator PatFrag PatLeaf
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops);
  dag Fragment = (vt);
  code PredicateCode = [{ return N->getVT().isInteger(); }];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def win__chkstk {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect];
  string Opcode = "ARMISD::WIN__CHKSTK";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTNone;
  string NAME = ?;
}
def win__dbzchk {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPHasChain, SDNPSideEffect, SDNPOutGlue];
  string Opcode = "ARMISD::WIN__DBZCHK";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDT_WIN__DBZCHK;
  string NAME = ?;
}
def word_alignedload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (load node:$ptr);
  code PredicateCode = [{
  return cast<LoadSDNode>(N)->getAlignment() == 4;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def word_alignedstore {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$val, node:$ptr);
  dag Fragment = (store node:$val, node:$ptr);
  code PredicateCode = [{
  return cast<StoreSDNode>(N)->getAlignment() == 4;
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def x86mmx {	// ValueType
  string Namespace = "MVT";
  int Size = 64;
  int Value = 109;
  string NAME = ?;
}
def xor {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [SDNPCommutative, SDNPAssociative];
  string Opcode = "ISD::XOR";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntBinOp;
  string NAME = ?;
}
def xor_su {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$lhs, node:$rhs);
  dag Fragment = (xor node:$lhs, node:$rhs);
  code PredicateCode = [{
  return N->hasOneUse();
}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = ?;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def zero_reg {
  string NAME = ?;
}
def zext {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ZERO_EXTEND";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTIntExtendOp;
  string NAME = ?;
}
def zext_invec {	// SDPatternOperator SDNode
  list<SDNodeProperty> Properties = [];
  string Opcode = "ISD::ZERO_EXTEND_VECTOR_INREG";
  string SDClass = "SDNode";
  SDTypeProfile TypeProfile = SDTExtInvec;
  string NAME = ?;
}
def zextload {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (unindexedload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = 1;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def zextloadi1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (zextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i1;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def zextloadi16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (zextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i16;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def zextloadi32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (zextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i32;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def zextloadi8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (zextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = i8;
  ValueType ScalarMemoryVT = ?;
  string NAME = ?;
}
def zextloadvi1 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (zextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i1;
  string NAME = ?;
}
def zextloadvi16 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (zextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i16;
  string NAME = ?;
}
def zextloadvi32 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (zextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i32;
  string NAME = ?;
}
def zextloadvi8 {	// SDPatternOperator PatFrag
  list<SDNodeProperty> Properties = [];
  dag Operands = (ops node:$ptr);
  dag Fragment = (zextload node:$ptr);
  code PredicateCode = [{}];
  code ImmediateCode = [{}];
  SDNodeXForm OperandTransform = NOOP_SDNodeXForm;
  bit IsLoad = 1;
  bit IsStore = ?;
  bit IsAtomic = ?;
  bit IsUnindexed = ?;
  bit IsNonExtLoad = ?;
  bit IsAnyExtLoad = ?;
  bit IsSignExtLoad = ?;
  bit IsZeroExtLoad = ?;
  bit IsTruncStore = ?;
  bit IsAtomicOrderingMonotonic = ?;
  bit IsAtomicOrderingAcquire = ?;
  bit IsAtomicOrderingRelease = ?;
  bit IsAtomicOrderingAcquireRelease = ?;
  bit IsAtomicOrderingSequentiallyConsistent = ?;
  bit IsAtomicOrderingAcquireOrStronger = ?;
  bit IsAtomicOrderingReleaseOrStronger = ?;
  ValueType MemoryVT = ?;
  ValueType ScalarMemoryVT = i8;
  string NAME = ?;
}